CTNF 18/585,393 CTNF 89904 DETAILED ACTION 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Examiner Notes Examiner cites particular columns and line numbers in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner. 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Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-23-aia AIA The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. 07-21-aia AIA Claim s 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Siddappa et al. (US 20210034416) in view of Wong et al. (US 20140317316) . As per claim 1, Siddappa teaches the invention substantially as claimed including a method for scheduling preemption in a multi-core system ([0006], cache-aware task scheduling in a multi-processing environment comprising a cache memory, [and] a multi-core processor; and [0019], method includes transmitting, by the source processing core, information related to the decision data to the second list using an interrupt), the multi-core system comprising a main processor ([0040], multi-core processor 202 may include a plurality of cores such as at least one source processing core 202 a ) , an auxiliary processor ([0040], multi-core processor includes ... at least one destination processing core) , and a shared memory between the main processor and the auxiliary processor ([0039], apparatus 200 include a multi-core processor 202 and a cache memory 204. The cache memory 204 may include a plurality of memory blocks; and [0046], cache memory 204 can be the same for the source processing core 202 a and destination processing core 202 b ) , the method comprising: generating, by the main processor during an execution of an operating system, a plurality of task requests ([0033], steps for adding activities to the ready list can include removing activities from a suspended list, changing the state of an activity to the READY state, adding an activity to a core specific READY list and triggering an interrupt if required; [0034], source processing core may remove activities from the suspended list; and [0041], scheduler 208 can be a part of an Operating System (OS) or a Real Time Operating System (RTOS) for controlling task scheduling in the plurality of core) , each task request corresponding to a job to be executed by the auxiliary processor ([0032], the steps for adding activities (e.g., tasks or jobs) to a ready list can include removing activities from a suspended list, changing the state of the activity to a READY state and then adding the activity to a ready list; and [0045], the schedule assist list may include scheduling decisions that are made in the source processing core 202 a and passed on to the destination processing core 202 b. The information shared across cores in such cases can be a TMU pointer or a bitmap indicating appropriate TMU resource) and having a respective priority level ([0011], decision data can be the priority of the task and the higher priority task may need to get scheduled; and [0049], the source processing core 202 a of the apparatus 200 may be configured to analyze decision data in the collected information related to at least one of the task, the event group, the signal data, and the queue. The decision data can be a priority (i.e., a score) of the task, and the information collected can be related to the task and the decision data (i.e., a priority/score)) ; storing, by the main processor, the plurality of task requests in the shared memory ([0044], Whenever activities (e.g., tasks) are to be partitioned across cores in the multi-core processor, the lookup table may be used to determine the assignment of the tasks to the cores 202 a and 202 b ... the apparatus 200 may store a plurality of lists such as first list, a second list, a third list, etc. The first list, the second list, the third list can be at least one of, but not limited to, an entity suspend list, a scheduler assist list, and a task ready list, respectively; and [0046], entity suspend list can be a look up table); selecting, by the main processor, a first task request from the plurality of task requests stored in the shared memory with a highest priority level ([0035], the destination processing core may get a highest READY priority bit from the priority bitmap; [0064], adding, by the source processing core 202 a, a task stored in a first list to a second list associated with the scheduler 208 of the destination processing core 202 b, based on an decision data (e.g., analyzed decision data); Examiner Note: Siddappa’s decision data includes a task priority: [0049], decision data can be a priority (i.e., a score) of the task ; and [0080], the source processing core 202 a may enable a bit in the reserved area such as look up table, during making the task ready (i.e., bits marked as 1 are enabled). At a second step, the destination processing cores 202 b, may access the available highest priority task stored in the lookup table and may disable a highest priority bit ) ; communicating, by the main processor, the first task request to the auxiliary processor ([0044], the scheduler assist list may include scheduling decisions made in the source processing core 202 a and can be passed on to the destination processing core 202 b before triggering interrupts; and [0049], the source processing core 202 a of the apparatus 200 is configured to add an activity (e.g., a task) stored in the entity suspend list (e.g., a first list) to a scheduler assist list (e.g., a second list) associated with the scheduler 208 of a destination processing core 202 b, based on the analyzed decision data...the source processing core 202 a of the apparatus 200 may be configured to transmit the information related to the decision data using an interrupt, to the scheduler assist list associated with the scheduler 208 of the destination processing core 202) , wherein the communicating comprises: communicating the respective priority level of the first task request to the auxiliary processor ([0035], the destination processing core may get a highest READY priority bit from the priority bitmap; and [0064], adding, by the source processing core 202 a, a task stored in a first list to a second list associated with the scheduler 208 of the destination processing core 202 b, based on an decision data (e.g., analyzed decision data); Examiner Note: Siddappa’s decision data includes a task priority: [0049], decision data can be a priority (i.e., a score) of the task) ) , storing information related to the first task request in the shared memory ([0044], Whenever activities (e.g., tasks) are to be partitioned across cores in the multi-core processor, the lookup table may be used to determine the assignment of the tasks to the cores 202 a and 202 b ... the apparatus 200 may store a plurality of lists such as first list, a second list, a third list, etc. The first list, the second list, the third list can be at least one of, but not limited to, an entity suspend list, a scheduler assist list, and a task ready list, respectively; and [0046], entity suspend list can be a look up table)), and communicating an interrupt signal to the auxiliary processor as a function of the first task request ([0049], the source processing core 202 a of the apparatus 200 may be configured to transmit the information related to the decision data using an interrupt, to the scheduler assist list associated with the scheduler 208 of the destination processing core 202); suspending, by the auxiliary processor, an execution of a current task in response to receiving the interrupt signal ([0035], the destination processing core may get a highest READY priority bit from the priority bitmap; and [0074], if the priority score in the priority bitmap is more for the upcoming highest priority task, then the currently running high priority task would be replaced by the most highest priority task (i.e. upcoming task) and would be executed) ; retrieving, by the auxiliary processor, the respective priority level of the first task request ([0035], the destination processing core may get a highest READY priority bit from the priority bitmap; and [0074], if the priority score in the priority bitmap is more for the upcoming highest priority task, then the currently running high priority task would be replaced by the most highest priority task (i.e. upcoming task) and would be executed); adding, by the auxiliary processor, the first task request ([0012], destination processing core may store the information in the first list/second list in response to receipt of the interrupt. The interrupt would be triggered to indicate to the destination core about a possible change in scheduling scenario if a task of higher priority for that core becomes READY) ; and executing, by the auxiliary processor, a task from the execution queue having a highest priority ([0033], a scheduler on a destination core for which a new activity became ready may retrieve the highest READY activity from the ready list and allow the retrieved activity to execute; and [0034], if an activity has been executed by a destination core with a priority 10 (P10), and an activity of high priority with a priority 5 (P5) is in the ready list, then preemption along with interrupts may be required). Siddappa fails to specifically teach, adding, by the auxiliary processor, the first task request and its respective priority level to an execution queue . However, it would have been obvious to one of ordinary skill in the art to include a priority level in the execution queue because Siddappa teaches sending a task and a priority level to a destination processing core. ([0012], destination processing core may store the information in the first list/second list in response to receipt of the interrupt. The interrupt would be triggered to indicate to the destination core about a possible change in scheduling scenario if a task of higher priority for that core becomes READY) . Furthermore, Wong teaches, adding, by the auxiliary processor, the first task request and its respective priority level to an execution queue ([0084], compute instructions include tasks as well as embedded priority and dependency information... GPU 335 schedules tasks based on the priority information so that the highest priority tasks, such as real-time tasks, are completed before tasks with lower priority that are not time-sensitive. An embodiment further includes scheduling, by the processing unit such as GPU 335, the tasks based on priority information in the compute instructions). Siddappa and Wong are analogous because they are each priority-based task scheduling including offloading tasks. Siddappa teaches a method of task scheduling including offloading tasks to managed cores. (Abstract, collect information related to a first activity and analyze the collected information to determine decision data. The information is stored in a first list of the source processing core for scheduling execution of the activity by a destination processing core to avoid cache misses. The source processing core is configured to transmit information related to the decision data using an interrupt, to a second list associated with a scheduler of the destination processing core, if the destination processing core is currently executing a second activity having a lower priority than the first activity) . Wong teaches priority based scheduling including queuing tasks and priority information to GPUs for processing. (Abstract, peripheral device firmware can determine and store compute instructions specifically for the GPU, in a command queue. The compute instructions in the command queue are understood and consumed by firmware of the GPU ; and [0084], compute instructions include tasks as well as embedded priority and dependency information... GPU 335 schedules tasks based on the priority information so that the highest priority tasks, such as real-time tasks, are completed before tasks with lower priority that are not time-sensitive. An embodiment further includes scheduling, by the processing unit such as GPU 335, the tasks based on priority information in the compute instructions) . It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention that based on the combination, the destination processor queues of Siddappa would be modified to include task priority information resulting in a system that offloads tasks including priority information. Therefore, it would have been obvious to combine the teachings of Siddappa and Wong. As per claim 2, Siddappa teaches, wherein executing, by the auxiliary processor, the task from the execution queue having the highest priority comprises retrieving information related to the task selected from the shared memory ([0049], decision data can be a priority (i.e., a score) of the task, and the information collected can be related to the task and the decision data (i.e., a priority/score). In an embodiment, the source processing core 202 a of the apparatus 200 is configured to add an activity (e.g., a task) stored in the entity suspend list (e.g., a first list) to a scheduler assist list (e.g., a second list) associated with the scheduler 208 of a destination processing core 202 b, based on the analyzed decision data...the source processing core 202 a of the apparatus 200 may be configured to transmit the information related to the decision data using an interrupt, to the scheduler assist list associated with the scheduler 208 of the destination processing core 202 b ; and [0080], the source processing core 202 a may enable a bit in the reserved area such as look up table, during making the task ready (i.e., bits marked as 1 are enabled). At a second step, the destination processing cores 202 b, may access the available highest priority task stored in the lookup table and may disable a highest priority bit). As per claim 3, Siddappa teaches, wherein the communicating, by the main processor, the first task request to the auxiliary processor is in response to an availability of a slot in the shared memory ([0048], the lookup table has a reserved memory equal to a cache line size multiplied by ‘n’, where ‘n’ is 1 or greater... The reserved memory may be equally divided across all the cores in an SMP cluster; and [0080], the source processing core 202 a may enable a bit in the reserved area such as look up table, during making the task ready (i.e., bits marked as 1 are enabled). At a second step, the destination processing cores 202 b, may access the available highest priority task stored in the lookup table and may disable a highest priority bit). As per claim 4, Siddappa teaches, wherein storing information related to the first task request in the shared memory comprises storing the information in a dedicated slot of the shared memory associated with a priority level of the first task request ([0080], the source processing core 202 a may enable a bit in the reserved area such as look up table, during making the task ready (i.e., bits marked as 1 are enabled). At a second step, the destination processing cores 202 b, may access the available highest priority task stored in the lookup table and may disable a highest priority bit). As per claim 5, Siddappa teaches, wherein executing, by the auxiliary processor, the task from the execution queue having the highest priority comprises retrieving information related to the task selected from the shared memory ([0035], the destination processing core may get a highest READY priority bit from the priority bitmap; and [0064], adding, by the source processing core 202 a, a task stored in a first list to a second list associated with the scheduler 208 of the destination processing core 202 b, based on an decision data (e.g., analyzed decision data); Examiner Note: Siddappa’s decision data includes a task priority: [0049], decision data can be a priority (i.e., a score) of the task) ; and [0080], the source processing core 202 a may enable a bit in the reserved area such as look up table, during making the task ready (i.e., bits marked as 1 are enabled). At a second step, the destination processing cores 202 b, may access the available highest priority task stored in the lookup table and may disable a highest priority bit) , and wherein the retrieving information related to the task selected from the shared memory is in response to determining the dedicated slot of the shared memory associated with the priority level of the task selected ([0080], the source processing core 202 a may enable a bit in the reserved area such as look up table, during making the task ready (i.e., bits marked as 1 are enabled). At a second step, the destination processing cores 202 b, may access the available highest priority task stored in the lookup table and may disable a highest priority bit). As per claim 6, Siddappa teaches, wherein the communicating the respective priority level of the first task request to the auxiliary processor comprises: writing in a register of a mailbox coupled between the main processor and the auxiliary processor; or writing in a dedicated slot of the shared memory ([0049], the source processing core 202 a of the apparatus 200 may be configured to transmit the information related to the decision data using an interrupt, to the scheduler assist list associated with the scheduler 208 of the destination processing core 202) . As per claim 7, Siddappa teaches, w herein communicating the interrupt signal to the auxiliary processor comprises: communicating the interrupt signal by the mailbox; or communicating the interrupt signal through a direct interrupt line between the main processor and the auxiliary processor ([0046], information stored in the entity suspend list can be used by the destination processing core 202 b as directly consumable information and also may generate data from the received information to consume the generated data in later stages; [0047], the directly consumable data such as a signal or signal data includes information sent with a signal mask that contains a few ON bits. The data type of the ON bits (e.g., a 32 bit unsigned integer) can be consumed directly by an asynchronous signal handler in the associated task contexts; [0048], Examples of the directly consumable information can be the task, the event group (e.g., a plurality of events), and the signal data. Examples of information that can be consumed at later stages include, a queue, and so on, by generating data from the information; and [0049], the source processing core 202 a of the apparatus 200 may be configured to transmit the information related to the decision data using an interrupt, to the scheduler assist list associated with the scheduler 208 of the destination processing core 202). As per claim 8, Siddappa teaches, wherein retrieving, by the auxiliary processor, the respective priority level of the first task request from the shared memory comprises retrieving, by the auxiliary processor, the respective priority level by reading the register of the mailbox or by reading from the dedicated slot of the shared memory ([0035], the destination processing core may get a highest READY priority bit from the priority bitmap; and [0064], adding, by the source processing core 202 a, a task stored in a first list to a second list associated with the scheduler 208 of the destination processing core 202 b, based on an decision data (e.g., analyzed decision data); Examiner Note: Siddappa’s decision data includes a task priority: [0049], decision data can be a priority (i.e., a score) of the task) ; and [0080], the source processing core 202 a may enable a bit in the reserved area such as look up table, during making the task ready (i.e., bits marked as 1 are enabled). At a second step, the destination processing cores 202 b, may access the available highest priority task stored in the lookup table and may disable a highest priority bit). As per claim 9, this is the “multi-core system claim” corresponding to claim 1 and is rejected for the same reasons. The same motivation used in the rejection of claim 1 is applicable to the instant claim. As per claim 10, this claim is similar to claim 2 and is rejected for the same reasons. As per claim 11, this claim is similar to claim 3 and is rejected for the same reasons. As per claim 12, this claim is similar to claim 4 and is rejected for the same reasons. As per claim 13, this claim is similar to claim 5 and is rejected for the same reasons. As per claim 14, this claim is similar to claim 6 and is rejected for the same reasons. As per claim 15, this claim is similar to claim 7 and is rejected for the same reasons. As per claim 16, this claim is similar to claim 8 and is rejected for the same reasons. As per claim 17, this is the “non-transitory computer-readable media claim” corresponding to claim 1 and is rejected for the same reasons. The same motivation used in the rejection of claim 1 is applicable to the instant claim. As per claim 18, this claim is similar to claim 2 and is rejected for the same reasons. As per claim 19, this claim is similar to claim 3 and is rejected for the same reasons. As per claim 20, this claim is similar to claim 4 and is rejected for the same reasons. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to MELISSA A HEADLY whose telephone number is (571)272-1972. The examiner can normally be reached Monday- Friday 9-5:30pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MELISSA A HEADLY/Examiner, Art Unit 2197 Application/Control Number: 18/585,393 Page 2 Art Unit: 2197 Application/Control Number: 18/585,393 Page 3 Art Unit: 2197 Application/Control Number: 18/585,393 Page 4 Art Unit: 2197 Application/Control Number: 18/585,393 Page 5 Art Unit: 2197 Application/Control Number: 18/585,393 Page 6 Art Unit: 2197 Application/Control Number: 18/585,393 Page 7 Art Unit: 2197 Application/Control Number: 18/585,393 Page 8 Art Unit: 2197 Application/Control Number: 18/585,393 Page 9 Art Unit: 2197 Application/Control Number: 18/585,393 Page 10 Art Unit: 2197 Application/Control Number: 18/585,393 Page 11 Art Unit: 2197 Application/Control Number: 18/585,393 Page 13 Art Unit: 2197 Application/Control Number: 18/585,393 Page 14 Art Unit: 2197 Application/Control Number: 18/585,393 Page 15 Art Unit: 2197
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