DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is in responsive to communication(s): original application filed on 02/23/2024, said application claims a priority filing date of 05/12/2023. Claims 1-15 are pending. Claims 1, 10, and 12 are independent.
Specification
The disclosure is objected to because of the following informalities:
in ¶ [0011], "… outputs a signal having the frequency of the sine wave as the center frequency as a microwave pulse …" appears to be "… outputs a signal having the frequency of the sine wave as the center frequency of a microwave pulse …";
in ¶ [0019], "… includes an amplitude set by the pulse waveform setting signal 115, at the input timing of the pulse trigger signal 114. ," appears to be "… includes an amplitude set by the pulse waveform setting signal 115, at the input timing of the pulse trigger signal 114."; i.e., remove an extra space and a comma at the end of paragraph.
in ¶ [0028], "… The logic circuit 203 also outputs modulation signal 214 to frequency generator201 during the period based on signal 116, based on the phase setting signal 117 and frequency offset setting signal 118 …" appears to be "… The logic circuit 203 also outputs modulation signal 214 to frequency generator201 during the period based on pulse width setting signal 116, the phase setting signal 117 and frequency offset setting signal 118 …";
in ¶ [0060], "The adder 702 adjusts the gain of the phase setting signal 117 using gain adjustment 707 and adds the differential value taken by differentiator 703 to the output of adder 702 to produce frequency modulation signal 214." appears to be "The adder 702 adjusts the gain of the phase setting signal 117 using gain adjustment 707 and adds the differential value taken by differentiator 703 to the output of multiplier 705 to produce frequency modulation signal 214." according to FIG. 7
in ¶ [0095], "… I-side ADC 1308 demodulates I demodulation signal 1317 to I demodulation data 1319 and Q-side ADC 1309 demodulates Q demodulation signal 1318 to Q demodulation data 1320 from analog to digital data" appears to be "… I-side ADC 1308 converts I demodulation signal 1317 to I demodulation data 1319 and Q-side ADC 1309 converts Q demodulation signal 1318 to Q demodulation data 1320 from analog to digital data" according to Claim 11;
in ¶ [0106], "… the phase shift between LO output sine wave 1315, LO output cosine wave 1316 and I modulation signal 1313, Q modulation signal1314 is θ …" appears to be "… the phase shift between LO output sine wave 1315, LO output cosine wave 1316 and I modulation signal 1313, Q modulation signal 1314 is θ …"; i.e., missing a space between signal and 1314;
according to ¶ [0115], "… I demodulation signal 1317 at ϕ=π/2 is in Formula 10, and Q demodulation signal 1318 at ϕ=π/2 is in Formula 11"; however, (1) both Formula 10 in ¶ [0118] and Formula 11 in ¶ [0119] are for VRQ (i.e., Q demodulation signal 1318) at ϕ=π/2; and (2) Formula 10 in ¶ [0118] is incorrect when applying ϕ=π/2 at Formula 6 in ¶ [0113] for demodulation signal 1317 (i.e., cos(ϕ)=0; sin(ϕ)=1) (NOTE: currently, Formula 10 in ¶ [0118] is the same as Formula 9 in ¶ [0117]); therefore, in ¶ [0118], "
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V
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=
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Appropriate correction is required.
Claim Objections
Claims 1-4, 6, and 9-15 are objected to because of the following informalities:
in Claim 1, lines 4-5, "… selects a quantum bit to be quantum manipulated from the quantum bit array and shifts the angular frequency …" appears to be "… selects a quantum bit to be quantum manipulated from the quantum bit array and shifts angular frequency …";
in Claim 1, lines 15-17, "… outputs a signal having the frequency of the sine wave as the center frequency as …" appears to be "… outputs a signal having the frequency of the sine wave as the center frequency of …" (see also 112 Rejections to Claim 1);
in Claim 2, lines 2-3, "… wherein the logic circuit outputs a frequency modulation signal based on the frequency of the selected quantum bit …" appears to be "… wherein the logic circuit outputs a frequency modulation signal based on the angular frequency of the selected quantum bit …";
in Claim 3, lines 2-4, "… wherein the logic circuit calculates the amount of phase shift based on the set pulse width and the frequency of the selected quantum bit …" appears to be "… wherein the logic circuit calculates an amount of phase shift based on the set pulse width and the angular frequency of the selected quantum bit …";
in Claim 4, lines 2-6, "… wherein the logic circuit outputs … based on the frequency of the selected quantum bit, and then outputs … based on the frequency of the selected quantum bit multiplied by a negative value" appears to be "… wherein the logic circuit outputs … based on the angular frequency of the selected quantum bit, and then outputs … based on the angular frequency of the selected quantum bit multiplied by a negative value" (see also 112 Rejections to Claim 4);
in Claim 6, lines 3-7, "… the frequency of the selected quantum bit and the frequency offset signal of the frequency of the selected quantum bit multiplied by a negative value, and outputs … based on the acquired frequency offset signal" appears to be "… the angular frequency of the selected quantum bit and the frequency offset setting signal of the angular frequency of the selected quantum bit multiplied by a negative value, and outputs … based on the acquired frequency offset setting signal" (see also 112 Rejections to Claim 6);
in Claim 9, lines 2-7, "… wherein the converters comprises … having the frequency of the sine wave as the center frequency as …" appears to be "… wherein the converter comprises … having the frequency of the sine wave as the center frequency of …" (see also 112 Rejections to Claim 9);
in Claim 10, lines 3-5, "… selects a quantum bit to be quantum manipulated from the quantum bit array and shifts the angular frequency …" appears to be "… selects a quantum bit to be quantum manipulated from the quantum bit array and shifts angular frequency …";
in Claim 10, lines 14-16, "… a DAC that converts the I modulation data and Q modulation data from digital data to analog and outputs I modulation signal and Q modulation signal …" appears to be "… a DAC that converts the I modulation data and the Q modulation data from digital data to analog signal and outputs I modulation signal and Q modulation signal …";
in Claim 11, lines 7-9, "… an ADC that converts the I demodulation signal and the Q demodulation signal from analog to digital data and outputs I demodulation data and Q demodulation data …" appears to be "… an ADC that converts the I demodulation signal and the Q demodulation signal from the analog signal to the digital data and outputs I demodulation data and Q demodulation data …" (see also Claim Objections to Claim 10 above);
in Claim11, lines 10-13, "… a calibration circuit that acquires the I demodulation data and Q demodulation data, calculates the IQ gain error and phase error, and outputs the IQ correction data to the logic circuit …" appears to be "… a calibration circuit that acquires the I demodulation data and the Q demodulation data, calculates IQ gain error and phase error, and outputs IQ correction data to the logic circuit …";
in Claim 12, lines 15-17, "… outputs a signal having the frequency of the sine wave as the center frequency as …" appears to be "… outputs a signal having the frequency of the sine wave as the center frequency of …" (see also 112 Rejections to Claim 12);
in Claim 13, lines 2-3, "… wherein the logic circuit outputs a frequency modulation signal based on the frequency of the selected quantum bit …" appears to be "… wherein the logic circuit outputs a frequency modulation signal based on the angular frequency of the selected quantum bit …";
in Claim 14, lines 2-4, "… wherein the logic circuit calculates the amount of phase shift based on the set pulse width and the selected quantum bit frequency …" appears to be "… wherein the logic circuit calculates an amount of phase shift based on the set pulse width and the angular frequency of the selected quantum bit …";
in Claim 15, lines 2-6, "… wherein the logic circuit outputs … based on the frequency of the selected quantum bit, and then outputs … based on the frequency of the selected quantum bit multiplied by a negative value" appears to be "… wherein the logic circuit outputs … based on the angular frequency of the selected quantum bit, and then outputs … based on the angular frequency of the selected quantum bit multiplied by a negative value" (see also 112 Rejections to Claim 4).
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation "… outputs a microwave pulse with a set pulse width and pulse amplitude … outputs a signal having the frequency of the sine wave as the center frequency as a microwave pulse …" in lines 7-17, which rendering the claim indefinite because it is unclear whether .
Claim 1 recites the limitation "… a quantum bit array with " in lines 2-22, which rendering the claim indefinite because (1) .
Claims 2-9 are rejected for fully incorporating the deficiency of their respective base claims.
Claim 2 recites the limitation "… the frequency generator outputs a sine wave based on the frequency modulation signal" in lines 4-5, which rendering the claim indefinite because ".
Claims 3-9 are rejected for fully incorporating the deficiency of their respective base claims.
Claim 3 recites the limitation "... outputs a frequency modulation signal based on the amount of phase shift" in lines 4-5, which rendering the claim indefinite because ".
Claim 4 recites the limitation "… wherein the logic circuit outputs a frequency modulation signal based on …, and then outputs a frequency modulation signal based on … multiplied by a negative value …" in lines 2-6, which rendering the claim indefinite because ".
Claim 5 recites the limitation "the phase setting signal" in line 2. There is insufficient antecedent basis for this limitation in the claim.
Claim 5 recites the limitation "… the set phase minus the phase shift amount …" in line . There is insufficient antecedent basis for limitations "the set phase" and "the phase shift amount" in the claim (NOTE: "the amount of phase shift" is recited in Claim 3 and not in the parent Claim 2). Clarification is required.
Claim 5 recites the limitation "… outputs " in lines 4-5, which rendering the claim indefinite because ".
Claim 6 recites the limitation " the frequency offset setting signal" in line . There is insufficient antecedent basis for this limitation in the claim (see also Claim Objections to Claim 6).
Claim 7 recites the limitation "... phase correction data that corrects the frequency shift of the plurality of quantum bits in the quantum bit array, wherein the frequency generator outputs a sine wave based on the phase correction data of the selected quantum bit" in lines 3-6, which rendering the claim indefinite because ''.
Claim 9 recites the limitation "... a DAC that converts the pulse data into an analog signal, and a mixer that modulates the analog signal with the sine wave and outputs a signal having the frequency of the sine wave as the center frequency as a microwave pulse" in lines 3-7, which rendering the claim indefinite because ".
Claim 10 recites the limitation "…" in lines 10-19, which rendering the claim indefinite because (1) it is unclear .
Claim 10 recites the limitation "… a frequency generator that generates LO output sine waves and LO output cosine waves with a phase difference of 90° from each other with the frequency set by the frequency setting signal, an IQ modulator that multiplies the I modulation signal and the Q modulation signal with the LO output sine wave and the LO output cosine wave, respectively …" in lines 17-22, which rendering the claim indefinite because it is unclear which "LO output sine wave" among "LO output sine waves" is referred by "the LO output sine wave" and which "LO output cosine wave" among "LO output cosine waves" is referred by "the LO output cosine wave". Clarification is required.
Claim 10 recites the limitation "… a quantum bit array with " in lines 2-2, which rendering the claim indefinite because (1) .
Claim 11 is rejected for fully incorporating the deficiency of their respective base claims.
Claim 11 recites the limitation "… an IQ demodulator that multiplies the microwave pulse with the LO output sine wave and the LO output cosine wave and demodulates it into I demodulation signal and Q demodulation signal …" in lines 3-6, which rendering the claim indefinite because ".
Claim 12 recites the limitation "… outputs a microwave pulse that quantum manipulates a quantum bit selected from a quantum bit array … outputs a signal having the frequency of the sine wave as the center frequency as a microwave pulse …" in lines , which rendering the claim indefinite because it is unclear whether two instances of ".
Claim 12 recites the limitation "… " in lines , which rendering the claim indefinite because if ".
Claims 13-15 are rejected for fully incorporating the deficiency of their respective base claims.
Claim 13 recites the limitation "… the frequency generator outputs a sine wave based on the frequency modulation signal" in lines 4-5, which rendering the claim indefinite because ".
Claims 14-15 are rejected for fully incorporating the deficiency of their respective base claims.
Claim 14 recites the limitation "... outputs a frequency modulation signal based on the amount of phase shift" in lines 4-5, which rendering the claim indefinite because ".
Claim 15 recites the limitation "… wherein the logic circuit outputs a frequency modulation signal based on …, and then outputs a frequency modulation signal based on … multiplied by a negative value …" in lines 2-6, which rendering the claim indefinite because ".
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 5, 7, and 9-14 are rejected under 35 U.S.C. 103 as being unpatentable over Szmuk et al. (US 2022/0045666 A1, pub. date: 02/10/2022), hereinafter Szmuk in view of Negoro et al. (US 2026/0134319 A1, filed on 10/26/2022), hereinafter Negoro.
Independent Claim 1
Szmuk teaches a quantum computer (Szmuk, ¶¶ [0021]-[0024] with FIG. 1B: quantum computers operate by storing information in the form of quantum bits ("qubits") and processing those qubits via quantum gates; it is the job of the quantum controller to generate the precise series of external signals, usually pulses of electromagnetic waves and pulses of base band voltage, to perform the desired logic operations (and thus carry out the desired quantum algorithm; ¶ [0025] with FIG. 2A: a quantum orchestration platform (QOP) comprises a quantum programming subsystem 202, a quantum controller 210, front-end circuitry 254, multi-LO tone generator 222, connectivity circuitry 224, and a quantum processor 218), comprising:
a quantum bit array with multiple quantum bits (Szmuk, ¶ [0031] with 218, 226, and 228 in FIG. 2A: in general, the quantum processor 218 comprises K (an integer) quantum elements 122, which includes qubits (which could be of any type such as superconducting, spin qubits, ion trapped, etc.), and, where applicable, any other element( s) for processing quantum information, storing quantum information (e.g. storage resonator), and/or coupling outbound quantum control pulses from front-end circuitry 254 and inbound quantum control pulses to the front-end circuitry 254; the quantum processor 218 comprises 4 readout elements 226 and 4 qubits 228), a quantum bit selector that selects a quantum bit to be quantum manipulated from the quantum bit array and shifts the angular frequency, and a microwave pulse generator that has the same frequency as the selected quantum bit and outputs a microwave pulse with a set pulse width and pulse amplitude, wherein the microwave pulse generator comprises, a logic circuit that outputs pulse data of the set pulse width and pulse amplitude, a frequency generator that outputs a sine wave having the same frequency as the selected quantum bit (Szmuk, ¶¶ [0026]-[0039] with FIGS. 2A-D: the quantum programming subsystem 202 comprises circuitry operable to generate a pulse generation program and quantum machine specification 206 which configures the quantum controller 210 and includes instructions the quantum controller 210 can execute to carry out the quantum algorithm (i.e., generate the necessary outbound quantum control pulse(s)) with little or no human intervention during runtime; the quantum programming subsystem 202 is coupled to the quantum controller 210 which comprises circuitry operable to load the machine code from the programming subsystem 202, and then execute the machine code to generate the necessary outbound quantum control pulse(s) that correspond to the desired operations to be performed on the quantum processor 218 (e.g., sent to qubit(s) for manipulating a state of the qubit(s) or to readout resonator(s) for reading the state of the qubit(s), etc.) and/or process inbound pulses returning from the quantum processor 218 via front-end circuitry 254; whether to transmit one or more outbound pulse and/or characteristics of one or more outbound pulse to be transmitted may be predetermined at design time and/or may be determined during runtime; the quantum controller 210 is coupled to front-end circuitry 254; the quantum controller 210 may comprise a plurality of interconnected, but physically separate quantum control modules 250; the number of quantum control modules 250 needed for a particular quantum system may be determined based on the number of qubits of the quantum processor 218 and their architecture (tunability, connectivity, coupling elements and readout architecture); port(s) 262 represent RF output ports via which pulses are sent to qubits of the quantum processor (in the example of FIG. 2A, 262 corresponds to 2251-2254); port(s) 264 represent RF output ports via which pulses are sent to readout elements of the quantum processor (in the example of FIG. 2A, 264 corresponds to 2250); port(s) 268 represent IF input ports via which pulses to be sent to qubits of the quantum processor 218 are received from a controller module 250 (in the example of FIG. 2A, 268 corresponds to one or more of 2211-2214); port(s) 270 represent IF input ports via which pulses to be sent to readout elements of the quantum processor 218 are received from a controller module 250 (in the example of FIG. 2A, 270 corresponds to 2210); the front-end circuitry 254 is operable to receive outbound intermediate frequency (IF) pulses from quantum controller 210 via one or more ports 221, upconvert the IF pulses to RF using the local oscillator signals received via one or more LO ports 229, and output the RF pulses to quantum processor 218 via one or more output ports 225; the number of front-end-circuitry modules needed for a particular quantum system may be determined based on the number of qubits of the quantum processor 218 and their architecture (tunability, connectivity, preparation, trapping, coupling elements and readout architecture); a signal 259 from the quantum programming subsystem 202 and/or a signal 257 from the quantum controller module 250 may open and close switching elements of the circuitry 254, adjust gains within the circuitry 254, adjust coefficients of filters within the circuitry 254, and/or otherwise configure the RF, IF, and/or LO signal paths of circuitry 254; the multi-tone generator 222 is operable to generate one or more signals at one or more desired frequencies, which will typically be dictated by the particular quantum processor 218 (e.g., based on the resonant frequencies of quantum elements of the quantum processor 218); two types of outputs are provided by quantum multi-tone generator 222: (a) one or more fixed frequency continuous wave (CW) tones 223; and (b) one or more synthesized frequency signals 231; allows splitting a tone 223 into up to six LO signals using a suitable power splitting circuit, without any additional active RF components; e.g., there are eight tones with f0=500 MHz and thus the tones 223 range from 2.5 GHz to 6 GHz in steps of 500 MHz; this, together with the ability of the quantum controller 210 to accurately and dynamically control the frequencies of IF pulses it generates (see e.g., FIGS. 6A and 6B, below), enables addressing qubits within a band of frequencies that covers all currently known and proposed superconducting qubit implementations; the synthesized signal or signals 231 output an adjustable frequency RF tone within a band of frequencies that contains, e.g., the band 4 GHz to 8 GHz; this, together with the ability of the quantum controller 210 to accurately and dynamically control the frequencies of IF pulses it generates (see e.g., FIGS. 6A and 6B, below), enables, for example, addressing various readout elements that use a wide range of frequencies; of course, different and/or other frequencies can be used to accommodate different qubit implementations; the connectivity circuitry 224 is operable to couple the outputs of the multi-tone generator 222 to the inputs of the front-end circuitry 254; because the desired connections between multi-tone generator 222 and quantum processor 218 depends on the architecture and operating frequencies of the quantum processor 218, the connectivity circuitry 224 is configurable by the user to support whatever configurations users may need for their particular quantum algorithms and particular quantum processor 218; the signal 253 from the quantum programming subsystem 202 and/or a signal 255 from the quantum controller module 250 may configure signal paths within circuitry 224 (e.g., by opening and closing switches, adjusting gains, adjusting filter coefficients, and/or the like); the reference generator circuit 219 provides a reference signal that the multi-tone generator 222 splits, frequency multiplies, amplifies and filters to generate signals 2230 -2237 and 231; in an example implementation, the low-phase-noise reference generator 219 is an oven-controlled crystal oscillator (OCXO) or other low-phase-noise reference generator 219; ¶¶ [0040]-[0054] with FIGS. 2A and 3: the quantum controller 210 comprises pulsers 3021 -302L-1, receive analog frontend 350, input manager 352, digital manager 354, pulse operations manager 356, pulse operations 358, output manager 360, transmit analog frontend 362, data exchange 364, synchronization manager 366, and input/output ("I/O") manager 368; the signal routing and multiplexing/demultiplexing functions performed by the input manager 352 enables: a particular pulser 302I to process different inbound pulses from different quantum elements at different times; a particular pulser 302I to process different inbound pulses from different quantum elements at the same time; and multiple of the pulsers 3020-302L-1 to processes the same inbound pulse at the same time; each pulser circuit 302I (I between 0 and L-1) comprises circuitry operable to generate outbound pulses according to quantum control operations to be performed on the quantum processor 218; this involves very precisely controlling characteristics such as phase, frequency, amplitude, and timing of the outbound pulses; the outbound pulses may be, e.g., control pulses sent to the quantum processor 218 to manipulate one or more properties of one or more quantum elements — e.g., manipulate a state of one or more qubits, manipulate a frequency of a qubit using flux biasing, etc., and/or readout a state of one or more quantum elements; the characteristics of an outbound pulse generated at any particular time may be determined, at least in part, on inbound pulses received from the quantum processor 218 via frontend circuitry 220 at a prior time; the time required to close the feedback loop (i.e., time from receiving a first pulse on an output 217 of front-end circuitry 254 to sending a second pulse (e.g., at an input 221 of front-end circuitry 254), where the second pulse is based on the first pulse, is significantly less than the coherence time of the qubits of the quantum processor 218; pulser 302I may process the inbound signal AII to determine the state of certain quantum element(s) in the quantum processor 218 and use this state information for making decisions such as, e.g., which raw outbound pulse CP'I to generate next, when to generate it, and what control signals to generate to affect the characteristics of that raw outbound pulse appropriately; the pulse operations circuitry 358 is operable to process the raw outbound pulses CP'0 -CP'L-1 to generate corresponding output outbound pulses CP0-CPL-1; this may comprise, e.g.,, manipulating the amplitude, phase, and/or frequency of the raw pulse CP'I; the output manager 360 enables: routing outbound pulses from a particular pulser 3021 to different ones input ports 221 at different times; routing outbound pulses from a particular pulser 3021 to multiple of the input ports 221 at the same time; and multiple of the pulsers 3020 -302L-1 generating pulses for the same input port 221 at the same time; at any given time, the output manager 360 is operable to concurrently route K of the digital signals CP0-CPL-1 as K independent outbound pulses, concurrently route K/2 of the digital signals CP0-CPL-1 as two-pulse pairs, or route some of signals CP0-CPL-1 as independent outbound pulses and some others of the signals CP0-CPL-1 as multi-pulse sets (at different times and/or concurrently); the digital manager 354 comprises circuitry operable to process and/or route digital control signals (DigCtrl0-DigCtrlJ-1) to various circuits of the quantum controller 210 and/or external circuits coupled to the quantum controller 210; each destination of the digital signals may require different operations to be performed on the digital signal (such as delay, broadening, or digital convolution with a given digital pattern); these operations may be performed by the digital manager 354 and may be specified by control signals from the pulsers 3020-302L-1; this allows each pulser 3021 to generate digital signals to different destinations and allows different ones of pulsers 3020-302L-1 to generate digital signals to the same destination while saving resources; the data exchange circuitry 364 is operable to manage exchange of data among the various circuits shown in FIG. 3; pulser 3021 may need to share, with pulser 3022, the characteristics of an inbound signal AI1 that it just processed so that pulser 3022 can generate a raw outbound pulse CP'2 based on the characteristics of AI1; ¶¶ [0055]-[0059] with FIG. 4: each pulse template stored in memory 404 comprises a sequence of one or more samples of any arbitrary shape (e.g., Gaussian, sine, impulse, etc.) representing the pulses to be sent to pulse operation circuitry 358; ¶¶ [0060]-[0071] with FIGS. 2A, 3 and 5: the pulse operations circuitry 358 comprises a plurality of pulse modification circuits 5080-508R-1 (R is an integer≥1 in general, and R=L/2 in the example shown); the pulse operations manager 356 comprises control circuitry 502, routing circuitry 506, and a plurality of modification settings circuits 5040-504K-1; assuming CP1 and CP2 are a phase-quadrature pulse pair to be output; in this example, pulse operations circuitry 358 may process CP1 and CP2 by multiplying a vector representation of CP'1 and CP'2 by one or more 2 by 2 matrices to: (a) perform single-sideband-modulation, where ω is the frequency of the single side band modulation and TS is the time passed since the reference time (e.g. the beginning of a certain control protocol); (b) keep track of frame-of-reference rotations, where ϕ is the total phase that the frame of reference accumulated since the reference time; and/or (c) perform an IQ-mixer correction where C00, C01, C10, and C11 are the elements of a matrix that corrects for IQ-mixer imperfections; each modification settings circuit, 504k, contains registers that contain the matrix elements of three matrices: an IQ-mixer correction matrix Ck; a single sideband frequency modulation matrix Sk; and a frame rotation matrix Fk, which rotates the IQ axes around the axis perpendicular to the IQ plane (i.e. the z-axis if I and Q are the x-axis and y-axis); each pulse modification circuit 508r is operable to process two raw outbound pulses CP'2r and CP'2r+1; such processing may comprise adjusting a phase, frequency, and/or amplitude of the raw outbound pulses CP'2r and CP'2r+1; pulse modification settings output to pulse operations circuitry 358 are specifically tailored to each raw outbound pulse (e.g., to which quantum element 226 or 228 the pulse is destined, to which input port 221 of front-end circuitry 254 the pulse is destined, etc.) to be processed by pulse operations circuitry 358; each path a pulse may travel to the quantum processor 218 via frontend circuitry 254 may have particular characteristics (e.g., non-idealities of interconnect, mixers, switches, attenuators, amplifiers, and/or circuits along the paths) to be accounted for by the pulse modification operations; similarly, each quantum element 1220-122k may have a particular characteristics (e.g. resonance frequency, frame of reference, etc.); the routing circuitry 506 is operable to route modification settings from the modification settings circuits 5040 -504L-1 to the pulse operations circuit 358 and to the pulsers 3020-302L-1; the pulser 3021 may determine ops_slct1 based on the particular quantum element 122k and/or signal path to which the pulse is to be transmitted (e.g., the resonant frequency of the quantum element, frame of reference, and/or mixer correction); the determination of which quantum element and/or signal path to which a particular pulser 3021 is to send an outbound pulse at a particular time may be predetermined in the pulse generation program and quantum machine specification 206 or may be determined based on calculations performed by the pulser 3021 and/or others of the pulsers 3020-302L-1 during runtime; the digital signal IFI instructs the pulse operations manager 356 to update a frequency setting of the modification settings circuit 504k indicated by ops_slct1; ¶¶ [0072]-[0079] with FIGS.3 and 6A-B: the frequency generation circuitry is part of control circuitry 502 of pulse operations manager circuitry 356; each CORDIC circuit 602k is operable to compute cosine and sine of its input, θk, thus generating two signals cos(θk) and sin(θk); the phase generation circuitry 604 is operable to generate the CORD IC input parameters θ0-θk-1 based on: (a) the frequency setting signals IF0-IFL-1 from the pulsers 3020-302L-1; and (b) the contents, TS, of the timestamp register 606; the timestamp register 606 comprises circuitry (e.g., a counter incremented on each cycle of the clock signal clk1) operable to track the number of cycles of clk1 since a reference point in time (e.g., power up of the quantum controller 210, start of execution of set of instructions of a pulse generation program by the quantum controller 210, etc.); the phase generation circuitry 604 sets θ0=2πf0(TS)(dtclk1), where f0 is a frequency determined from the signal IF0, TS is the number of clock cycles counted from the reference point and dtclk1 is the duration of a single clock cycle of clk1; this leads to the CORD IC outputs being a pair of phase-quadrature reference signals, cos(2πf0(TS)(dtclk1)) and sin(2πf0(TS)(dtclk1)), as in the example shown, which are used to generate the S0 rotation matrix that rotates at a frequency f0; as shown in FIG. 6B, the signal IFI may comprise an update component and an fI component; when updateI is asserted then the phase generation circuitry updates one of more of f0-fk-1 to be the value of fI; the S-matrix generation circuitry 608 is operable to build the matrices S0-SK-1 from the outputs of the CORDIC circuits 6020-602K-1; the S-matrix generation circuit 608 is operable to synchronize changes to the S matrices such that any matrix update occurs on a desired cycle of clock clk1 (which may be determined by the control information IF0-IFL- 1); in instances that more than K frequencies are needed over the course of a set of instructions, the phase generation circuit 604 is operable to change the input parameter θk of one or more of the CORDIC circuits 6020-602K-1 to stop generating one frequency and start generating the K+1th frequency; it may be necessary for the new frequency to start at a phase θ that would have been the phase if the new frequency was being generated from the initial reference time (e.g., because the new frequency would be used to address a quantum element that has a resonance at the new frequency and that was coherent since the reference point); in some other instances, it might be necessary to start the new frequency from the phase that the old frequency ended in; ¶ [0093]: patternz of signal Pz may be determined based on: the destination(s) of signal Pz; characteristics of the corresponding quantum control pulse (e.g., any one or more of its frequency, phase, amplitude, and/or duration); and/or process, temperature, and/or voltage variations; ¶¶ [0094]-[0106] with FIGS. 9A-B: FIG. 9A illustrates configuration and control of the quantum controller via the quantum programming subsystem; connected to the inputs and outputs of the quantum controller 210 may be a plurality of external devices (e.g., oscilloscopes, waveform generators, spectrum analyzers, mixers, amplifiers, etc.) and a plurality of quantum elements; the pulse generation program 904 comprises statements that define a sequence of operations to be performed by the quantum machine defined in the specification 902; such operations typically include the generation of one or more analog pulses to be sent to a controlled element, such as a quantum element; such operations typically include measuring one or more return pulses from an element; the pulse generation program is also referred to herein as a QUA program; defines the sequence of statements for: (a) generating, shaping and sending pulses to the quantum device; (b) measuring of pulses returning from the quantum device; (c) performing real-time classical calculations on the measured data and storing results in classical variables; (d) performing real-time classical calculations on classical variables; (e) controlling the flow of the program, including branching statements; and (6) streaming of data from the quantum controller 210 to the quantum programing system 202 and processing and saving it in the quantum programing system 202; a QUA program can define exactly the timing in which pulses are played, down to the single sample level and single clock cycles of the quantum controller 210; during compilation, pulse modification settings for manipulating pulses intended for an element may be generated (for loading into pulse modification settings circuits 504) and the pulse modification setting circuit(s) 504 to which they will be loaded before execution may be chosen and may be allocated to the quantum machine on which the program is to be executed; similarly, parameters and configurations of operations that will be performed on input signals related to an element (e.g. readout/measurement pulses) may be generated during compilation (for loading into compute and signal processing circuits 410); an element that a quantum machine may contain is a mixer of front-end circuitry 254; to correct for mixer imbalances, the in-phase/quadrature (10) waveforms of the pulse can be multiplied by a 2x2 mixer correction matrix before being sent to the output ports; this mixer correction matrix, determined via a calibration routine, may be frequency dependent; thus, a mixer definition may include the mixer's name and a list of one or more frequencies and the correction matrix to be used at each frequency; in one example implementation, the correction matrix is loaded into corresponding pulse modification circuit during compilation; similarly, an element definition may include an intermediate frequency with which every pulse sent to the element is to be modulated; when generating local oscillators for quantum control, it is desirable to minimize phase noise at offset from the carrier frequency that are determined by typical quantum gate(s) times, and typical quantum element coherence times; e.g., for one quantum system with shorter gate time it may be desirable to minimize phase noise in the range of 10 MHz to 100 MHz, whereas for another quantum system with longer gate times, it may be desirable to minimize phase noise in the range of 100 Hz to 100 kHz; also, the tolerable amount of phase noise may depend on the quantum system being controlled and/or the quantum algorithm being performed; some systems and/or algorithms can tolerate higher phase noise' laboratories using these systems and/or running these algorithms could benefit from a lower-cost implementation of multi-tone generator 222), a converter that converts the pulse data into an analog signal (Szmuk, ¶ [0049] with FIGS. 2A and 3: the transmit analog frontend 362 comprises circuitry operable to concurrently process up to K digital signals DOk to generate up to K concurrent analog signals AOk to be output to inputs 221 of the front-end circuitry 254; such processing may comprise, e.g., digital-to analog conversion, filtering, upconversion, downconversion, amplification, attenuation, time division multiplexing/demultiplexing, frequency division multiplexing/demultiplexing and/or the like; the transmit analog frontend 362 is operable to process digital signals DO0-DOK-1 as K independent outbound pulses, as K/2 two-pulse pairs, or process some of signals DO0-DOK-1 as independent outbound pulses and some signals DO0-DOK-1 as two-pulse pairs (at different times and/or concurrently)), modulates it with the sine wave, and outputs a signal having the frequency of the sine wave as the center frequency as a microwave pulse (Szmuk, ¶¶ [0032]-[0039] with FIG. 2A-D: the front-end circuitry 254 is operable to receive outbound intermediate frequency (IF) pulses from quantum controller 210 via one or more ports 221, upconvert the IF pulses to RF using the local oscillator signals received via one or more LO ports 229, and output the RF pulses to quantum processor 218 via one or more output ports 225; each IF input port 221 is configured to receive an independent pulse or multi-pulse pair (e.g., an IQ pair of pulses comprising an in-phase pulse and quadrature-phase pulse); in the latter case, the front-end circuitry 254 is operable to perform IQ upconversion; in FIG. 2D, the circuitry 254 comprises 6 IQ mixers 270; each of mixers 2700-2704 receives an IQ pair of IF signals via a respective one of ports 2210-2214, and uses an LO signal received via a respective one of ports 2290-2294 to upconvert the IQ pair to a corresponding RF signal output via a respective one of ports 2250 -2254; the multi-tone generator 222 is operable to generate one or more signals at one or more desired frequencies, which will typically be dictated by the particular quantum processor 218 (e.g., based on the resonant frequencies of quantum elements of the quantum processor 218); two types of outputs are provided by quantum multi-tone generator 222: (a) one or more fixed frequency continuous wave (CW) tones 223; and (b) one or more synthesized frequency signals 231; the connectivity circuitry 224 is operable to couple the outputs of the multi-tone generator 222 to the inputs of the front-end circuitry 254; the connectivity circuitry 224 can connect any one or more of the signals 2230 -2237 and 231 to any one or more of the input ports 2290 -2295 of front-end circuitry 254), and a frequency divider that (Szmuk, ¶ [0050] with FIGS. 2A and 3: the output manager 360 comprises circuitry operable to route any one or more of signals CP0-CPL-1 to any one or more input ports 221 of the front-end circuitry 254; the output manager 360 comprises one or more switch networks, multiplexers, and/or the like for dynamically reconfiguring which one or more signals CP0-CPL-1 are routed to which input port(s) 221 of the front-end 220; this may enable time division multiplexing multiple of the signals CP0-CPL-1 onto a single input port 221 of the front-end circuit 220 and/or time division demultiplexing components (e.g., time slices) of a signal CP m onto multiple of the input ports 221 of the front-end circuitry 254; the output manager 360 comprises one or more mixers and/or filters for frequency division multiplexing multiple of the signals CP0-CPM-1 onto a single input port 221 of front-end circuitry 254 and/or frequency division demultiplexing components (e.g., frequency bands) of a signal CPm onto multiple of the input ports 221 of the front-end circuitry 254; ¶¶ [0034] and [0038] with FIG. 2A: allows splitting a tone 223 into up to six LO signals using a suitable power splitting circuit, without any additional active RF components; the reference generator circuit 219 provides a reference signal that the multi-tone generator 222 splits, frequency multiplies, amplifies and filters to generate signals 2230 -2237 and 231; ¶¶ [0075]-[0078]: the timestamp register 606 comprises circuitry (e.g., a counter incremented on each cycle of the clock signal clk1) operable to track the number of cycles of clk1 since a reference point in time (e.g., power up of the quantum controller 210, start of execution of set of instructions of a pulse generation program by the quantum controller 210, etc.); a desired cycle of clock clk1 (which may be determined by the control information IF0-IFL- 1); ¶ [0107] with FIG. 10: the signal processing circuitry is operable to perform splitting, frequency multiplication, gain adjustment, filtering, and/or other signal processing operations to generate M+1 local oscillator signals 1003 from the OCXO output 1001), wherein the frequency generator operates at the same frequency as the quantum bit other than the selected quantum bit except when the microwave pulse is output (Szmuk, ¶¶ [0033]-[0037] and [0042]-[0050] with FIGS. 2A and 3: the multi-tone generator 222 is operable to generate one or more signals at one or more desired frequencies, which will typically be dictated by the particular quantum processor 218 (e.g., based on the resonant frequencies of quantum elements of the quantum processor 218); two types of outputs are provided by quantum multi-tone generator 222: (a) one or more fixed frequency continuous wave (CW) tones 223; and (b) one or more synthesized frequency signals 231; together with the ability of the quantum controller 210 to accurately and dynamically control the frequencies of IF pulses it generates (see e.g., FIGS. 6A and 6B, below), enables addressing qubits within a band of frequencies that covers all currently known and proposed superconducting qubit implementations; together with the ability of the quantum controller 210 to accurately and dynamically control the frequencies of IF pulses it generates (see e.g., FIGS. 6A and 6B, below), enables, for example, addressing various readout elements that use a wide range of frequencies; because the desired connections between multi-tone generator 222 and quantum processor 218 depends on the architecture and operating frequencies of the quantum processor 218, the connectivity circuitry 224 is configurable by the user to support whatever configurations users may need for their particular quantum algorithms and particular quantum processor 218; the signal routing and multiplexing/demultiplexing functions performed by the input manager 352 enables: a particular pulser 302I to process different inbound pulses from different quantum elements at different times; a particular pulser 302I to process different inbound pulses from different quantum elements at the same time; and multiple of the pulsers 3020-302L-1 to processes the same inbound pulse at the same time; each pulser circuit 302I (I between 0 and L-1) comprises circuitry operable to generate outbound pulses according to quantum control operations to be performed on the quantum processor 218; this involves very precisely controlling characteristics such as phase, frequency, amplitude, and timing of the outbound pulses; the outbound pulses may be, e.g., control pulses sent to the quantum processor 218 to manipulate one or more properties of one or more quantum elements — e.g., manipulate a state of one or more qubits, manipulate a frequency of a qubit using flux biasing, etc., and/or readout a state of one or more quantum elements; the characteristics of an outbound pulse generated at any particular time may be determined, at least in part, on inbound pulses received from the quantum processor 218 via frontend circuitry 220 at a prior time; ¶¶ [0107]-[0111] with FIGS. 2A and 10: a quantum control multi-tone generator (e.g., multi-tone generator 222) comprising oven-controlled crystal oscillator (OCXO) and signal processing circuitry 1002; the signal processing circuitry is operable to perform splitting, frequency multiplication, gain adjustment, filtering, and/or other signal processing operations to generate M+1 local oscillator signals 1003 from the OCXO output 1001; the signal 1001 is at frequency fi, ID is a multiple of fi, each of the signals 223 is at a multiple of ID, and each of k and M are integers; the use of multiple fixed-frequency tones, avoids the need for the voltage controlled oscillators and phase locked loops used in the signal generators conventionally used for driving quantum systems, which has the benefit of greatly reducing phase noise in the circuitry 222 (in general VCOs introduce additional phase noise as compared to OCXOs); the quantum control multi-tone generator 222 also comprises a variable frequency signal generator 1004 operable to output a signal 231 having a variable (i.e., tunable) frequency; the variable frequency generator 1004 may be driven by the same reference signal that is input to the OCXO 1000 (e.g., a 10 MHz signal) and/or may be driven by the signal 1001 output by OXCO 1000 (e.g., a 1000 MHz signal); the use of a single fundamental frequency, fi, which is then upconverted to the output frequencies using mixers, amplifiers, and bandpass filters provides positive phase correlation between the phase noises of the outputs; this generation of coherent tones through multiplication and filtering of a common reference signal may increase quantum gate fidelity in scenarios where multiple sequential single-gate operations are applied to qubits that are operating using different frequency tones, as well as two-qubit gate operations; the signal processing circuit 1002 performs fanout, frequency multiplication, amplification, and filtration functions; ¶¶ [0112]-[0141] with FIGS. 11A-D: a quantum control multi-tone generator in FIG. 11A including the OCXO 1000 and the circuit 1002 which outputs M multiples of the fi; each of the outputs of circuit 1002 is then input to circuitry comprising a PLL and DRO 1120 in a feedback arrangement to generate a signal 223; the DROs have the effect of lowering phase noise in the signals 223 at frequencies far from the carrier frequency; a quantum control multi-tone generator in FIG. 11B uses only a single DRO 1120 and PLL 1104; the outputs of circuit 1002 and the DRO 1120 feed a signal processing circuit 1122 which mixes the signals 11060-1106N-1 (N is an integer) to generate signals 2230-223M-1; which of the N+1 signals 11060-1106N-1 is selected as signal 1106q (q is an integer where 0≤q≤N-1) to be input to the PLL 1104 may be determined (e.g., preconfigured or controlled programmatically during operation via signal(s) 253, 255, 257, and/or 259) based on the desired frequencies of the signals 2230-223M; the number of signals 223 and/or the frequency spacing of the signals 223 may be determined based on the range of frequencies that the control circuitry 502 of quantum controller 210 is configured to generate; the circuit 1002 may comprise one or more frequency multiplier circuits 1052; each circuit 1150 comprises M, an integer, multiplier circuits 1052, each of which generates an output signal that is an integer multiple of its input signal (in addition to the frequency multiplication, each circuit 1052 may also perform filtering and/or other signal conditioning operations such as current and/or voltage amplification to make the output signal suitable for driving one or more of: another multiplication circuit 1052, a PLL such as 1104, mixer(s) of the circuit 1122, and/or one or more inputs of the circuit 224; the circuit 1122 may comprise one or more mixer circuits 1152; through setting (either at design time or in the field using jumpers, variable resistors, switches, etc.) the multiplication factors of each multiplier 1052, the number of circuits 1150, the number of circuits 1152, and/or the interconnection of the circuits 1150 and 1152, a wide range of frequencies and channel spacings can be achieved to support a wide range of quantum processors and a wide range of quantum controllers; e.g., the multipliers are configured and connected to achieve 24 output frequencies spaced at 4fi, as follows: (a) circuit 11500 outputs: (i) fi, which drives an output port of the multitone generator 222; (ii) 4fi, which drives the input of circuit 11501, and is the basis for the frequency spacing; and (iii) 10fi, which drives an output port of the multitone generator 222; (b) circuit 11501 outputs: (i) 4fi, which drives an input of each of circuits 11520 , 11521 , and 11522; (ii) 8fi, which drives an input of each of circuits 11520 , 11521 , and 11522; (iii) 12fi, which drives an input of each of circuits 11520 , 11521 , and 11522; and (iv) 16fi, which drives an input of circuit 11502; (c) circuit 11502 outputs: (i) 16fi, which drives an output port of the multitone generator 222; (ii) 32fi, which drives an input of circuit 11520; (iii) 48fi, which drives an input of circuit 11521; (iii) 64fi which drives an input of circuit 11522; and (iv) 80fi, which drives an output port of the multitone generator 222; (d)circuit 11520 receives 4fi, 8fi, 12fi, and 32fi and outputs 28fi, 36fi, 40fi, 24fi, 44fi, and 20fi; (e) circuit 11521 receives 4fi, 8fi, 12fi, and 48fi and outputs 52fi, 44fi, 56fi, 40fi, 60fi, and 36fi; and (f) circuit 11522 receives 4fi, 8fi, 12fi, and 64fi and outputs 68fi, 60fi, 72fi, 56fi, 76fi, and 52fi; the multi-tone generator is operable to generate a plurality of fixed-frequency signals from a single fixed-frequency reference signal (e.g., 2230 -2237), and output the plurality of fixed-frequency signals via a corresponding plurality of output ports (e.g., ports of 222); each of the plurality of fixed-frequency signals may be at a different one of a plurality of frequencies from a first frequency (e.g., 2.5 GHz) to a second frequency (e.g., 6 GHz); the frequency spacing between frequency-adjacent signals of the plurality of fixed-frequency signals may be less than or equal to a range of frequencies (e.g., a range of 500 MHz) at which the quantum control pulse generation circuitry is configured to generate a pulse signal (e.g., AO0) such that any frequency in the range from the first frequency to the second frequency for controlling quantum elements can be achieved through tuning of the pulse signal and mixing of the pulse signal with one of the plurality of fixed-frequency signals; the quantum control pulse generation circuit may be operable to generate baseband pulses, and upconvert the baseband pulses to an intermediate frequency to generate the quantum control pulses, wherein the intermediate frequency is tunable over a range at least as large as the first frequency spacing), and the logic circuit operates in synchronization with the system clock (Szmuk, ¶ [0052] with FIG. 3: the synchronization manager 366 comprises circuitry operable to manage synchronization of the various circuits shown in FIG. 3; such synchronization is advantageous in a modular and dynamic system, such as quantum controller 210, where different ones of pulsers 3020-302L-1 generate, receive, and process pulses to and from different quantum elements at different times; e.g., a pulse generation program may require that a first pulser circuit 3021 and a second pulser circuit 3022 sometimes need to transmit pulses at precisely the same time, and at other times transmit pulses independently of one another; the synchronization manager 366 reduces the overhead involved in performing such synchronization; ¶ [0078] with FIGS. 6A-B: the S-matrix generation circuit 608 is operable to synchronize changes to the S matrices such that any matrix update occurs on a desired cycle of clock clk1 (which may be determined by the control information IF0-IFL- 1); ¶ [0086] with FIGS. 3 and 7: each of the controlled circuits 7100-710J-1 and input manager 372 is a circuit which, at least some of the time, needs to operate synchronously with quantum control pulses generated by one or more of pulsers 3020-302L-1 (possibly a reflection/return pulse from a quantum processor in the case of input manager 372); accordingly, each of the control circuits 7100-710J-1 receives a respective one of control signals DigOut0-DigCtrlJ-1 that is synchronized with a respective quantum control pulse).
Szmuk fails to explicitly disclose a frequency divider that outputs a system clock divided by the frequency of the wave.
Negoro teaches a system and a method relating to a quantum computer controller (Negoro, ¶ [0001]), wherein a frequency divider that outputs a system clock divided by the frequency of the wave (Negoro, ¶¶ [0027]-[0032] with FIG. 2: the quantum computer 100 includes a controller 110 and a qubit system 120 having a plurality of qubits; the controller 110 includes a server 130, a plurality of signal processing units 140-1, a clock distribution unit 150, and a master 160; upon receipt of an instruction input from a user, the server 130 calculates a waveform signal required for state manipulation of the qubits of the qubit system 120 or for readout from the qubit system 120, and outputs the waveform signal to each of the signal processing units 140-1; the clock distribution unit 150 distributes a common clock to the signal processing units 140-I; the master 160 distributes a common time to the signal processing units 140-i in accordance with a time synchronization protocol; each of the signal processing units 140-i is designed by integrating the functions of the baseband circuits 40, the oscillation circuit 50, and the analog circuit 60 of the conventional quantum computer shown in FIG. 1 into a single unit, and generates, based on the waveform signal calculated by the server 130, a microwave signal (electromagnetic wave signal) with which the qubit system 120 is irradiated; ¶¶ [0055]-[0063] with FIG. 3: the dividers 372 are respectively provided at the output stages of the filter/multiplier units 370; the microwave signal from the filter/multiplier unit 370 is divided into two signals (a first microwave signal OUT1 and a second microwave signal OUT2) by the divider 372; the first microwave signal OUT1 is emitted onto the qubits of the qubit system 120 through a cable, and the second microwave signal OUT2 is output to the feedback circuit 380; some of the plurality of first microwave signals OUT1 are control signals for manipulating the states of the qubits, and the remaining first microwave signals OUT1 include a read pulse for reading the qubits and a pump pulse for amplifying the read signal; when the second microwave signal OUT2 is selected, the second microwave signal OUT2 is used for correcting the baseband signal as described below; on the other hand, when the external signal EXT from the other signal processing unit 140-j is selected, the external signal EXT is used for monitoring synchronization between different signal processing units 140-i and 140-j (i≠j); when the monitor signal corresponds to the second microwave signal OUT2, the receiving logic 318 calculates a difference between the monitor signal and the baseband signal output from the transmitting logic 316, and sets a correction parameter for eliminating the difference, as a parameter 316a for the transmitting logic 316; the transmitting logic 316 corrects, in accordance with the parameter 316a, the baseband signal generated from the waveform signal held in the HBM 314, and outputs the corrected baseband signal; with the automatic calibration based on the monitor signal as described above, it is possible to improve usability, and achieve high performance and high stability; when the monitor signal corresponds to the external signal EXT input from the other signal processing unit 140-j to the signal processing unit 140-i (i≠j), the receiving logic 318 of the signal processing unit 140-i compares the monitor signal with a reference signal to analyze the synchronization between the different signal processing units 140-i and 140-j, and writes the analysis result into the HBM 314; ¶¶ [0066]-[0069] with FIGS. 3, 5, and 7B: the clock distribution unit 150 includes a clock generation source 510, a first clock generator 521, a second clock generator 522, and a third clock generator 523; the clock generation source 510 generates a clock with a given frequency (e.g., 10 MHz); the clock generated by the clock generation source 510 is distributed into the first clock generator 521, the second clock generator 522, and the third clock generator 523; each of the first clock generator 521, the second clock generator 522, and the third clock generator 523 includes a phase-locked loop (PLL), a frequency divider circuit, and the like; the first clock generator 521, the second clock generator 522, and the third clock generator 523 generate a first clock, a second clock, and a third clock, respectively, having different frequencies from one another; the first clock, the second clock, and the third clock are distributed to all the signal processing units 140-1, 140-2, …, and 140-N, through signal lines 531, 532, and 533, respectively; the first clock is a system operation clock with a first frequency (e.g., 125 MHz); the second clock is a clock with a second frequency (e.g., 62.5 kHz) having a longer period than the first clock, and is used for synchronization in different channels between the logic device 310 and the DAC/ADC module 330 (see FIG. 7B); the third clock is a reference clock with a third frequency (e.g., 100 MHz), on which the oscillation signals of the oscillators (NCOs, LO) are based; the logic device 310 of each of the signal processing units 140-i generates, from the first clock, an operation clock with a higher frequency than the first clock).
Szmuk and Negoro are analogous art because they are from the same field of endeavor, a system and a method relating to a quantum computer controller. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to apply the teaching of Negoro to Szmuk. Motivation for doing so would provide better synchronization (Negoro, ¶¶ [0013], [0062], [0068]-[0069], [0071]-[0075], and [088]).
Claims 2 and 13
Szmuk in view of Negoro discloses all the elements as stated in Claims 1 and 12 respectively and further discloses wherein the logic circuit outputs a frequency modulation signal based on the frequency of the selected quantum bit, and the frequency generator outputs a sine wave based on the frequency modulation signal (Szmuk, ¶¶ [0032]-[0039] with FIG. 2A-D: the front-end circuitry 254 is operable to receive outbound intermediate frequency (IF) pulses from quantum controller 210 via one or more ports 221, upconvert the IF pulses to RF using the local oscillator signals received via one or more LO ports 229, and output the RF pulses to quantum processor 218 via one or more output ports 225; each IF input port 221 is configured to receive an independent pulse or multi-pulse pair (e.g., an IQ pair of pulses comprising an in-phase pulse and quadrature-phase pulse); in the latter case, the front-end circuitry 254 is operable to perform IQ upconversion; in FIG. 2D, the circuitry 254 comprises 6 IQ mixers 270; each of mixers 2700-2704 receives an IQ pair of IF signals via a respective one of ports 2210-2214, and uses an LO signal received via a respective one of ports 2290-2294 to upconvert the IQ pair to a corresponding RF signal output via a respective one of ports 2250 -2254; the multi-tone generator 222 is operable to generate one or more signals at one or more desired frequencies, which will typically be dictated by the particular quantum processor 218 (e.g., based on the resonant frequencies of quantum elements of the quantum processor 218); two types of outputs are provided by quantum multi-tone generator 222: (a) one or more fixed frequency continuous wave (CW) tones 223; and (b) one or more synthesized frequency signals 231; the connectivity circuitry 224 is operable to couple the outputs of the multi-tone generator 222 to the inputs of the front-end circuitry 254; the connectivity circuitry 224 can connect any one or more of the signals 2230 -2237 and 231 to any one or more of the input ports 2290 -2295 of front-end circuitry 254; ¶ [0056] with FIG. 4: each pulse template stored in memory 404 comprises a sequence of one or more samples of any arbitrary shape (e.g., Gaussian, sine, impulse, etc.) representing the pulses to be sent to pulse operation circuitry 358; ¶¶ [0060]-[0071] with FIGS. 2A, 3 and 5: the pulse operations circuitry 358 comprises a plurality of pulse modification circuits 5080-508R-1 (R is an integer≥1 in general, and R=L/2 in the example shown); the pulse operations manager 356 comprises control circuitry 502, routing circuitry 506, and a plurality of modification settings circuits 5040-504K-1; two of the pulsers 3020-302L-1 may generate two raw outbound pulses which are a phase-quadrature pulse pair; assuming CP1 and CP2 are a phase-quadrature pulse pair to be output; in this example, pulse operations circuitry 358 may process CP1 and CP2 by multiplying a vector representation of CP'1 and CP'2 by one or more 2 by 2 matrices to: (a) perform single-sideband-modulation, where ω is the frequency of the single side band modulation and TS is the time passed since the reference time (e.g. the beginning of a certain control protocol); (b) keep track of frame-of-reference rotations, where ϕ is the total phase that the frame of reference accumulated since the reference time; and/or (c) perform an IQ-mixer correction where C00, C01, C10, and C11 are the elements of a matrix that corrects for IQ-mixer imperfections; each modification settings circuit, 504k, contains registers that contain the matrix elements of three matrices: an IQ-mixer correction matrix Ck; a single sideband frequency modulation matrix Sk; and a frame rotation matrix Fk, which rotates the IQ axes around the axis perpendicular to the IQ plane (i.e. the z-axis if I and Q are the x-axis and y-axis); each pulse modification circuit 508r is operable to process two raw outbound pulses CP'2r and CP'2r+1; such processing may comprise adjusting a phase, frequency, and/or amplitude of the raw outbound pulses CP'2r and CP'2r+1; pulse modification settings output to pulse operations circuitry 358 are specifically tailored to each raw outbound pulse (e.g., to which quantum element 226 or 228 the pulse is destined, to which input port 221 of front-end circuitry 254 the pulse is destined, etc.) to be processed by pulse operations circuitry 358; each path a pulse may travel to the quantum processor 218 via frontend circuitry 254 may have particular characteristics (e.g., non-idealities of interconnect, mixers, switches, attenuators, amplifiers, and/or circuits along the paths) to be accounted for by the pulse modification operations; similarly, each quantum element 1220-122k may have a particular characteristics (e.g. resonance frequency, frame of reference, etc.); the routing circuitry 506 is operable to route modification settings from the modification settings circuits 5040 -504L-1 to the pulse operations circuit 358 and to the pulsers 3020-302L-1; the pulser 3021 may determine ops_slct1 based on the particular quantum element 122k and/or signal path to which the pulse is to be transmitted (e.g., the resonant frequency of the quantum element, frame of reference, and/or mixer correction); the determination of which quantum element and/or signal path to which a particular pulser 3021 is to send an outbound pulse at a particular time may be predetermined in the pulse generation program and quantum machine specification 206 or may be determined based on calculations performed by the pulser 3021 and/or others of the pulsers 3020-302L-1 during runtime; the digital signal IFI instructs the pulse operations manager 356 to update a frequency setting of the modification settings circuit 504k indicated by ops_slct1; ¶¶ [0072]-[0079] with FIGS.3 and 6A-B: the frequency generation circuitry is part of control circuitry 502 of pulse operations manager circuitry 356; each CORDIC circuit 602k is operable to compute cosine and sine of its input, θk, thus generating two signals cos(θk) and sin(θk); the phase generation circuitry 604 is operable to generate the CORD IC input parameters θ0-θk-1 based on: (a) the frequency setting signals IF0-IFL-1 from the pulsers 3020-302L-1; and (b) the contents, TS, of the timestamp register 606; the timestamp register 606 comprises circuitry (e.g., a counter incremented on each cycle of the clock signal clk1) operable to track the number of cycles of clk1 since a reference point in time (e.g., power up of the quantum controller 210, start of execution of set of instructions of a pulse generation program by the quantum controller 210, etc.); the phase generation circuitry 604 sets θ0=2πf0(TS)(dtclk1), where f0 is a frequency determined from the signal IF0, TS is the number of clock cycles counted from the reference point and dtclk1 is the duration of a single clock cycle of clk1; this leads to the CORD IC outputs being a pair of phase-quadrature reference signals, cos(2πf0(TS)(dtclk1)) and sin(2πf0(TS)(dtclk1)), as in the example shown, which are used to generate the S0 rotation matrix that rotates at a frequency f0; as shown in FIG. 6B, the signal IFI may comprise an update component and an fI component; when updateI is asserted then the phase generation circuitry updates one of more of f0-fk-1 to be the value of fI; the S-matrix generation circuitry 608 is operable to build the matrices S0-SK-1 from the outputs of the CORDIC circuits 6020-602K-1; the S-matrix generation circuit 608 is operable to synchronize changes to the S matrices such that any matrix update occurs on a desired cycle of clock clk1 (which may be determined by the control information IF0-IFL- 1); in instances that more than K frequencies are needed over the course of a set of instructions, the phase generation circuit 604 is operable to change the input parameter θk of one or more of the CORDIC circuits 6020-602K-1 to stop generating one frequency and start generating the K+1th frequency; it may be necessary for the new frequency to start at a phase θ that would have been the phase if the new frequency was being generated from the initial reference time (e.g., because the new frequency would be used to address a quantum element that has a resonance at the new frequency and that was coherent since the reference point); in some other instances, it might be necessary to start the new frequency from the phase that the old frequency ended in; ¶ [0105] with FIG. 2A: an element that a quantum machine may contain is a mixer of front-end circuitry 254; to correct for mixer imbalances, the in-phase/quadrature (10) waveforms of the pulse can be multiplied by a 2x2 mixer correction matrix before being sent to the output ports; this mixer correction matrix, determined via a calibration routine, may be frequency dependent; thus, a mixer definition may include the mixer's name and a list of one or more frequencies and the correction matrix to be used at each frequency; in one example implementation, the correction matrix is loaded into corresponding pulse modification circuit during compilation; similarly, an element definition may include an intermediate frequency with which every pulse sent to the element is to be modulated; ¶¶ [0107]-[0111] with FIGS. 2A and 10: a quantum control multi-tone generator (e.g., multi-tone generator 222) comprising oven-controlled crystal oscillator (OCXO) and signal processing circuitry 1002; the signal processing circuitry is operable to perform splitting, frequency multiplication, gain adjustment, filtering, and/or other signal processing operations to generate M+1 local oscillator signals 1003 from the OCXO output 1001; the signal 1001 is at frequency fi, ID is a multiple of fi, each of the signals 223 is at a multiple of ID, and each of k and M are integers; the use of multiple fixed-frequency tones, avoids the need for the voltage controlled oscillators and phase locked loops used in the signal generators conventionally used for driving quantum systems, which has the benefit of greatly reducing phase noise in the circuitry 222 (in general VCOs introduce additional phase noise as compared to OCXOs); the quantum control multi-tone generator 222 also comprises a variable frequency signal generator 1004 operable to output a signal 231 having a variable (i.e., tunable) frequency; the variable frequency generator 1004 may be driven by the same reference signal that is input to the OCXO 1000 (e.g., a 10 MHz signal) and/or may be driven by the signal 1001 output by OXCO 1000 (e.g., a 1000 MHz signal); the use of a single fundamental frequency, fi, which is then upconverted to the output frequencies using mixers, amplifiers, and bandpass filters provides positive phase correlation between the phase noises of the outputs; this generation of coherent tones through multiplication and filtering of a common reference signal may increase quantum gate fidelity in scenarios where multiple sequential single-gate operations are applied to qubits that are operating using different frequency tones, as well as two-qubit gate operations; the signal processing circuit 1002 performs fanout, frequency multiplication, amplification, and filtration functions; ¶¶ [0112]-[0141] with FIGS. 11A-D: a quantum control multi-tone generator in FIG. 11A including the OCXO 1000 and the circuit 1002 which outputs M multiples of the fi; each of the outputs of circuit 1002 is then input to circuitry comprising a PLL and DRO 1120 in a feedback arrangement to generate a signal 223; the DROs have the effect of lowering phase noise in the signals 223 at frequencies far from the carrier frequency; a quantum control multi-tone generator in FIG. 11B uses only a single DRO 1120 and PLL 1104; the outputs of circuit 1002 and the DRO 1120 feed a signal processing circuit 1122 which mixes the signals 11060-1106N-1 (N is an integer) to generate signals 2230-223M-1; which of the N+1 signals 11060-1106N-1 is selected as signal 1106q (q is an integer where 0≤q≤N-1) to be input to the PLL 1104 may be determined (e.g., preconfigured or controlled programmatically during operation via signal(s) 253, 255, 257, and/or 259) based on the desired frequencies of the signals 2230-223M; the number of signals 223 and/or the frequency spacing of the signals 223 may be determined based on the range of frequencies that the control circuitry 502 of quantum controller 210 is configured to generate; the circuit 1002 may comprise one or more frequency multiplier circuits 1052; each circuit 1150 comprises M, an integer, multiplier circuits 1052, each of which generates an output signal that is an integer multiple of its input signal (in addition to the frequency multiplication, each circuit 1052 may also perform filtering and/or other signal conditioning operations such as current and/or voltage amplification to make the output signal suitable for driving one or more of: another multiplication circuit 1052, a PLL such as 1104, mixer(s) of the circuit 1122, and/or one or more inputs of the circuit 224; the circuit 1122 may comprise one or more mixer circuits 1152; through setting (either at design time or in the field using jumpers, variable resistors, switches, etc.) the multiplication factors of each multiplier 1052, the number of circuits 1150, the number of circuits 1152, and/or the interconnection of the circuits 1150 and 1152, a wide range of frequencies and channel spacings can be achieved to support a wide range of quantum processors and a wide range of quantum controllers; e.g., the multipliers are configured and connected to achieve 24 output frequencies spaced at 4fi, as follows: (a) circuit 11500 outputs: (i) fi, which drives an output port of the multitone generator 222; (ii) 4fi, which drives the input of circuit 11501, and is the basis for the frequency spacing; and (iii) 10fi, which drives an output port of the multitone generator 222; (b) circuit 11501 outputs: (i) 4fi, which drives an input of each of circuits 11520 , 11521 , and 11522; (ii) 8fi, which drives an input of each of circuits 11520 , 11521 , and 11522; (iii) 12fi, which drives an input of each of circuits 11520 , 11521 , and 11522; and (iv) 16fi, which drives an input of circuit 11502; (c) circuit 11502 outputs: (i) 16fi, which drives an output port of the multitone generator 222; (ii) 32fi, which drives an input of circuit 11520; (iii) 48fi, which drives an input of circuit 11521; (iii) 64fi which drives an input of circuit 11522; and (iv) 80fi, which drives an output port of the multitone generator 222; (d)circuit 11520 receives 4fi, 8fi, 12fi, and 32fi and outputs 28fi, 36fi, 40fi, 24fi, 44fi, and 20fi; (e) circuit 11521 receives 4fi, 8fi, 12fi, and 48fi and outputs 52fi, 44fi, 56fi, 40fi, 60fi, and 36fi; and (f) circuit 11522 receives 4fi, 8fi, 12fi, and 64fi and outputs 68fi, 60fi, 72fi, 56fi, 76fi, and 52fi; the multi-tone generator is operable to generate a plurality of fixed-frequency signals from a single fixed-frequency reference signal (e.g., 2230 -2237), and output the plurality of fixed-frequency signals via a corresponding plurality of output ports (e.g., ports of 222); each of the plurality of fixed-frequency signals may be at a different one of a plurality of frequencies from a first frequency (e.g., 2.5 GHz) to a second frequency (e.g., 6 GHz); the frequency spacing between frequency-adjacent signals of the plurality of fixed-frequency signals may be less than or equal to a range of frequencies (e.g., a range of 500 MHz) at which the quantum control pulse generation circuitry is configured to generate a pulse signal (e.g., AO0) such that any frequency in the range from the first frequency to the second frequency for controlling quantum elements can be achieved through tuning of the pulse signal and mixing of the pulse signal with one of the plurality of fixed-frequency signals; the quantum control pulse generation circuit may be operable to generate baseband pulses, and upconvert the baseband pulses to an intermediate frequency to generate the quantum control pulses, wherein the intermediate frequency is tunable over a range at least as large as the first frequency spacing).
Claims 3 and 14
Szmuk in view of Negoro discloses all the elements as stated in Claims 2 and 13 respectively and further discloses wherein the logic circuit calculates the amount of phase shift based on the set pulse width and the frequency of the selected quantum bit, and outputs a frequency modulation signal based on the amount of phase shift (Szmuk, ¶¶ [0040]-[0054] with FIGS. 2A and 3: the signal routing and multiplexing/demultiplexing functions performed by the input manager 352 enables: a particular pulser 302I to process different inbound pulses from different quantum elements at different times; a particular pulser 302I to process different inbound pulses from different quantum elements at the same time; and multiple of the pulsers 3020-302L-1 to processes the same inbound pulse at the same time; each pulser circuit 302I (I between 0 and L-1) comprises circuitry operable to generate outbound pulses according to quantum control operations to be performed on the quantum processor 218; this involves very precisely controlling characteristics such as phase, frequency, amplitude, and timing of the outbound pulses; the outbound pulses may be, e.g., control pulses sent to the quantum processor 218 to manipulate one or more properties of one or more quantum elements — e.g., manipulate a state of one or more qubits, manipulate a frequency of a qubit using flux biasing, etc., and/or readout a state of one or more quantum elements; the characteristics of an outbound pulse generated at any particular time may be determined, at least in part, on inbound pulses received from the quantum processor 218 via frontend circuitry 220 at a prior time; the time required to close the feedback loop (i.e., time from receiving a first pulse on an output 217 of front-end circuitry 254 to sending a second pulse (e.g., at an input 221 of front-end circuitry 254), where the second pulse is based on the first pulse, is significantly less than the coherence time of the qubits of the quantum processor 218; pulser 302I may process the inbound signal AII to determine the state of certain quantum element(s) in the quantum processor 218 and use this state information for making decisions such as, e.g., which raw outbound pulse CP'I to generate next, when to generate it, and what control signals to generate to affect the characteristics of that raw outbound pulse appropriately; the pulse operations circuitry 358 is operable to process the raw outbound pulses CP'0 -CP'L-1 to generate corresponding output outbound pulses CP0-CPL-1; this may comprise, e.g.,, manipulating the amplitude, phase, and/or frequency of the raw pulse CP'I; the pulse operations manager 356 comprises circuitry operable to configure the pulse operations circuitry 358 such that the pulse operations applied to each raw outbound pulse CP'l are tailored to that particular raw outbound pulse; denoting a first raw outbound pulse to be output during a first time interval T1 as CP'l,T1, and a second raw outbound pulse to be output during a second time interval T2 as CP'l,T2, then pulse operations circuitry 358 is operable to perform a first one or more operations on CP'l,T1 and a second one or more operations on CP'l,T2; the first one or more operations may be determined, at least in part, based on to which quantum element the pulse CP'l,T1 is to be sent, and the second one or more operations may be determined, at least in part, based on to which quantum element the pulse CP'l,T2 is to be sent; the determination of the first one or more operations and second one or more operations may be performed dynamically during runtime; the output manager 360 enables: routing outbound pulses from a particular pulser 3021 to different ones input ports 221 at different times; routing outbound pulses from a particular pulser 3021 to multiple of the input ports 221 at the same time; and multiple of the pulsers 3020 -302L-1 generating pulses for the same input port 221 at the same time; at any given time, the output manager 360 is operable to concurrently route K of the digital signals CP0-CPL-1 as K independent outbound pulses, concurrently route K/2 of the digital signals CP0-CPL-1 as two-pulse pairs, or route some of signals CP0-CPL-1 as independent outbound pulses and some others of the signals CP0-CPL-1 as multi-pulse sets (at different times and/or concurrently); ¶¶ [0060]-[0071] with FIGS. 2A, 3 and 5: the pulse operations circuitry 358 comprises a plurality of pulse modification circuits 5080-508R-1 (R is an integer≥1 in general, and R=L/2 in the example shown); the pulse operations manager 356 comprises control circuitry 502, routing circuitry 506, and a plurality of modification settings circuits 5040-504K-1; two of the pulsers 3020-302L-1 may generate two raw outbound pulses which are a phase-quadrature pulse pair; assuming CP1 and CP2 are a phase-quadrature pulse pair to be output; in this example, pulse operations circuitry 358 may process CP1 and CP2 by multiplying a vector representation of CP'1 and CP'2 by one or more 2 by 2 matrices to: (a) perform single-sideband-modulation, where ω is the frequency of the single side band modulation and TS is the time passed since the reference time (e.g. the beginning of a certain control protocol); (b) keep track of frame-of-reference rotations, where ϕ is the total phase that the frame of reference accumulated since the reference time; and/or (c) perform an IQ-mixer correction where C00, C01, C10, and C11 are the elements of a matrix that corrects for IQ-mixer imperfections; each modification settings circuit, 504k, contains registers that contain the matrix elements of three matrices: an IQ-mixer correction matrix Ck; a single sideband frequency modulation matrix Sk; and a frame rotation matrix Fk, which rotates the IQ axes around the axis perpendicular to the IQ plane (i.e. the z-axis if I and Q are the x-axis and y-axis); each pulse modification circuit 508r is operable to process two raw outbound pulses CP'2r and CP'2r+1; such processing may comprise adjusting a phase, frequency, and/or amplitude of the raw outbound pulses CP'2r and CP'2r+1; pulse modification settings output to pulse operations circuitry 358 are specifically tailored to each raw outbound pulse (e.g., to which quantum element 226 or 228 the pulse is destined, to which input port 221 of front-end circuitry 254 the pulse is destined, etc.) to be processed by pulse operations circuitry 358; each path a pulse may travel to the quantum processor 218 via frontend circuitry 254 may have particular characteristics (e.g., non-idealities of interconnect, mixers, switches, attenuators, amplifiers, and/or circuits along the paths) to be accounted for by the pulse modification operations; similarly, each quantum element 1220-122k may have a particular characteristics (e.g. resonance frequency, frame of reference, etc.); the routing circuitry 506 is operable to route modification settings from the modification settings circuits 5040 -504L-1 to the pulse operations circuit 358 and to the pulsers 3020-302L-1; the pulser 3021 may determine ops_slct1 based on the particular quantum element 122k and/or signal path to which the pulse is to be transmitted (e.g., the resonant frequency of the quantum element, frame of reference, and/or mixer correction); the determination of which quantum element and/or signal path to which a particular pulser 3021 is to send an outbound pulse at a particular time may be predetermined in the pulse generation program and quantum machine specification 206 or may be determined based on calculations performed by the pulser 3021 and/or others of the pulsers 3020-302L-1 during runtime; the digital signal IFI instructs the pulse operations manager 356 to update a frequency setting of the modification settings circuit 504k indicated by ops_slct1; ¶¶ [0072]-[0079] with FIGS.3 and 6A-B: the frequency generation circuitry is part of control circuitry 502 of pulse operations manager circuitry 356; each CORDIC circuit 602k is operable to compute cosine and sine of its input, θk, thus generating two signals cos(θk) and sin(θk); the phase generation circuitry 604 is operable to generate the CORD IC input parameters θ0-θk-1 based on: (a) the frequency setting signals IF0-IFL-1 from the pulsers 3020-302L-1; and (b) the contents, TS, of the timestamp register 606; the timestamp register 606 comprises circuitry (e.g., a counter incremented on each cycle of the clock signal clk1) operable to track the number of cycles of clk1 since a reference point in time (e.g., power up of the quantum controller 210, start of execution of set of instructions of a pulse generation program by the quantum controller 210, etc.); the phase generation circuitry 604 sets θ0=2πf0(TS)(dtclk1), where f0 is a frequency determined from the signal IF0, TS is the number of clock cycles counted from the reference point and dtclk1 is the duration of a single clock cycle of clk1; this leads to the CORD IC outputs being a pair of phase-quadrature reference signals, cos(2πf0(TS)(dtclk1)) and sin(2πf0(TS)(dtclk1)), as in the example shown, which are used to generate the S0 rotation matrix that rotates at a frequency f0; as shown in FIG. 6B, the signal IFI may comprise an update component and an fI component; when updateI is asserted then the phase generation circuitry updates one of more of f0-fk-1 to be the value of fI; the S-matrix generation circuitry 608 is operable to build the matrices S0-SK-1 from the outputs of the CORDIC circuits 6020-602K-1; the S-matrix generation circuit 608 is operable to synchronize changes to the S matrices such that any matrix update occurs on a desired cycle of clock clk1 (which may be determined by the control information IF0-IFL- 1); in instances that more than K frequencies are needed over the course of a set of instructions, the phase generation circuit 604 is operable to change the input parameter θk of one or more of the CORDIC circuits 6020-602K-1 to stop generating one frequency and start generating the K+1th frequency; it may be necessary for the new frequency to start at a phase θ that would have been the phase if the new frequency was being generated from the initial reference time (e.g., because the new frequency would be used to address a quantum element that has a resonance at the new frequency and that was coherent since the reference point); in some other instances, it might be necessary to start the new frequency from the phase that the old frequency ended in; ¶ [0093]: patternz of signal Pz may be determined based on: the destination(s) of signal Pz; characteristics of the corresponding quantum control pulse (e.g., any one or more of its frequency, phase, amplitude, and/or duration); and/or process, temperature, and/or voltage variations; ¶¶ [0105]-[0106] with FIG. 2A: an element that a quantum machine may contain is a mixer of front-end circuitry 254; to correct for mixer imbalances, the in-phase/quadrature (10) waveforms of the pulse can be multiplied by a 2x2 mixer correction matrix before being sent to the output ports; this mixer correction matrix, determined via a calibration routine, may be frequency dependent; thus, a mixer definition may include the mixer's name and a list of one or more frequencies and the correction matrix to be used at each frequency; in one example implementation, the correction matrix is loaded into corresponding pulse modification circuit during compilation; similarly, an element definition may include an intermediate frequency with which every pulse sent to the element is to be modulated; when generating local oscillators for quantum control, it is desirable to minimize phase noise at offset from the carrier frequency that are determined by typical quantum gate(s) times, and typical quantum element coherence times; e.g., for one quantum system with shorter gate time it may be desirable to minimize phase noise in the range of 10 MHz to 100 MHz, whereas for another quantum system with longer gate times, it may be desirable to minimize phase noise in the range of 100 Hz to 100 kHz; also, the tolerable amount of phase noise may depend on the quantum system being controlled and/or the quantum algorithm being performed; some systems and/or algorithms can tolerate higher phase noise' laboratories using these systems and/or running these algorithms could benefit from a lower-cost implementation of multi-tone generator 222; ¶¶ [0107]-[0111] with FIGS. 2A and 10: a quantum control multi-tone generator (e.g., multi-tone generator 222) comprising oven-controlled crystal oscillator (OCXO) and signal processing circuitry 1002; the signal processing circuitry is operable to perform splitting, frequency multiplication, gain adjustment, filtering, and/or other signal processing operations to generate M+1 local oscillator signals 1003 from the OCXO output 1001; the signal 1001 is at frequency fi, ID is a multiple of fi, each of the signals 223 is at a multiple of ID, and each of k and M are integers; the use of multiple fixed-frequency tones, avoids the need for the voltage controlled oscillators and phase locked loops used in the signal generators conventionally used for driving quantum systems, which has the benefit of greatly reducing phase noise in the circuitry 222 (in general VCOs introduce additional phase noise as compared to OCXOs); the quantum control multi-tone generator 222 also comprises a variable frequency signal generator 1004 operable to output a signal 231 having a variable (i.e., tunable) frequency; the variable frequency generator 1004 may be driven by the same reference signal that is input to the OCXO 1000 (e.g., a 10 MHz signal) and/or may be driven by the signal 1001 output by OXCO 1000 (e.g., a 1000 MHz signal); the use of a single fundamental frequency, fi, which is then upconverted to the output frequencies using mixers, amplifiers, and bandpass filters provides positive phase correlation between the phase noises of the outputs; this generation of coherent tones through multiplication and filtering of a common reference signal may increase quantum gate fidelity in scenarios where multiple sequential single-gate operations are applied to qubits that are operating using different frequency tones, as well as two-qubit gate operations; the signal processing circuit 1002 performs fanout, frequency multiplication, amplification, and filtration functions; ¶¶ [0112]-[0141] with FIGS. 11A-D: a quantum control multi-tone generator in FIG. 11A including the OCXO 1000 and the circuit 1002 which outputs M multiples of the fi; each of the outputs of circuit 1002 is then input to circuitry comprising a PLL and DRO 1120 in a feedback arrangement to generate a signal 223; the DROs have the effect of lowering phase noise in the signals 223 at frequencies far from the carrier frequency; a quantum control multi-tone generator in FIG. 11B uses only a single DRO 1120 and PLL 1104; the outputs of circuit 1002 and the DRO 1120 feed a signal processing circuit 1122 which mixes the signals 11060-1106N-1 (N is an integer) to generate signals 2230-223M-1; which of the N+1 signals 11060-1106N-1 is selected as signal 1106q (q is an integer where 0≤q≤N-1) to be input to the PLL 1104 may be determined (e.g., preconfigured or controlled programmatically during operation via signal(s) 253, 255, 257, and/or 259) based on the desired frequencies of the signals 2230-223M; the number of signals 223 and/or the frequency spacing of the signals 223 may be determined based on the range of frequencies that the control circuitry 502 of quantum controller 210 is configured to generate; the circuit 1002 may comprise one or more frequency multiplier circuits 1052; each circuit 1150 comprises M, an integer, multiplier circuits 1052, each of which generates an output signal that is an integer multiple of its input signal (in addition to the frequency multiplication, each circuit 1052 may also perform filtering and/or other signal conditioning operations such as current and/or voltage amplification to make the output signal suitable for driving one or more of: another multiplication circuit 1052, a PLL such as 1104, mixer(s) of the circuit 1122, and/or one or more inputs of the circuit 224; the circuit 1122 may comprise one or more mixer circuits 1152; through setting (either at design time or in the field using jumpers, variable resistors, switches, etc.) the multiplication factors of each multiplier 1052, the number of circuits 1150, the number of circuits 1152, and/or the interconnection of the circuits 1150 and 1152, a wide range of frequencies and channel spacings can be achieved to support a wide range of quantum processors and a wide range of quantum controllers; e.g., the multipliers are configured and connected to achieve 24 output frequencies spaced at 4fi, as follows: (a) circuit 11500 outputs: (i) fi, which drives an output port of the multitone generator 222; (ii) 4fi, which drives the input of circuit 11501, and is the basis for the frequency spacing; and (iii) 10fi, which drives an output port of the multitone generator 222; (b) circuit 11501 outputs: (i) 4fi, which drives an input of each of circuits 11520 , 11521 , and 11522; (ii) 8fi, which drives an input of each of circuits 11520 , 11521 , and 11522; (iii) 12fi, which drives an input of each of circuits 11520 , 11521 , and 11522; and (iv) 16fi, which drives an input of circuit 11502; (c) circuit 11502 outputs: (i) 16fi, which drives an output port of the multitone generator 222; (ii) 32fi, which drives an input of circuit 11520; (iii) 48fi, which drives an input of circuit 11521; (iii) 64fi which drives an input of circuit 11522; and (iv) 80fi, which drives an output port of the multitone generator 222; (d)circuit 11520 receives 4fi, 8fi, 12fi, and 32fi and outputs 28fi, 36fi, 40fi, 24fi, 44fi, and 20fi; (e) circuit 11521 receives 4fi, 8fi, 12fi, and 48fi and outputs 52fi, 44fi, 56fi, 40fi, 60fi, and 36fi; and (f) circuit 11522 receives 4fi, 8fi, 12fi, and 64fi and outputs 68fi, 60fi, 72fi, 56fi, 76fi, and 52fi; the multi-tone generator is operable to generate a plurality of fixed-frequency signals from a single fixed-frequency reference signal (e.g., 2230 -2237), and output the plurality of fixed-frequency signals via a corresponding plurality of output ports (e.g., ports of 222); each of the plurality of fixed-frequency signals may be at a different one of a plurality of frequencies from a first frequency (e.g., 2.5 GHz) to a second frequency (e.g., 6 GHz); the frequency spacing between frequency-adjacent signals of the plurality of fixed-frequency signals may be less than or equal to a range of frequencies (e.g., a range of 500 MHz) at which the quantum control pulse generation circuitry is configured to generate a pulse signal (e.g., AO0) such that any frequency in the range from the first frequency to the second frequency for controlling quantum elements can be achieved through tuning of the pulse signal and mixing of the pulse signal with one of the plurality of fixed-frequency signals; the quantum control pulse generation circuit may be operable to generate baseband pulses, and upconvert the baseband pulses to an intermediate frequency to generate the quantum control pulses, wherein the intermediate frequency is tunable over a range at least as large as the first frequency spacing).
Claim 5
Szmuk in view of Negoro discloses all the elements as stated in Claim 2 and further discloses wherein the logic circuit acquires the phase setting signal, which is the set phase minus the phase shift amount, from an external source, and outputs a frequency modulation signal based on the acquired phase setting signal (Szmuk, ¶¶ [0040]-[0054] with FIGS. 2A and 3: the signal routing and multiplexing/demultiplexing functions performed by the input manager 352 enables: a particular pulser 302I to process different inbound pulses from different quantum elements at different times; a particular pulser 302I to process different inbound pulses from different quantum elements at the same time; and multiple of the pulsers 3020-302L-1 to processes the same inbound pulse at the same time; each pulser circuit 302I (I between 0 and L-1) comprises circuitry operable to generate outbound pulses according to quantum control operations to be performed on the quantum processor 218; this involves very precisely controlling characteristics such as phase, frequency, amplitude, and timing of the outbound pulses; the outbound pulses may be, e.g., control pulses sent to the quantum processor 218 to manipulate one or more properties of one or more quantum elements — e.g., manipulate a state of one or more qubits, manipulate a frequency of a qubit using flux biasing, etc., and/or readout a state of one or more quantum elements; the characteristics of an outbound pulse generated at any particular time may be determined, at least in part, on inbound pulses received from the quantum processor 218 via frontend circuitry 220 at a prior time; the time required to close the feedback loop (i.e., time from receiving a first pulse on an output 217 of front-end circuitry 254 to sending a second pulse (e.g., at an input 221 of front-end circuitry 254), where the second pulse is based on the first pulse, is significantly less than the coherence time of the qubits of the quantum processor 218; pulser 302I may process the inbound signal AII to determine the state of certain quantum element(s) in the quantum processor 218 and use this state information for making decisions such as, e.g., which raw outbound pulse CP'I to generate next, when to generate it, and what control signals to generate to affect the characteristics of that raw outbound pulse appropriately; the pulse operations circuitry 358 is operable to process the raw outbound pulses CP'0 -CP'L-1 to generate corresponding output outbound pulses CP0-CPL-1; this may comprise, e.g.,, manipulating the amplitude, phase, and/or frequency of the raw pulse CP'I; the pulse operations manager 356 comprises circuitry operable to configure the pulse operations circuitry 358 such that the pulse operations applied to each raw outbound pulse CP'l are tailored to that particular raw outbound pulse; denoting a first raw outbound pulse to be output during a first time interval T1 as CP'l,T1, and a second raw outbound pulse to be output during a second time interval T2 as CP'l,T2, then pulse operations circuitry 358 is operable to perform a first one or more operations on CP'l,T1 and a second one or more operations on CP'l,T2; the first one or more operations may be determined, at least in part, based on to which quantum element the pulse CP'l,T1 is to be sent, and the second one or more operations may be determined, at least in part, based on to which quantum element the pulse CP'l,T2 is to be sent; the determination of the first one or more operations and second one or more operations may be performed dynamically during runtime; the output manager 360 enables: routing outbound pulses from a particular pulser 3021 to different ones input ports 221 at different times; routing outbound pulses from a particular pulser 3021 to multiple of the input ports 221 at the same time; and multiple of the pulsers 3020 -302L-1 generating pulses for the same input port 221 at the same time; at any given time, the output manager 360 is operable to concurrently route K of the digital signals CP0-CPL-1 as K independent outbound pulses, concurrently route K/2 of the digital signals CP0-CPL-1 as two-pulse pairs, or route some of signals CP0-CPL-1 as independent outbound pulses and some others of the signals CP0-CPL-1 as multi-pulse sets (at different times and/or concurrently); ¶¶ [0060]-[0071] with FIGS. 2A, 3 and 5: the pulse operations circuitry 358 comprises a plurality of pulse modification circuits 5080-508R-1 (R is an integer≥1 in general, and R=L/2 in the example shown); the pulse operations manager 356 comprises control circuitry 502, routing circuitry 506, and a plurality of modification settings circuits 5040-504K-1; two of the pulsers 3020-302L-1 may generate two raw outbound pulses which are a phase-quadrature pulse pair; assuming CP1 and CP2 are a phase-quadrature pulse pair to be output; in this example, pulse operations circuitry 358 may process CP1 and CP2 by multiplying a vector representation of CP'1 and CP'2 by one or more 2 by 2 matrices to: (a) perform single-sideband-modulation, where ω is the frequency of the single side band modulation and TS is the time passed since the reference time (e.g. the beginning of a certain control protocol); (b) keep track of frame-of-reference rotations, where ϕ is the total phase that the frame of reference accumulated since the reference time; and/or (c) perform an IQ-mixer correction where C00, C01, C10, and C11 are the elements of a matrix that corrects for IQ-mixer imperfections; each modification settings circuit, 504k, contains registers that contain the matrix elements of three matrices: an IQ-mixer correction matrix Ck; a single sideband frequency modulation matrix Sk; and a frame rotation matrix Fk, which rotates the IQ axes around the axis perpendicular to the IQ plane (i.e. the z-axis if I and Q are the x-axis and y-axis); each pulse modification circuit 508r is operable to process two raw outbound pulses CP'2r and CP'2r+1; such processing may comprise adjusting a phase, frequency, and/or amplitude of the raw outbound pulses CP'2r and CP'2r+1; pulse modification settings output to pulse operations circuitry 358 are specifically tailored to each raw outbound pulse (e.g., to which quantum element 226 or 228 the pulse is destined, to which input port 221 of front-end circuitry 254 the pulse is destined, etc.) to be processed by pulse operations circuitry 358; each path a pulse may travel to the quantum processor 218 via frontend circuitry 254 may have particular characteristics (e.g., non-idealities of interconnect, mixers, switches, attenuators, amplifiers, and/or circuits along the paths) to be accounted for by the pulse modification operations; similarly, each quantum element 1220-122k may have a particular characteristics (e.g. resonance frequency, frame of reference, etc.); the routing circuitry 506 is operable to route modification settings from the modification settings circuits 5040 -504L-1 to the pulse operations circuit 358 and to the pulsers 3020-302L-1; the pulser 3021 may determine ops_slct1 based on the particular quantum element 122k and/or signal path to which the pulse is to be transmitted (e.g., the resonant frequency of the quantum element, frame of reference, and/or mixer correction); the determination of which quantum element and/or signal path to which a particular pulser 3021 is to send an outbound pulse at a particular time may be predetermined in the pulse generation program and quantum machine specification 206 or may be determined based on calculations performed by the pulser 3021 and/or others of the pulsers 3020-302L-1 during runtime; the digital signal IFI instructs the pulse operations manager 356 to update a frequency setting of the modification settings circuit 504k indicated by ops_slct1; ¶¶ [0072]-[0079] with FIGS.3 and 6A-B: the frequency generation circuitry is part of control circuitry 502 of pulse operations manager circuitry 356; each CORDIC circuit 602k is operable to compute cosine and sine of its input, θk, thus generating two signals cos(θk) and sin(θk); the phase generation circuitry 604 is operable to generate the CORD IC input parameters θ0-θk-1 based on: (a) the frequency setting signals IF0-IFL-1 from the pulsers 3020-302L-1; and (b) the contents, TS, of the timestamp register 606; the timestamp register 606 comprises circuitry (e.g., a counter incremented on each cycle of the clock signal clk1) operable to track the number of cycles of clk1 since a reference point in time (e.g., power up of the quantum controller 210, start of execution of set of instructions of a pulse generation program by the quantum controller 210, etc.); the phase generation circuitry 604 sets θ0=2πf0(TS)(dtclk1), where f0 is a frequency determined from the signal IF0, TS is the number of clock cycles counted from the reference point and dtclk1 is the duration of a single clock cycle of clk1; this leads to the CORD IC outputs being a pair of phase-quadrature reference signals, cos(2πf0(TS)(dtclk1)) and sin(2πf0(TS)(dtclk1)), as in the example shown, which are used to generate the S0 rotation matrix that rotates at a frequency f0; as shown in FIG. 6B, the signal IFI may comprise an update component and an fI component; when updateI is asserted then the phase generation circuitry updates one of more of f0-fk-1 to be the value of fI; the S-matrix generation circuitry 608 is operable to build the matrices S0-SK-1 from the outputs of the CORDIC circuits 6020-602K-1; the S-matrix generation circuit 608 is operable to synchronize changes to the S matrices such that any matrix update occurs on a desired cycle of clock clk1 (which may be determined by the control information IF0-IFL- 1); in instances that more than K frequencies are needed over the course of a set of instructions, the phase generation circuit 604 is operable to change the input parameter θk of one or more of the CORDIC circuits 6020-602K-1 to stop generating one frequency and start generating the K+1th frequency; it may be necessary for the new frequency to start at a phase θ that would have been the phase if the new frequency was being generated from the initial reference time (e.g., because the new frequency would be used to address a quantum element that has a resonance at the new frequency and that was coherent since the reference point); in some other instances, it might be necessary to start the new frequency from the phase that the old frequency ended in; ¶ [0093]: patternz of signal Pz may be determined based on: the destination(s) of signal Pz; characteristics of the corresponding quantum control pulse (e.g., any one or more of its frequency, phase, amplitude, and/or duration); and/or process, temperature, and/or voltage variations; ¶¶ [0105]-[0106] with FIG. 2A: an element that a quantum machine may contain is a mixer of front-end circuitry 254; to correct for mixer imbalances, the in-phase/quadrature (10) waveforms of the pulse can be multiplied by a 2x2 mixer correction matrix before being sent to the output ports; this mixer correction matrix, determined via a calibration routine, may be frequency dependent; thus, a mixer definition may include the mixer's name and a list of one or more frequencies and the correction matrix to be used at each frequency; in one example implementation, the correction matrix is loaded into corresponding pulse modification circuit during compilation; similarly, an element definition may include an intermediate frequency with which every pulse sent to the element is to be modulated; when generating local oscillators for quantum control, it is desirable to minimize phase noise at offset from the carrier frequency that are determined by typical quantum gate(s) times, and typical quantum element coherence times; e.g., for one quantum system with shorter gate time it may be desirable to minimize phase noise in the range of 10 MHz to 100 MHz, whereas for another quantum system with longer gate times, it may be desirable to minimize phase noise in the range of 100 Hz to 100 kHz; also, the tolerable amount of phase noise may depend on the quantum system being controlled and/or the quantum algorithm being performed; some systems and/or algorithms can tolerate higher phase noise' laboratories using these systems and/or running these algorithms could benefit from a lower-cost implementation of multi-tone generator 222; ¶¶ [0107]-[0111] with FIGS. 2A and 10: a quantum control multi-tone generator (e.g., multi-tone generator 222) comprising oven-controlled crystal oscillator (OCXO) and signal processing circuitry 1002; the signal processing circuitry is operable to perform splitting, frequency multiplication, gain adjustment, filtering, and/or other signal processing operations to generate M+1 local oscillator signals 1003 from the OCXO output 1001; the signal 1001 is at frequency fi, ID is a multiple of fi, each of the signals 223 is at a multiple of ID, and each of k and M are integers; the use of multiple fixed-frequency tones, avoids the need for the voltage controlled oscillators and phase locked loops used in the signal generators conventionally used for driving quantum systems, which has the benefit of greatly reducing phase noise in the circuitry 222 (in general VCOs introduce additional phase noise as compared to OCXOs); the quantum control multi-tone generator 222 also comprises a variable frequency signal generator 1004 operable to output a signal 231 having a variable (i.e., tunable) frequency; the variable frequency generator 1004 may be driven by the same reference signal that is input to the OCXO 1000 (e.g., a 10 MHz signal) and/or may be driven by the signal 1001 output by OXCO 1000 (e.g., a 1000 MHz signal); the use of a single fundamental frequency, fi, which is then upconverted to the output frequencies using mixers, amplifiers, and bandpass filters provides positive phase correlation between the phase noises of the outputs; this generation of coherent tones through multiplication and filtering of a common reference signal may increase quantum gate fidelity in scenarios where multiple sequential single-gate operations are applied to qubits that are operating using different frequency tones, as well as two-qubit gate operations; the signal processing circuit 1002 performs fanout, frequency multiplication, amplification, and filtration functions; ¶¶ [0112]-[0141] with FIGS. 11A-D: a quantum control multi-tone generator in FIG. 11A including the OCXO 1000 and the circuit 1002 which outputs M multiples of the fi; each of the outputs of circuit 1002 is then input to circuitry comprising a PLL and DRO 1120 in a feedback arrangement to generate a signal 223; the DROs have the effect of lowering phase noise in the signals 223 at frequencies far from the carrier frequency; a quantum control multi-tone generator in FIG. 11B uses only a single DRO 1120 and PLL 1104; the outputs of circuit 1002 and the DRO 1120 feed a signal processing circuit 1122 which mixes the signals 11060-1106N-1 (N is an integer) to generate signals 2230-223M-1; which of the N+1 signals 11060-1106N-1 is selected as signal 1106q (q is an integer where 0≤q≤N-1) to be input to the PLL 1104 may be determined (e.g., preconfigured or controlled programmatically during operation via signal(s) 253, 255, 257, and/or 259) based on the desired frequencies of the signals 2230-223M; the number of signals 223 and/or the frequency spacing of the signals 223 may be determined based on the range of frequencies that the control circuitry 502 of quantum controller 210 is configured to generate; the circuit 1002 may comprise one or more frequency multiplier circuits 1052; each circuit 1150 comprises M, an integer, multiplier circuits 1052, each of which generates an output signal that is an integer multiple of its input signal (in addition to the frequency multiplication, each circuit 1052 may also perform filtering and/or other signal conditioning operations such as current and/or voltage amplification to make the output signal suitable for driving one or more of: another multiplication circuit 1052, a PLL such as 1104, mixer(s) of the circuit 1122, and/or one or more inputs of the circuit 224; the circuit 1122 may comprise one or more mixer circuits 1152; through setting (either at design time or in the field using jumpers, variable resistors, switches, etc.) the multiplication factors of each multiplier 1052, the number of circuits 1150, the number of circuits 1152, and/or the interconnection of the circuits 1150 and 1152, a wide range of frequencies and channel spacings can be achieved to support a wide range of quantum processors and a wide range of quantum controllers; e.g., the multipliers are configured and connected to achieve 24 output frequencies spaced at 4fi, as follows: (a) circuit 11500 outputs: (i) fi, which drives an output port of the multitone generator 222; (ii) 4fi, which drives the input of circuit 11501, and is the basis for the frequency spacing; and (iii) 10fi, which drives an output port of the multitone generator 222; (b) circuit 11501 outputs: (i) 4fi, which drives an input of each of circuits 11520 , 11521 , and 11522; (ii) 8fi, which drives an input of each of circuits 11520 , 11521 , and 11522; (iii) 12fi, which drives an input of each of circuits 11520 , 11521 , and 11522; and (iv) 16fi, which drives an input of circuit 11502; (c) circuit 11502 outputs: (i) 16fi, which drives an output port of the multitone generator 222; (ii) 32fi, which drives an input of circuit 11520; (iii) 48fi, which drives an input of circuit 11521; (iii) 64fi which drives an input of circuit 11522; and (iv) 80fi, which drives an output port of the multitone generator 222; (d)circuit 11520 receives 4fi, 8fi, 12fi, and 32fi and outputs 28fi, 36fi, 40fi, 24fi, 44fi, and 20fi; (e) circuit 11521 receives 4fi, 8fi, 12fi, and 48fi and outputs 52fi, 44fi, 56fi, 40fi, 60fi, and 36fi; and (f) circuit 11522 receives 4fi, 8fi, 12fi, and 64fi and outputs 68fi, 60fi, 72fi, 56fi, 76fi, and 52fi; the multi-tone generator is operable to generate a plurality of fixed-frequency signals from a single fixed-frequency reference signal (e.g., 2230 -2237), and output the plurality of fixed-frequency signals via a corresponding plurality of output ports (e.g., ports of 222); each of the plurality of fixed-frequency signals may be at a different one of a plurality of frequencies from a first frequency (e.g., 2.5 GHz) to a second frequency (e.g., 6 GHz); the frequency spacing between frequency-adjacent signals of the plurality of fixed-frequency signals may be less than or equal to a range of frequencies (e.g., a range of 500 MHz) at which the quantum control pulse generation circuitry is configured to generate a pulse signal (e.g., AO0) such that any frequency in the range from the first frequency to the second frequency for controlling quantum elements can be achieved through tuning of the pulse signal and mixing of the pulse signal with one of the plurality of fixed-frequency signals; the quantum control pulse generation circuit may be operable to generate baseband pulses, and upconvert the baseband pulses to an intermediate frequency to generate the quantum control pulses, wherein the intermediate frequency is tunable over a range at least as large as the first frequency spacing).
Claim 7
Szmuk in view of Negoro discloses all the elements as stated in Claim 2 and further discloses phase correction data that corrects the frequency shift of the plurality of quantum bits in the quantum bit array, wherein the frequency generator outputs a sine wave based on the phase correction data of the selected quantum bit (Szmuk, ¶¶ [0040]-[0054] with FIGS. 2A and 3: the signal routing and multiplexing/demultiplexing functions performed by the input manager 352 enables: a particular pulser 302I to process different inbound pulses from different quantum elements at different times; a particular pulser 302I to process different inbound pulses from different quantum elements at the same time; and multiple of the pulsers 3020-302L-1 to processes the same inbound pulse at the same time; each pulser circuit 302I (I between 0 and L-1) comprises circuitry operable to generate outbound pulses according to quantum control operations to be performed on the quantum processor 218; this involves very precisely controlling characteristics such as phase, frequency, amplitude, and timing of the outbound pulses; the outbound pulses may be, e.g., control pulses sent to the quantum processor 218 to manipulate one or more properties of one or more quantum elements — e.g., manipulate a state of one or more qubits, manipulate a frequency of a qubit using flux biasing, etc., and/or readout a state of one or more quantum elements; the characteristics of an outbound pulse generated at any particular time may be determined, at least in part, on inbound pulses received from the quantum processor 218 via frontend circuitry 220 at a prior time; the time required to close the feedback loop (i.e., time from receiving a first pulse on an output 217 of front-end circuitry 254 to sending a second pulse (e.g., at an input 221 of front-end circuitry 254), where the second pulse is based on the first pulse, is significantly less than the coherence time of the qubits of the quantum processor 218; pulser 302I may process the inbound signal AII to determine the state of certain quantum element(s) in the quantum processor 218 and use this state information for making decisions such as, e.g., which raw outbound pulse CP'I to generate next, when to generate it, and what control signals to generate to affect the characteristics of that raw outbound pulse appropriately; the pulse operations circuitry 358 is operable to process the raw outbound pulses CP'0 -CP'L-1 to generate corresponding output outbound pulses CP0-CPL-1; this may comprise, e.g.,, manipulating the amplitude, phase, and/or frequency of the raw pulse CP'I; the pulse operations manager 356 comprises circuitry operable to configure the pulse operations circuitry 358 such that the pulse operations applied to each raw outbound pulse CP'l are tailored to that particular raw outbound pulse; denoting a first raw outbound pulse to be output during a first time interval T1 as CP'l,T1, and a second raw outbound pulse to be output during a second time interval T2 as CP'l,T2, then pulse operations circuitry 358 is operable to perform a first one or more operations on CP'l,T1 and a second one or more operations on CP'l,T2; the first one or more operations may be determined, at least in part, based on to which quantum element the pulse CP'l,T1 is to be sent, and the second one or more operations may be determined, at least in part, based on to which quantum element the pulse CP'l,T2 is to be sent; the determination of the first one or more operations and second one or more operations may be performed dynamically during runtime; the output manager 360 enables: routing outbound pulses from a particular pulser 3021 to different ones input ports 221 at different times; routing outbound pulses from a particular pulser 3021 to multiple of the input ports 221 at the same time; and multiple of the pulsers 3020 -302L-1 generating pulses for the same input port 221 at the same time; at any given time, the output manager 360 is operable to concurrently route K of the digital signals CP0-CPL-1 as K independent outbound pulses, concurrently route K/2 of the digital signals CP0-CPL-1 as two-pulse pairs, or route some of signals CP0-CPL-1 as independent outbound pulses and some others of the signals CP0-CPL-1 as multi-pulse sets (at different times and/or concurrently); ¶¶ [0060]-[0071] with FIGS. 2A, 3 and 5: the pulse operations circuitry 358 comprises a plurality of pulse modification circuits 5080-508R-1 (R is an integer≥1 in general, and R=L/2 in the example shown); the pulse operations manager 356 comprises control circuitry 502, routing circuitry 506, and a plurality of modification settings circuits 5040-504K-1; two of the pulsers 3020-302L-1 may generate two raw outbound pulses which are a phase-quadrature pulse pair; assuming CP1 and CP2 are a phase-quadrature pulse pair to be output; in this example, pulse operations circuitry 358 may process CP1 and CP2 by multiplying a vector representation of CP'1 and CP'2 by one or more 2 by 2 matrices to: (a) perform single-sideband-modulation, where ω is the frequency of the single side band modulation and TS is the time passed since the reference time (e.g. the beginning of a certain control protocol); (b) keep track of frame-of-reference rotations, where ϕ is the total phase that the frame of reference accumulated since the reference time; and/or (c) perform an IQ-mixer correction where C00, C01, C10, and C11 are the elements of a matrix that corrects for IQ-mixer imperfections; each modification settings circuit, 504k, contains registers that contain the matrix elements of three matrices: an IQ-mixer correction matrix Ck; a single sideband frequency modulation matrix Sk; and a frame rotation matrix Fk, which rotates the IQ axes around the axis perpendicular to the IQ plane (i.e. the z-axis if I and Q are the x-axis and y-axis); each pulse modification circuit 508r is operable to process two raw outbound pulses CP'2r and CP'2r+1; such processing may comprise adjusting a phase, frequency, and/or amplitude of the raw outbound pulses CP'2r and CP'2r+1; pulse modification settings output to pulse operations circuitry 358 are specifically tailored to each raw outbound pulse (e.g., to which quantum element 226 or 228 the pulse is destined, to which input port 221 of front-end circuitry 254 the pulse is destined, etc.) to be processed by pulse operations circuitry 358; each path a pulse may travel to the quantum processor 218 via frontend circuitry 254 may have particular characteristics (e.g., non-idealities of interconnect, mixers, switches, attenuators, amplifiers, and/or circuits along the paths) to be accounted for by the pulse modification operations; similarly, each quantum element 1220-122k may have a particular characteristics (e.g. resonance frequency, frame of reference, etc.); the routing circuitry 506 is operable to route modification settings from the modification settings circuits 5040 -504L-1 to the pulse operations circuit 358 and to the pulsers 3020-302L-1; the pulser 3021 may determine ops_slct1 based on the particular quantum element 122k and/or signal path to which the pulse is to be transmitted (e.g., the resonant frequency of the quantum element, frame of reference, and/or mixer correction); the determination of which quantum element and/or signal path to which a particular pulser 3021 is to send an outbound pulse at a particular time may be predetermined in the pulse generation program and quantum machine specification 206 or may be determined based on calculations performed by the pulser 3021 and/or others of the pulsers 3020-302L-1 during runtime; the digital signal IFI instructs the pulse operations manager 356 to update a frequency setting of the modification settings circuit 504k indicated by ops_slct1; ¶¶ [0072]-[0079] with FIGS.3 and 6A-B: the frequency generation circuitry is part of control circuitry 502 of pulse operations manager circuitry 356; each CORDIC circuit 602k is operable to compute cosine and sine of its input, θk, thus generating two signals cos(θk) and sin(θk); the phase generation circuitry 604 is operable to generate the CORD IC input parameters θ0-θk-1 based on: (a) the frequency setting signals IF0-IFL-1 from the pulsers 3020-302L-1; and (b) the contents, TS, of the timestamp register 606; the timestamp register 606 comprises circuitry (e.g., a counter incremented on each cycle of the clock signal clk1) operable to track the number of cycles of clk1 since a reference point in time (e.g., power up of the quantum controller 210, start of execution of set of instructions of a pulse generation program by the quantum controller 210, etc.); the phase generation circuitry 604 sets θ0=2πf0(TS)(dtclk1), where f0 is a frequency determined from the signal IF0, TS is the number of clock cycles counted from the reference point and dtclk1 is the duration of a single clock cycle of clk1; this leads to the CORD IC outputs being a pair of phase-quadrature reference signals, cos(2πf0(TS)(dtclk1)) and sin(2πf0(TS)(dtclk1)), as in the example shown, which are used to generate the S0 rotation matrix that rotates at a frequency f0; as shown in FIG. 6B, the signal IFI may comprise an update component and an fI component; when updateI is asserted then the phase generation circuitry updates one of more of f0-fk-1 to be the value of fI; the S-matrix generation circuitry 608 is operable to build the matrices S0-SK-1 from the outputs of the CORDIC circuits 6020-602K-1; the S-matrix generation circuit 608 is operable to synchronize changes to the S matrices such that any matrix update occurs on a desired cycle of clock clk1 (which may be determined by the control information IF0-IFL- 1); in instances that more than K frequencies are needed over the course of a set of instructions, the phase generation circuit 604 is operable to change the input parameter θk of one or more of the CORDIC circuits 6020-602K-1 to stop generating one frequency and start generating the K+1th frequency; it may be necessary for the new frequency to start at a phase θ that would have been the phase if the new frequency was being generated from the initial reference time (e.g., because the new frequency would be used to address a quantum element that has a resonance at the new frequency and that was coherent since the reference point); in some other instances, it might be necessary to start the new frequency from the phase that the old frequency ended in; ¶ [0093]: patternz of signal Pz may be determined based on: the destination(s) of signal Pz; characteristics of the corresponding quantum control pulse (e.g., any one or more of its frequency, phase, amplitude, and/or duration); and/or process, temperature, and/or voltage variations; ¶¶ [0105]-[0106] with FIG. 2A: an element that a quantum machine may contain is a mixer of front-end circuitry 254; to correct for mixer imbalances, the in-phase/quadrature (10) waveforms of the pulse can be multiplied by a 2x2 mixer correction matrix before being sent to the output ports; this mixer correction matrix, determined via a calibration routine, may be frequency dependent; thus, a mixer definition may include the mixer's name and a list of one or more frequencies and the correction matrix to be used at each frequency; in one example implementation, the correction matrix is loaded into corresponding pulse modification circuit during compilation; similarly, an element definition may include an intermediate frequency with which every pulse sent to the element is to be modulated; when generating local oscillators for quantum control, it is desirable to minimize phase noise at offset from the carrier frequency that are determined by typical quantum gate(s) times, and typical quantum element coherence times; e.g., for one quantum system with shorter gate time it may be desirable to minimize phase noise in the range of 10 MHz to 100 MHz, whereas for another quantum system with longer gate times, it may be desirable to minimize phase noise in the range of 100 Hz to 100 kHz; also, the tolerable amount of phase noise may depend on the quantum system being controlled and/or the quantum algorithm being performed; some systems and/or algorithms can tolerate higher phase noise' laboratories using these systems and/or running these algorithms could benefit from a lower-cost implementation of multi-tone generator 222; ¶¶ [0107]-[0111] with FIGS. 2A and 10: a quantum control multi-tone generator (e.g., multi-tone generator 222) comprising oven-controlled crystal oscillator (OCXO) and signal processing circuitry 1002; the signal processing circuitry is operable to perform splitting, frequency multiplication, gain adjustment, filtering, and/or other signal processing operations to generate M+1 local oscillator signals 1003 from the OCXO output 1001; the signal 1001 is at frequency fi, ID is a multiple of fi, each of the signals 223 is at a multiple of ID, and each of k and M are integers; the use of multiple fixed-frequency tones, avoids the need for the voltage controlled oscillators and phase locked loops used in the signal generators conventionally used for driving quantum systems, which has the benefit of greatly reducing phase noise in the circuitry 222 (in general VCOs introduce additional phase noise as compared to OCXOs); the quantum control multi-tone generator 222 also comprises a variable frequency signal generator 1004 operable to output a signal 231 having a variable (i.e., tunable) frequency; the variable frequency generator 1004 may be driven by the same reference signal that is input to the OCXO 1000 (e.g., a 10 MHz signal) and/or may be driven by the signal 1001 output by OXCO 1000 (e.g., a 1000 MHz signal); the use of a single fundamental frequency, fi, which is then upconverted to the output frequencies using mixers, amplifiers, and bandpass filters provides positive phase correlation between the phase noises of the outputs; this generation of coherent tones through multiplication and filtering of a common reference signal may increase quantum gate fidelity in scenarios where multiple sequential single-gate operations are applied to qubits that are operating using different frequency tones, as well as two-qubit gate operations; the signal processing circuit 1002 performs fanout, frequency multiplication, amplification, and filtration functions; ¶¶ [0112]-[0141] with FIGS. 11A-D: a quantum control multi-tone generator in FIG. 11A including the OCXO 1000 and the circuit 1002 which outputs M multiples of the fi; each of the outputs of circuit 1002 is then input to circuitry comprising a PLL and DRO 1120 in a feedback arrangement to generate a signal 223; the DROs have the effect of lowering phase noise in the signals 223 at frequencies far from the carrier frequency; a quantum control multi-tone generator in FIG. 11B uses only a single DRO 1120 and PLL 1104; the outputs of circuit 1002 and the DRO 1120 feed a signal processing circuit 1122 which mixes the signals 11060-1106N-1 (N is an integer) to generate signals 2230-223M-1; which of the N+1 signals 11060-1106N-1 is selected as signal 1106q (q is an integer where 0≤q≤N-1) to be input to the PLL 1104 may be determined (e.g., preconfigured or controlled programmatically during operation via signal(s) 253, 255, 257, and/or 259) based on the desired frequencies of the signals 2230-223M; the number of signals 223 and/or the frequency spacing of the signals 223 may be determined based on the range of frequencies that the control circuitry 502 of quantum controller 210 is configured to generate; the circuit 1002 may comprise one or more frequency multiplier circuits 1052; each circuit 1150 comprises M, an integer, multiplier circuits 1052, each of which generates an output signal that is an integer multiple of its input signal (in addition to the frequency multiplication, each circuit 1052 may also perform filtering and/or other signal conditioning operations such as current and/or voltage amplification to make the output signal suitable for driving one or more of: another multiplication circuit 1052, a PLL such as 1104, mixer(s) of the circuit 1122, and/or one or more inputs of the circuit 224; the circuit 1122 may comprise one or more mixer circuits 1152; through setting (either at design time or in the field using jumpers, variable resistors, switches, etc.) the multiplication factors of each multiplier 1052, the number of circuits 1150, the number of circuits 1152, and/or the interconnection of the circuits 1150 and 1152, a wide range of frequencies and channel spacings can be achieved to support a wide range of quantum processors and a wide range of quantum controllers; e.g., the multipliers are configured and connected to achieve 24 output frequencies spaced at 4fi, as follows: (a) circuit 11500 outputs: (i) fi, which drives an output port of the multitone generator 222; (ii) 4fi, which drives the input of circuit 11501, and is the basis for the frequency spacing; and (iii) 10fi, which drives an output port of the multitone generator 222; (b) circuit 11501 outputs: (i) 4fi, which drives an input of each of circuits 11520 , 11521 , and 11522; (ii) 8fi, which drives an input of each of circuits 11520 , 11521 , and 11522; (iii) 12fi, which drives an input of each of circuits 11520 , 11521 , and 11522; and (iv) 16fi, which drives an input of circuit 11502; (c) circuit 11502 outputs: (i) 16fi, which drives an output port of the multitone generator 222; (ii) 32fi, which drives an input of circuit 11520; (iii) 48fi, which drives an input of circuit 11521; (iii) 64fi which drives an input of circuit 11522; and (iv) 80fi, which drives an output port of the multitone generator 222; (d)circuit 11520 receives 4fi, 8fi, 12fi, and 32fi and outputs 28fi, 36fi, 40fi, 24fi, 44fi, and 20fi; (e) circuit 11521 receives 4fi, 8fi, 12fi, and 48fi and outputs 52fi, 44fi, 56fi, 40fi, 60fi, and 36fi; and (f) circuit 11522 receives 4fi, 8fi, 12fi, and 64fi and outputs 68fi, 60fi, 72fi, 56fi, 76fi, and 52fi; the multi-tone generator is operable to generate a plurality of fixed-frequency signals from a single fixed-frequency reference signal (e.g., 2230 -2237), and output the plurality of fixed-frequency signals via a corresponding plurality of output ports (e.g., ports of 222); each of the plurality of fixed-frequency signals may be at a different one of a plurality of frequencies from a first frequency (e.g., 2.5 GHz) to a second frequency (e.g., 6 GHz); the frequency spacing between frequency-adjacent signals of the plurality of fixed-frequency signals may be less than or equal to a range of frequencies (e.g., a range of 500 MHz) at which the quantum control pulse generation circuitry is configured to generate a pulse signal (e.g., AO0) such that any frequency in the range from the first frequency to the second frequency for controlling quantum elements can be achieved through tuning of the pulse signal and mixing of the pulse signal with one of the plurality of fixed-frequency signals; the quantum control pulse generation circuit may be operable to generate baseband pulses, and upconvert the baseband pulses to an intermediate frequency to generate the quantum control pulses, wherein the intermediate frequency is tunable over a range at least as large as the first frequency spacing).
Claim 9
Szmuk in view of Negoro discloses all the elements as stated in Claim 2 and further discloses wherein the converters comprises a DAC that converts the pulse data into an analog signal (Szmuk, ¶ [0049] with FIGS. 2A and 3: the transmit analog frontend 362 comprises circuitry operable to concurrently process up to K digital signals DOk to generate up to K concurrent analog signals AOk to be output to inputs 221 of the front-end circuitry 254; such processing may comprise, e.g., digital-to analog conversion, filtering, upconversion, downconversion, amplification, attenuation, time division multiplexing/demultiplexing, frequency division multiplexing/demultiplexing and/or the like; the transmit analog frontend 362 is operable to process digital signals DO0-DOK-1 as K independent outbound pulses, as K/2 two-pulse pairs, or process some of signals DO0-DOK-1 as independent outbound pulses and some signals DO0-DOK-1 as two-pulse pairs (at different times and/or concurrently)), and a mixer that modulates the analog signal with the sine wave and outputs a signal having the frequency of the sine wave as the center frequency as a microwave pulse (Szmuk, ¶¶ [0032]-[0039] with FIG. 2A-D: the front-end circuitry 254 is operable to receive outbound intermediate frequency (IF) pulses from quantum controller 210 via one or more ports 221, upconvert the IF pulses to RF using the local oscillator signals received via one or more LO ports 229, and output the RF pulses to quantum processor 218 via one or more output ports 225; each IF input port 221 is configured to receive an independent pulse or multi-pulse pair (e.g., an IQ pair of pulses comprising an in-phase pulse and quadrature-phase pulse); in the latter case, the front-end circuitry 254 is operable to perform IQ upconversion; in FIG. 2D, the circuitry 254 comprises 6 IQ mixers 270; each of mixers 2700-2704 receives an IQ pair of IF signals via a respective one of ports 2210-2214, and uses an LO signal received via a respective one of ports 2290-2294 to upconvert the IQ pair to a corresponding RF signal output via a respective one of ports 2250 -2254; the mixer 270s uses the LO received via port 229s to downconvert the RF signal received via port 227 to generate the IF IQ pair output via port 217; the multi-tone generator 222 is operable to generate one or more signals at one or more desired frequencies, which will typically be dictated by the particular quantum processor 218 (e.g., based on the resonant frequencies of quantum elements of the quantum processor 218); two types of outputs are provided by quantum multi-tone generator 222: (a) one or more fixed frequency continuous wave (CW) tones 223; and (b) one or more synthesized frequency signals 231; the connectivity circuitry 224 is operable to couple the outputs of the multi-tone generator 222 to the inputs of the front-end circuitry 254; quantum processor 218 in FIG. 2A comprises four qubits 228 with no tunability, and four readout elements 226 (e.g., superconducting resonators) addressed by the same control line from port 2250; in this case, the QOP requires only a single quantum controller module 250, only a single front-end circuitry module with six mixers, and a single multi-tone generator 222; the connectivity circuitry 224 can connect any one or more of the signals 2230 -2237 and 231 to any one or more of the input ports 2290 -2295 of front-end circuitry 254; because the desired connections between multi-tone generator 222 and quantum processor 218 depends on the architecture and operating frequencies of the quantum processor 218, the connectivity circuitry 224 is configurable by the user to support whatever configurations users may need for their particular quantum algorithms and particular quantum processor 218; ¶ [0050] with FIG. 3: the output manager 360 comprises one or more mixers and/or filters for frequency division multiplexing multiple of the signals CP0-CPM-1 onto a single input port 221 of front-end circuitry 254 and/or frequency division demultiplexing components (e.g., frequency bands) of a signal CP m onto multiple of the input ports 221 of the front-end circuitry 254; the signal routing and multiplexing/demultiplexing functions performed by the output manager 360 enables: routing outbound pulses from a particular pulser 3021 to different ones input ports 221 at different times; routing outbound pulses from a particular pulser 3021 to multiple of the input ports 221 at the same time; and multiple of the pulsers 3020-302L-1 generating pulses for the same input port 221 at the same time; ¶¶ [0060]-[0071] with FIGS. 2A, 3 and 5: the pulse operations circuitry 358 comprises a plurality of pulse modification circuits 5080-508R-1 (R is an integer≥1 in general, and R=L/2 in the example shown); the pulse operations manager 356 comprises control circuitry 502, routing circuitry 506, and a plurality of modification settings circuits 5040-504K-1; two of the pulsers 3020-302L-1 may generate two raw outbound pulses which are a phase-quadrature pulse pair; assuming CP1 and CP2 are a phase-quadrature pulse pair to be output; in this example, pulse operations circuitry 358 may process CP1 and CP2 by multiplying a vector representation of CP'1 and CP'2 by one or more 2 by 2 matrices to: (a) perform single-sideband-modulation, where ω is the frequency of the single side band modulation and TS is the time passed since the reference time (e.g. the beginning of a certain control protocol); (b) keep track of frame-of-reference rotations, where ϕ is the total phase that the frame of reference accumulated since the reference time; and/or (c) perform an IQ-mixer correction where C00, C01, C10, and C11 are the elements of a matrix that corrects for IQ-mixer imperfections; each modification settings circuit, 504k, contains registers that contain the matrix elements of three matrices: an IQ-mixer correction matrix Ck; a single sideband frequency modulation matrix Sk; and a frame rotation matrix Fk, which rotates the IQ axes around the axis perpendicular to the IQ plane (i.e. the z-axis if I and Q are the x-axis and y-axis); each pulse modification circuit 508r is operable to process two raw outbound pulses CP'2r and CP'2r+1; such processing may comprise adjusting a phase, frequency, and/or amplitude of the raw outbound pulses CP'2r and CP'2r+1; pulse modification settings output to pulse operations circuitry 358 are specifically tailored to each raw outbound pulse (e.g., to which quantum element 226 or 228 the pulse is destined, to which input port 221 of front-end circuitry 254 the pulse is destined, etc.) to be processed by pulse operations circuitry 358; each path a pulse may travel to the quantum processor 218 via frontend circuitry 254 may have particular characteristics (e.g., non-idealities of interconnect, mixers, switches, attenuators, amplifiers, and/or circuits along the paths) to be accounted for by the pulse modification operations; similarly, each quantum element 1220-122k may have a particular characteristics (e.g. resonance frequency, frame of reference, etc.); the routing circuitry 506 is operable to route modification settings from the modification settings circuits 5040 -504L-1 to the pulse operations circuit 358 and to the pulsers 3020-302L-1; the pulser 3021 may determine ops_slct1 based on the particular quantum element 122k and/or signal path to which the pulse is to be transmitted (e.g., the resonant frequency of the quantum element, frame of reference, and/or mixer correction); the determination of which quantum element and/or signal path to which a particular pulser 3021 is to send an outbound pulse at a particular time may be predetermined in the pulse generation program and quantum machine specification 206 or may be determined based on calculations performed by the pulser 3021 and/or others of the pulsers 3020-302L-1 during runtime; the digital signal IFI instructs the pulse operations manager 356 to update a frequency setting of the modification settings circuit 504k indicated by ops_slct1; ¶ [0094] with FIG. 9A: connected to the inputs and outputs of the quantum controller 210 may be a plurality of external devices (e.g., oscilloscopes, waveform generators, spectrum analyzers, mixers, amplifiers, etc.) and a plurality of quantum elements; ¶¶ [0105]-[0106] with FIG. 2A: an element that a quantum machine may contain is a mixer of front-end circuitry 254; to correct for mixer imbalances, the in-phase/quadrature (10) waveforms of the pulse can be multiplied by a 2x2 mixer correction matrix before being sent to the output ports; this mixer correction matrix, determined via a calibration routine, may be frequency dependent; thus, a mixer definition may include the mixer's name and a list of one or more frequencies and the correction matrix to be used at each frequency; in one example implementation, the correction matrix is loaded into corresponding pulse modification circuit during compilation; similarly, an element definition may include an intermediate frequency with which every pulse sent to the element is to be modulated; when generating local oscillators for quantum control, it is desirable to minimize phase noise at offset from the carrier frequency that are determined by typical quantum gate(s) times, and typical quantum element coherence times; e.g., for one quantum system with shorter gate time it may be desirable to minimize phase noise in the range of 10 MHz to 100 MHz, whereas for another quantum system with longer gate times, it may be desirable to minimize phase noise in the range of 100 Hz to 100 kHz; also, the tolerable amount of phase noise may depend on the quantum system being controlled and/or the quantum algorithm being performed; some systems and/or algorithms can tolerate higher phase noise' laboratories using these systems and/or running these algorithms could benefit from a lower-cost implementation of multi-tone generator 222; ¶ [0110] with FIG. 10: in the implementations of FIG. 10, the use of a single fundamental frequency, fi, which is then upconverted to the output frequencies using mixers, amplifiers, and bandpass filters provides positive phase correlation between the phase noises of the outputs; ¶¶ [0112]-[0141] with FIGS. 11A-D: a quantum control multi-tone generator in FIG. 11A including the OCXO 1000 and the circuit 1002 which outputs M multiples of the fi; each of the outputs of circuit 1002 is then input to circuitry comprising a PLL and DRO 1120 in a feedback arrangement to generate a signal 223; the DROs have the effect of lowering phase noise in the signals 223 at frequencies far from the carrier frequency; a quantum control multi-tone generator in FIG. 11B uses only a single DRO 1120 and PLL 1104; the outputs of circuit 1002 and the DRO 1120 feed a signal processing circuit 1122 which mixes the signals 11060-1106N-1 (N is an integer) to generate signals 2230-223M-1; which of the N+1 signals 11060-1106N-1 is selected as signal 1106q (q is an integer where 0≤q≤N-1) to be input to the PLL 1104 may be determined (e.g., preconfigured or controlled programmatically during operation via signal(s) 253, 255, 257, and/or 259) based on the desired frequencies of the signals 2230-223M; the number of signals 223 and/or the frequency spacing of the signals 223 may be determined based on the range of frequencies that the control circuitry 502 of quantum controller 210 is configured to generate; the circuit 1002 may comprise one or more frequency multiplier circuits 1052; each circuit 1150 comprises M, an integer, multiplier circuits 1052, each of which generates an output signal that is an integer multiple of its input signal (in addition to the frequency multiplication, each circuit 1052 may also perform filtering and/or other signal conditioning operations such as current and/or voltage amplification to make the output signal suitable for driving one or more of: another multiplication circuit 1052, a PLL such as 1104, mixer(s) of the circuit 1122, and/or one or more inputs of the circuit 224; the circuit 1122 may comprise one or more mixer circuits 1152; through setting (either at design time or in the field using jumpers, variable resistors, switches, etc.) the multiplication factors of each multiplier 1052, the number of circuits 1150, the number of circuits 1152, and/or the interconnection of the circuits 1150 and 1152, a wide range of frequencies and channel spacings can be achieved to support a wide range of quantum processors and a wide range of quantum controllers; e.g., the multipliers are configured and connected to achieve 24 output frequencies spaced at 4fi, as follows: (a) circuit 11500 outputs: (i) fi, which drives an output port of the multitone generator 222; (ii) 4fi, which drives the input of circuit 11501, and is the basis for the frequency spacing; and (iii) 10fi, which drives an output port of the multitone generator 222; (b) circuit 11501 outputs: (i) 4fi, which drives an input of each of circuits 11520 , 11521 , and 11522; (ii) 8fi, which drives an input of each of circuits 11520 , 11521 , and 11522; (iii) 12fi, which drives an input of each of circuits 11520 , 11521 , and 11522; and (iv) 16fi, which drives an input of circuit 11502; (c) circuit 11502 outputs: (i) 16fi, which drives an output port of the multitone generator 222; (ii) 32fi, which drives an input of circuit 11520; (iii) 48fi, which drives an input of circuit 11521; (iii) 64fi which drives an input of circuit 11522; and (iv) 80fi, which drives an output port of the multitone generator 222; (d)circuit 11520 receives 4fi, 8fi, 12fi, and 32fi and outputs 28fi, 36fi, 40fi, 24fi, 44fi, and 20fi; (e) circuit 11521 receives 4fi, 8fi, 12fi, and 48fi and outputs 52fi, 44fi, 56fi, 40fi, 60fi, and 36fi; and (f) circuit 11522 receives 4fi, 8fi, 12fi, and 64fi and outputs 68fi, 60fi, 72fi, 56fi, 76fi, and 52fi; the multi-tone generator is operable to generate a plurality of fixed-frequency signals from a single fixed-frequency reference signal (e.g., 2230 -2237), and output the plurality of fixed-frequency signals via a corresponding plurality of output ports (e.g., ports of 222); each of the plurality of fixed-frequency signals may be at a different one of a plurality of frequencies from a first frequency (e.g., 2.5 GHz) to a second frequency (e.g., 6 GHz); the frequency spacing between frequency-adjacent signals of the plurality of fixed-frequency signals may be less than or equal to a range of frequencies (e.g., a range of 500 MHz) at which the quantum control pulse generation circuitry is configured to generate a pulse signal (e.g., AO0) such that any frequency in the range from the first frequency to the second frequency for controlling quantum elements can be achieved through tuning of the pulse signal and mixing of the pulse signal with one of the plurality of fixed-frequency signals; the quantum control pulse generation circuit may be operable to generate baseband pulses, and upconvert the baseband pulses to an intermediate frequency to generate the quantum control pulses, wherein the intermediate frequency is tunable over a range at least as large as the first frequency spacing).
Independent Claim 10
Szmuk teaches a quantum computer (Szmuk, ¶¶ [0021]-[0024] with FIG. 1B: quantum computers operate by storing information in the form of quantum bits ("qubits") and processing those qubits via quantum gates; it is the job of the quantum controller to generate the precise series of external signals, usually pulses of electromagnetic waves and pulses of base band voltage, to perform the desired logic operations (and thus carry out the desired quantum algorithm; ¶ [0025] with FIG. 2A: a quantum orchestration platform (QOP) comprises a quantum programming subsystem 202, a quantum controller 210, front-end circuitry 254, multi-LO tone generator 222, connectivity circuitry 224, and a quantum processor 218), comprising:
a quantum bit array with multiple quantum bits (Szmuk, ¶ [0031] with 218, 226, and 228 in FIG. 2A: in general, the quantum processor 218 comprises K (an integer) quantum elements 122, which includes qubits (which could be of any type such as superconducting, spin qubits, ion trapped, etc.), and, where applicable, any other element( s) for processing quantum information, storing quantum information (e.g. storage resonator), and/or coupling outbound quantum control pulses from front-end circuitry 254 and inbound quantum control pulses to the front-end circuitry 254), a quantum bit selector that selects a quantum bit to be quantum manipulated from the quantum bit array and shifts the angular frequency, and a microwave pulse generator that has the same frequency as the selected quantum bit and outputs a microwave pulse with a set pulse width and pulse amplitude, wherein the microwave pulse generator comprises, a logic circuit that generates cosine and sine waves with set phase and frequency, multiplies them by pulses of the set pulse width and pulse amplitude, respectively, and outputs I modulation data and Q modulation data, respectively (Szmuk, ¶¶ [0026]-[0039] with FIGS. 2A-D: the quantum programming subsystem 202 comprises circuitry operable to generate a pulse generation program and quantum machine specification 206 which configures the quantum controller 210 and includes instructions the quantum controller 210 can execute to carry out the quantum algorithm (i.e., generate the necessary outbound quantum control pulse(s)) with little or no human intervention during runtime; the quantum programming subsystem 202 is coupled to the quantum controller 210 which comprises circuitry operable to load the machine code from the programming subsystem 202, and then execute the machine code to generate the necessary outbound quantum control pulse(s) that correspond to the desired operations to be performed on the quantum processor 218 (e.g., sent to qubit(s) for manipulating a state of the qubit(s) or to readout resonator(s) for reading the state of the qubit(s), etc.) and/or process inbound pulses returning from the quantum processor 218 via front-end circuitry 254; whether to transmit one or more outbound pulse and/or characteristics of one or more outbound pulse to be transmitted may be predetermined at design time and/or may be determined during runtime; the quantum controller 210 is coupled to front-end circuitry 254; the quantum controller 210 may comprise a plurality of interconnected, but physically separate quantum control modules 250; the number of quantum control modules 250 needed for a particular quantum system may be determined based on the number of qubits of the quantum processor 218 and their architecture (tunability, connectivity, coupling elements and readout architecture); port(s) 262 represent RF output ports via which pulses are sent to qubits of the quantum processor (in the example of FIG. 2A, 262 corresponds to 2251-2254); port(s) 264 represent RF output ports via which pulses are sent to readout elements of the quantum processor (in the example of FIG. 2A, 264 corresponds to 2250); port(s) 268 represent IF input ports via which pulses to be sent to qubits of the quantum processor 218 are received from a controller module 250 (in the example of FIG. 2A, 268 corresponds to one or more of 2211-2214); port(s) 270 represent IF input ports via which pulses to be sent to readout elements of the quantum processor 218 are received from a controller module 250 (in the example of FIG. 2A, 270 corresponds to 2210); the front-end circuitry 254 is operable to receive outbound intermediate frequency (IF) pulses from quantum controller 210 via one or more ports 221, upconvert the IF pulses to RF using the local oscillator signals received via one or more LO ports 229, and output the RF pulses to quantum processor 218 via one or more output ports 225; the number of front-end-circuitry modules needed for a particular quantum system may be determined based on the number of qubits of the quantum processor 218 and their architecture (tunability, connectivity, preparation, trapping, coupling elements and readout architecture); a signal 259 from the quantum programming subsystem 202 and/or a signal 257 from the quantum controller module 250 may open and close switching elements of the circuitry 254, adjust gains within the circuitry 254, adjust coefficients of filters within the circuitry 254, and/or otherwise configure the RF, IF, and/or LO signal paths of circuitry 254; the multi-tone generator 222 is operable to generate one or more signals at one or more desired frequencies, which will typically be dictated by the particular quantum processor 218 (e.g., based on the resonant frequencies of quantum elements of the quantum processor 218); two types of outputs are provided by quantum multi-tone generator 222: (a) one or more fixed frequency continuous wave (CW) tones 223; and (b) one or more synthesized frequency signals 231; allows splitting a tone 223 into up to six LO signals using a suitable power splitting circuit, without any additional active RF components; e.g., there are eight tones with f0=500 MHz and thus the tones 223 range from 2.5 GHz to 6 GHz in steps of 500 MHz; this, together with the ability of the quantum controller 210 to accurately and dynamically control the frequencies of IF pulses it generates (see e.g., FIGS. 6A and 6B, below), enables addressing qubits within a band of frequencies that covers all currently known and proposed superconducting qubit implementations; the synthesized signal or signals 231 output an adjustable frequency RF tone within a band of frequencies that contains, e.g., the band 4 GHz to 8 GHz; this, together with the ability of the quantum controller 210 to accurately and dynamically control the frequencies of IF pulses it generates (see e.g., FIGS. 6A and 6B, below), enables, for example, addressing various readout elements that use a wide range of frequencies; of course, different and/or other frequencies can be used to accommodate different qubit implementations; the connectivity circuitry 224 is operable to couple the outputs of the multi-tone generator 222 to the inputs of the front-end circuitry 254; because the desired connections between multi-tone generator 222 and quantum processor 218 depends on the architecture and operating frequencies of the quantum processor 218, the connectivity circuitry 224 is configurable by the user to support whatever configurations users may need for their particular quantum algorithms and particular quantum processor 218; the signal 253 from the quantum programming subsystem 202 and/or a signal 255 from the quantum controller module 250 may configure signal paths within circuitry 224 (e.g., by opening and closing switches, adjusting gains, adjusting filter coefficients, and/or the like); the reference generator circuit 219 provides a reference signal that the multi-tone generator 222 splits, frequency multiplies, amplifies and filters to generate signals 2230 -2237 and 231; in an example implementation, the low-phase-noise reference generator 219 is an oven-controlled crystal oscillator (OCXO) or other low-phase-noise reference generator 219; ¶¶ [0040]-[0054] with FIGS. 2A and 3: the quantum controller 210 comprises pulsers 3021 -302L-1, receive analog frontend 350, input manager 352, digital manager 354, pulse operations manager 356, pulse operations 358, output manager 360, transmit analog frontend 362, data exchange 364, synchronization manager 366, and input/output ("I/O") manager 368; the signal routing and multiplexing/demultiplexing functions performed by the input manager 352 enables: a particular pulser 302I to process different inbound pulses from different quantum elements at different times; a particular pulser 302I to process different inbound pulses from different quantum elements at the same time; and multiple of the pulsers 3020-302L-1 to processes the same inbound pulse at the same time; each pulser circuit 302I (I between 0 and L-1) comprises circuitry operable to generate outbound pulses according to quantum control operations to be performed on the quantum processor 218; this involves very precisely controlling characteristics such as phase, frequency, amplitude, and timing of the outbound pulses; the outbound pulses may be, e.g., control pulses sent to the quantum processor 218 to manipulate one or more properties of one or more quantum elements — e.g., manipulate a state of one or more qubits, manipulate a frequency of a qubit using flux biasing, etc., and/or readout a state of one or more quantum elements; the characteristics of an outbound pulse generated at any particular time may be determined, at least in part, on inbound pulses received from the quantum processor 218 via frontend circuitry 220 at a prior time; the time required to close the feedback loop (i.e., time from receiving a first pulse on an output 217 of front-end circuitry 254 to sending a second pulse (e.g., at an input 221 of front-end circuitry 254), where the second pulse is based on the first pulse, is significantly less than the coherence time of the qubits of the quantum processor 218; pulser 302I may process the inbound signal AII to determine the state of certain quantum element(s) in the quantum processor 218 and use this state information for making decisions such as, e.g., which raw outbound pulse CP'I to generate next, when to generate it, and what control signals to generate to affect the characteristics of that raw outbound pulse appropriately; the pulse operations circuitry 358 is operable to process the raw outbound pulses CP'0 -CP'L-1 to generate corresponding output outbound pulses CP0-CPL-1; this may comprise, e.g.,, manipulating the amplitude, phase, and/or frequency of the raw pulse CP'I; the output manager 360 enables: routing outbound pulses from a particular pulser 3021 to different ones input ports 221 at different times; routing outbound pulses from a particular pulser 3021 to multiple of the input ports 221 at the same time; and multiple of the pulsers 3020 -302L-1 generating pulses for the same input port 221 at the same time; at any given time, the output manager 360 is operable to concurrently route K of the digital signals CP0-CPL-1 as K independent outbound pulses, concurrently route K/2 of the digital signals CP0-CPL-1 as two-pulse pairs, or route some of signals CP0-CPL-1 as independent outbound pulses and some others of the signals CP0-CPL-1 as multi-pulse sets (at different times and/or concurrently); the digital manager 354 comprises circuitry operable to process and/or route digital control signals (DigCtrl0-DigCtrlJ-1) to various circuits of the quantum controller 210 and/or external circuits coupled to the quantum controller 210; each destination of the digital signals may require different operations to be performed on the digital signal (such as delay, broadening, or digital convolution with a given digital pattern); these operations may be performed by the digital manager 354 and may be specified by control signals from the pulsers 3020-302L-1; this allows each pulser 3021 to generate digital signals to different destinations and allows different ones of pulsers 3020-302L-1 to generate digital signals to the same destination while saving resources; the data exchange circuitry 364 is operable to manage exchange of data among the various circuits shown in FIG. 3; pulser 3021 may need to share, with pulser 3022, the characteristics of an inbound signal AI1 that it just processed so that pulser 3022 can generate a raw outbound pulse CP'2 based on the characteristics of AI1; ¶¶ [0055]-[0059] with FIG. 4: each pulse template stored in memory 404 comprises a sequence of one or more samples of any arbitrary shape (e.g., Gaussian, sine, impulse, etc.) representing the pulses to be sent to pulse operation circuitry 358; ¶¶ [0060]-[0071] with FIGS. 2A, 3 and 5: the pulse operations circuitry 358 comprises a plurality of pulse modification circuits 5080-508R-1 (R is an integer≥1 in general, and R=L/2 in the example shown); the pulse operations manager 356 comprises control circuitry 502, routing circuitry 506, and a plurality of modification settings circuits 5040-504K-1; assuming CP1 and CP2 are a phase-quadrature pulse pair to be output; in this example, pulse operations circuitry 358 may process CP1 and CP2 by multiplying a vector representation of CP'1 and CP'2 by one or more 2 by 2 matrices to: (a) perform single-sideband-modulation, where ω is the frequency of the single side band modulation and TS is the time passed since the reference time (e.g. the beginning of a certain control protocol); (b) keep track of frame-of-reference rotations, where ϕ is the total phase that the frame of reference accumulated since the reference time; and/or (c) perform an IQ-mixer correction where C00, C01, C10, and C11 are the elements of a matrix that corrects for IQ-mixer imperfections; each modification settings circuit, 504k, contains registers that contain the matrix elements of three matrices: an IQ-mixer correction matrix Ck; a single sideband frequency modulation matrix Sk; and a frame rotation matrix Fk, which rotates the IQ axes around the axis perpendicular to the IQ plane (i.e. the z-axis if I and Q are the x-axis and y-axis); each pulse modification circuit 508r is operable to process two raw outbound pulses CP'2r and CP'2r+1; such processing may comprise adjusting a phase, frequency, and/or amplitude of the raw outbound pulses CP'2r and CP'2r+1; pulse modification settings output to pulse operations circuitry 358 are specifically tailored to each raw outbound pulse (e.g., to which quantum element 226 or 228 the pulse is destined, to which input port 221 of front-end circuitry 254 the pulse is destined, etc.) to be processed by pulse operations circuitry 358; each path a pulse may travel to the quantum processor 218 via frontend circuitry 254 may have particular characteristics (e.g., non-idealities of interconnect, mixers, switches, attenuators, amplifiers, and/or circuits along the paths) to be accounted for by the pulse modification operations; similarly, each quantum element 1220-122k may have a particular characteristics (e.g. resonance frequency, frame of reference, etc.); the routing circuitry 506 is operable to route modification settings from the modification settings circuits 5040 -504L-1 to the pulse operations circuit 358 and to the pulsers 3020-302L-1; the pulser 3021 may determine ops_slct1 based on the particular quantum element 122k and/or signal path to which the pulse is to be transmitted (e.g., the resonant frequency of the quantum element, frame of reference, and/or mixer correction); the determination of which quantum element and/or signal path to which a particular pulser 3021 is to send an outbound pulse at a particular time may be predetermined in the pulse generation program and quantum machine specification 206 or may be determined based on calculations performed by the pulser 3021 and/or others of the pulsers 3020-302L-1 during runtime; the digital signal IFI instructs the pulse operations manager 356 to update a frequency setting of the modification settings circuit 504k indicated by ops_slct1; ¶¶ [0072]-[0079] with FIGS.3 and 6A-B: the frequency generation circuitry is part of control circuitry 502 of pulse operations manager circuitry 356; each CORDIC circuit 602k is operable to compute cosine and sine of its input, θk, thus generating two signals cos(θk) and sin(θk); the phase generation circuitry 604 is operable to generate the CORD IC input parameters θ0-θk-1 based on: (a) the frequency setting signals IF0-IFL-1 from the pulsers 3020-302L-1; and (b) the contents, TS, of the timestamp register 606; the timestamp register 606 comprises circuitry (e.g., a counter incremented on each cycle of the clock signal clk1) operable to track the number of cycles of clk1 since a reference point in time (e.g., power up of the quantum controller 210, start of execution of set of instructions of a pulse generation program by the quantum controller 210, etc.); the phase generation circuitry 604 sets θ0=2πf0(TS)(dtclk1), where f0 is a frequency determined from the signal IF0, TS is the number of clock cycles counted from the reference point and dtclk1 is the duration of a single clock cycle of clk1; this leads to the CORD IC outputs being a pair of phase-quadrature reference signals, cos(2πf0(TS)(dtclk1)) and sin(2πf0(TS)(dtclk1)), as in the example shown, which are used to generate the S0 rotation matrix that rotates at a frequency f0; as shown in FIG. 6B, the signal IFI may comprise an update component and an fI component; when updateI is asserted then the phase generation circuitry updates one of more of f0-fk-1 to be the value of fI; the S-matrix generation circuitry 608 is operable to build the matrices S0-SK-1 from the outputs of the CORDIC circuits 6020-602K-1; the S-matrix generation circuit 608 is operable to synchronize changes to the S matrices such that any matrix update occurs on a desired cycle of clock clk1 (which may be determined by the control information IF0-IFL- 1); in instances that more than K frequencies are needed over the course of a set of instructions, the phase generation circuit 604 is operable to change the input parameter θk of one or more of the CORDIC circuits 6020-602K-1 to stop generating one frequency and start generating the K+1th frequency; it may be necessary for the new frequency to start at a phase θ that would have been the phase if the new frequency was being generated from the initial reference time (e.g., because the new frequency would be used to address a quantum element that has a resonance at the new frequency and that was coherent since the reference point); in some other instances, it might be necessary to start the new frequency from the phase that the old frequency ended in; ¶ [0093]: patternz of signal Pz may be determined based on: the destination(s) of signal Pz; characteristics of the corresponding quantum control pulse (e.g., any one or more of its frequency, phase, amplitude, and/or duration); and/or process, temperature, and/or voltage variations; ¶¶ [0094]-[0106] with FIGS. 9A-B: FIG. 9A illustrates configuration and control of the quantum controller via the quantum programming subsystem; connected to the inputs and outputs of the quantum controller 210 may be a plurality of external devices (e.g., oscilloscopes, waveform generators, spectrum analyzers, mixers, amplifiers, etc.) and a plurality of quantum elements; the pulse generation program 904 comprises statements that define a sequence of operations to be performed by the quantum machine defined in the specification 902; such operations typically include the generation of one or more analog pulses to be sent to a controlled element, such as a quantum element; such operations typically include measuring one or more return pulses from an element; the pulse generation program is also referred to herein as a QUA program; defines the sequence of statements for: (a) generating, shaping and sending pulses to the quantum device; (b) measuring of pulses returning from the quantum device; (c) performing real-time classical calculations on the measured data and storing results in classical variables; (d) performing real-time classical calculations on classical variables; (e) controlling the flow of the program, including branching statements; and (6) streaming of data from the quantum controller 210 to the quantum programing system 202 and processing and saving it in the quantum programing system 202; a QUA program can define exactly the timing in which pulses are played, down to the single sample level and single clock cycles of the quantum controller 210; during compilation, pulse modification settings for manipulating pulses intended for an element may be generated (for loading into pulse modification settings circuits 504) and the pulse modification setting circuit(s) 504 to which they will be loaded before execution may be chosen and may be allocated to the quantum machine on which the program is to be executed; similarly, parameters and configurations of operations that will be performed on input signals related to an element (e.g. readout/measurement pulses) may be generated during compilation (for loading into compute and signal processing circuits 410); an element that a quantum machine may contain is a mixer of front-end circuitry 254; to correct for mixer imbalances, the in-phase/quadrature (10) waveforms of the pulse can be multiplied by a 2x2 mixer correction matrix before being sent to the output ports; this mixer correction matrix, determined via a calibration routine, may be frequency dependent; thus, a mixer definition may include the mixer's name and a list of one or more frequencies and the correction matrix to be used at each frequency; in one example implementation, the correction matrix is loaded into corresponding pulse modification circuit during compilation; similarly, an element definition may include an intermediate frequency with which every pulse sent to the element is to be modulated; when generating local oscillators for quantum control, it is desirable to minimize phase noise at offset from the carrier frequency that are determined by typical quantum gate(s) times, and typical quantum element coherence times; e.g., for one quantum system with shorter gate time it may be desirable to minimize phase noise in the range of 10 MHz to 100 MHz, whereas for another quantum system with longer gate times, it may be desirable to minimize phase noise in the range of 100 Hz to 100 kHz; also, the tolerable amount of phase noise may depend on the quantum system being controlled and/or the quantum algorithm being performed; some systems and/or algorithms can tolerate higher phase noise' laboratories using these systems and/or running these algorithms could benefit from a lower-cost implementation of multi-tone generator 222), a DAC that converts the I modulation data and Q modulation data from digital data to analog and outputs I modulation signal and Q modulation signal (Szmuk, ¶ [0049] with FIGS. 2A and 3: the transmit analog frontend 362 comprises circuitry operable to concurrently process up to K digital signals DOk to generate up to K concurrent analog signals AOk to be output to inputs 221 of the front-end circuitry 254; such processing may comprise, e.g., digital-to analog conversion, filtering, upconversion, downconversion, amplification, attenuation, time division multiplexing/demultiplexing, frequency division multiplexing/demultiplexing and/or the like; the transmit analog frontend 362 is operable to process digital signals DO0-DOK-1 as K independent outbound pulses, as K/2 two-pulse pairs, or process some of signals DO0-DOK-1 as independent outbound pulses and some signals DO0-DOK-1 as two-pulse pairs (at different times and/or concurrently)), a frequency generator that generates LO output sine waves and LO output cosine waves with a phase difference of 90° from each other with the frequency set by the frequency setting signal, an IQ modulator that multiplies the I modulation signal and the Q modulation signal with the LO output sine wave and the LO output cosine wave, respectively, and outputs a phase modulated microwave pulse (Szmuk, ¶¶ [0032]-[0039] with FIG. 2A-D: the front-end circuitry 254 is operable to receive outbound intermediate frequency (IF) pulses from quantum controller 210 via one or more ports 221, upconvert the IF pulses to RF using the local oscillator signals received via one or more LO ports 229, and output the RF pulses to quantum processor 218 via one or more output ports 225; each IF input port 221 is configured to receive an independent pulse or multi-pulse pair (e.g., an IQ pair of pulses comprising an in-phase pulse and quadrature-phase pulse); in the latter case, the front-end circuitry 254 is operable to perform IQ upconversion; in FIG. 2D, the circuitry 254 comprises 6 IQ mixers 270; each of mixers 2700-2704 receives an IQ pair of IF signals via a respective one of ports 2210-2214, and uses an LO signal received via a respective one of ports 2290-2294 to upconvert the IQ pair to a corresponding RF signal output via a respective one of ports 2250 -2254; the multi-tone generator 222 is operable to generate one or more signals at one or more desired frequencies, which will typically be dictated by the particular quantum processor 218 (e.g., based on the resonant frequencies of quantum elements of the quantum processor 218); two types of outputs are provided by quantum multi-tone generator 222: (a) one or more fixed frequency continuous wave (CW) tones 223; and (b) one or more synthesized frequency signals 231; the connectivity circuitry 224 is operable to couple the outputs of the multi-tone generator 222 to the inputs of the front-end circuitry 254; the connectivity circuitry 224 can connect any one or more of the signals 2230 -2237 and 231 to any one or more of the input ports 2290 -2295 of front-end circuitry 254; ¶ [0062] with FIGS. 3 and 5: two of the pulsers 3020 -302L-1 may generate two raw outbound pulses which are a phase-quadrature pulse pair; assuming CP1 and CP2 are a phase-quadrature pulse pair to be output; in this example, pulse operations circuitry 358 may process CP1 and CP2 by multiplying a vector representation of CP'1 and CP'2 by one or more 2 by 2 matrices to: (a) perform single-sideband-modulation, where ω is the frequency of the single side band modulation and TS is the time passed since the reference time (e.g. the beginning of a certain control protocol); (b) keep track of frame-of-reference rotations, where ϕ is the total phase that the frame of reference accumulated since the reference time; and/or (c) perform an IQ-mixer correction where C00, C01, C10, and C11 are the elements of a matrix that corrects for IQ-mixer imperfections; ¶ [0076] with FIG. 6A: the phase generation circuitry 604 sets θ0=2πf0(TS)(dtclk1), where f0 is a frequency determined from the signal IF0, TS is the number of clock cycles counted from the reference point and dtclk1 is the duration of a single clock cycle of clk1; this leads to the CORD IC outputs being a pair of phase-quadrature reference signals, cos(2πf0(TS)(dtclk1)) and sin(2πf0(TS)(dtclk1)), as in the example shown, which are used to generate the S0 rotation matrix that rotates at a frequency f0; ¶ [0105] with FIG. 2A: an element that a quantum machine may contain is a mixer of front-end circuitry 254; to correct for mixer imbalances, the in-phase/quadrature (10) waveforms of the pulse can be multiplied by a 2x2 mixer correction matrix before being sent to the output ports; this mixer correction matrix, determined via a calibration routine, may be frequency dependent; thus, a mixer definition may include the mixer's name and a list of one or more frequencies and the correction matrix to be used at each frequency; in one example implementation, the correction matrix is loaded into corresponding pulse modification circuit during compilation; similarly, an element definition may include an intermediate frequency with which every pulse sent to the element is to be modulated), and a frequency divider that (Szmuk, ¶ [0050] with FIGS. 2A and 3: the output manager 360 comprises circuitry operable to route any one or more of signals CP0-CPL-1 to any one or more input ports 221 of the front-end circuitry 254; the output manager 360 comprises one or more switch networks, multiplexers, and/or the like for dynamically reconfiguring which one or more signals CP0-CPL-1 are routed to which input port(s) 221 of the front-end 220; this may enable time division multiplexing multiple of the signals CP0-CPL-1 onto a single input port 221 of the front-end circuit 220 and/or time division demultiplexing components (e.g., time slices) of a signal CP m onto multiple of the input ports 221 of the front-end circuitry 254; the output manager 360 comprises one or more mixers and/or filters for frequency division multiplexing multiple of the signals CP0-CPM-1 onto a single input port 221 of front-end circuitry 254 and/or frequency division demultiplexing components (e.g., frequency bands) of a signal CPm onto multiple of the input ports 221 of the front-end circuitry 254; ¶¶ [0034] and [0038] with FIG. 2A: allows splitting a tone 223 into up to six LO signals using a suitable power splitting circuit, without any additional active RF components; the reference generator circuit 219 provides a reference signal that the multi-tone generator 222 splits, frequency multiplies, amplifies and filters to generate signals 2230 -2237 and 231; ¶¶ [0075]-[0078]: the timestamp register 606 comprises circuitry (e.g., a counter incremented on each cycle of the clock signal clk1) operable to track the number of cycles of clk1 since a reference point in time (e.g., power up of the quantum controller 210, start of execution of set of instructions of a pulse generation program by the quantum controller 210, etc.); a desired cycle of clock clk1 (which may be determined by the control information IF0-IFL- 1); ¶ [0107] with FIG. 10: the signal processing circuitry is operable to perform splitting, frequency multiplication, gain adjustment, filtering, and/or other signal processing operations to generate M+1 local oscillator signals 1003 from the OCXO output 1001), wherein the frequency generator operates at the same frequency as the quantum bit other than the selected quantum bit except when the microwave pulse is output (Szmuk, ¶¶ [0033]-[0037] and [0042]-[0050] with FIGS. 2A and 3: the multi-tone generator 222 is operable to generate one or more signals at one or more desired frequencies, which will typically be dictated by the particular quantum processor 218 (e.g., based on the resonant frequencies of quantum elements of the quantum processor 218); two types of outputs are provided by quantum multi-tone generator 222: (a) one or more fixed frequency continuous wave (CW) tones 223; and (b) one or more synthesized frequency signals 231; together with the ability of the quantum controller 210 to accurately and dynamically control the frequencies of IF pulses it generates (see e.g., FIGS. 6A and 6B, below), enables addressing qubits within a band of frequencies that covers all currently known and proposed superconducting qubit implementations; together with the ability of the quantum controller 210 to accurately and dynamically control the frequencies of IF pulses it generates (see e.g., FIGS. 6A and 6B, below), enables, for example, addressing various readout elements that use a wide range of frequencies; because the desired connections between multi-tone generator 222 and quantum processor 218 depends on the architecture and operating frequencies of the quantum processor 218, the connectivity circuitry 224 is configurable by the user to support whatever configurations users may need for their particular quantum algorithms and particular quantum processor 218; the signal routing and multiplexing/demultiplexing functions performed by the input manager 352 enables: a particular pulser 302I to process different inbound pulses from different quantum elements at different times; a particular pulser 302I to process different inbound pulses from different quantum elements at the same time; and multiple of the pulsers 3020-302L-1 to processes the same inbound pulse at the same time; each pulser circuit 302I (I between 0 and L-1) comprises circuitry operable to generate outbound pulses according to quantum control operations to be performed on the quantum processor 218; this involves very precisely controlling characteristics such as phase, frequency, amplitude, and timing of the outbound pulses; the outbound pulses may be, e.g., control pulses sent to the quantum processor 218 to manipulate one or more properties of one or more quantum elements — e.g., manipulate a state of one or more qubits, manipulate a frequency of a qubit using flux biasing, etc., and/or readout a state of one or more quantum elements; the characteristics of an outbound pulse generated at any particular time may be determined, at least in part, on inbound pulses received from the quantum processor 218 via frontend circuitry 220 at a prior time; ¶¶ [0107]-[0111] with FIGS. 2A and 10: a quantum control multi-tone generator (e.g., multi-tone generator 222) comprising oven-controlled crystal oscillator (OCXO) and signal processing circuitry 1002; the signal processing circuitry is operable to perform splitting, frequency multiplication, gain adjustment, filtering, and/or other signal processing operations to generate M+1 local oscillator signals 1003 from the OCXO output 1001; the signal 1001 is at frequency fi, ID is a multiple of fi, each of the signals 223 is at a multiple of ID, and each of k and M are integers; the use of multiple fixed-frequency tones, avoids the need for the voltage controlled oscillators and phase locked loops used in the signal generators conventionally used for driving quantum systems, which has the benefit of greatly reducing phase noise in the circuitry 222 (in general VCOs introduce additional phase noise as compared to OCXOs); the quantum control multi-tone generator 222 also comprises a variable frequency signal generator 1004 operable to output a signal 231 having a variable (i.e., tunable) frequency; the variable frequency generator 1004 may be driven by the same reference signal that is input to the OCXO 1000 (e.g., a 10 MHz signal) and/or may be driven by the signal 1001 output by OXCO 1000 (e.g., a 1000 MHz signal); the use of a single fundamental frequency, fi, which is then upconverted to the output frequencies using mixers, amplifiers, and bandpass filters provides positive phase correlation between the phase noises of the outputs; this generation of coherent tones through multiplication and filtering of a common reference signal may increase quantum gate fidelity in scenarios where multiple sequential single-gate operations are applied to qubits that are operating using different frequency tones, as well as two-qubit gate operations; the signal processing circuit 1002 performs fanout, frequency multiplication, amplification, and filtration functions; ¶¶ [0112]-[0141] with FIGS. 11A-D: a quantum control multi-tone generator in FIG. 11A including the OCXO 1000 and the circuit 1002 which outputs M multiples of the fi; each of the outputs of circuit 1002 is then input to circuitry comprising a PLL and DRO 1120 in a feedback arrangement to generate a signal 223; the DROs have the effect of lowering phase noise in the signals 223 at frequencies far from the carrier frequency; a quantum control multi-tone generator in FIG. 11B uses only a single DRO 1120 and PLL 1104; the outputs of circuit 1002 and the DRO 1120 feed a signal processing circuit 1122 which mixes the signals 11060-1106N-1 (N is an integer) to generate signals 2230-223M-1; which of the N+1 signals 11060-1106N-1 is selected as signal 1106q (q is an integer where 0≤q≤N-1) to be input to the PLL 1104 may be determined (e.g., preconfigured or controlled programmatically during operation via signal(s) 253, 255, 257, and/or 259) based on the desired frequencies of the signals 2230-223M; the number of signals 223 and/or the frequency spacing of the signals 223 may be determined based on the range of frequencies that the control circuitry 502 of quantum controller 210 is configured to generate; the circuit 1002 may comprise one or more frequency multiplier circuits 1052; each circuit 1150 comprises M, an integer, multiplier circuits 1052, each of which generates an output signal that is an integer multiple of its input signal (in addition to the frequency multiplication, each circuit 1052 may also perform filtering and/or other signal conditioning operations such as current and/or voltage amplification to make the output signal suitable for driving one or more of: another multiplication circuit 1052, a PLL such as 1104, mixer(s) of the circuit 1122, and/or one or more inputs of the circuit 224; the circuit 1122 may comprise one or more mixer circuits 1152; through setting (either at design time or in the field using jumpers, variable resistors, switches, etc.) the multiplication factors of each multiplier 1052, the number of circuits 1150, the number of circuits 1152, and/or the interconnection of the circuits 1150 and 1152, a wide range of frequencies and channel spacings can be achieved to support a wide range of quantum processors and a wide range of quantum controllers; e.g., the multipliers are configured and connected to achieve 24 output frequencies spaced at 4fi, as follows: (a) circuit 11500 outputs: (i) fi, which drives an output port of the multitone generator 222; (ii) 4fi, which drives the input of circuit 11501, and is the basis for the frequency spacing; and (iii) 10fi, which drives an output port of the multitone generator 222; (b) circuit 11501 outputs: (i) 4fi, which drives an input of each of circuits 11520 , 11521 , and 11522; (ii) 8fi, which drives an input of each of circuits 11520 , 11521 , and 11522; (iii) 12fi, which drives an input of each of circuits 11520 , 11521 , and 11522; and (iv) 16fi, which drives an input of circuit 11502; (c) circuit 11502 outputs: (i) 16fi, which drives an output port of the multitone generator 222; (ii) 32fi, which drives an input of circuit 11520; (iii) 48fi, which drives an input of circuit 11521; (iii) 64fi which drives an input of circuit 11522; and (iv) 80fi, which drives an output port of the multitone generator 222; (d)circuit 11520 receives 4fi, 8fi, 12fi, and 32fi and outputs 28fi, 36fi, 40fi, 24fi, 44fi, and 20fi; (e) circuit 11521 receives 4fi, 8fi, 12fi, and 48fi and outputs 52fi, 44fi, 56fi, 40fi, 60fi, and 36fi; and (f) circuit 11522 receives 4fi, 8fi, 12fi, and 64fi and outputs 68fi, 60fi, 72fi, 56fi, 76fi, and 52fi; the multi-tone generator is operable to generate a plurality of fixed-frequency signals from a single fixed-frequency reference signal (e.g., 2230 -2237), and output the plurality of fixed-frequency signals via a corresponding plurality of output ports (e.g., ports of 222); each of the plurality of fixed-frequency signals may be at a different one of a plurality of frequencies from a first frequency (e.g., 2.5 GHz) to a second frequency (e.g., 6 GHz); the frequency spacing between frequency-adjacent signals of the plurality of fixed-frequency signals may be less than or equal to a range of frequencies (e.g., a range of 500 MHz) at which the quantum control pulse generation circuitry is configured to generate a pulse signal (e.g., AO0) such that any frequency in the range from the first frequency to the second frequency for controlling quantum elements can be achieved through tuning of the pulse signal and mixing of the pulse signal with one of the plurality of fixed-frequency signals; the quantum control pulse generation circuit may be operable to generate baseband pulses, and upconvert the baseband pulses to an intermediate frequency to generate the quantum control pulses, wherein the intermediate frequency is tunable over a range at least as large as the first frequency spacing), and the logic circuit operates in synchronization with the system clock (Szmuk, ¶ [0052] with FIG. 3: the synchronization manager 366 comprises circuitry operable to manage synchronization of the various circuits shown in FIG. 3; such synchronization is advantageous in a modular and dynamic system, such as quantum controller 210, where different ones of pulsers 3020-302L-1 generate, receive, and process pulses to and from different quantum elements at different times; e.g., a pulse generation program may require that a first pulser circuit 3021 and a second pulser circuit 3022 sometimes need to transmit pulses at precisely the same time, and at other times transmit pulses independently of one another; the synchronization manager 366 reduces the overhead involved in performing such synchronization; ¶ [0078] with FIGS. 6A-B: the S-matrix generation circuit 608 is operable to synchronize changes to the S matrices such that any matrix update occurs on a desired cycle of clock clk1 (which may be determined by the control information IF0-IFL- 1); ¶ [0086] with FIGS. 3 and 7: each of the controlled circuits 7100-710J-1 and input manager 372 is a circuit which, at least some of the time, needs to operate synchronously with quantum control pulses generated by one or more of pulsers 3020-302L-1 (possibly a reflection/return pulse from a quantum processor in the case of input manager 372); accordingly, each of the control circuits 7100-710J-1 receives a respective one of control signals DigOut0-DigCtrlJ-1 that is synchronized with a respective quantum control pulse).
Szmuk fails to explicitly disclose a frequency divider that outputs a system clock divided by the frequency of the wave.
Negoro teaches a system and a method relating to a quantum computer controller (Negoro, ¶ [0001]), wherein a frequency divider that outputs a system clock divided by the frequency of the wave (Negoro, ¶¶ [0027]-[0032] with FIG. 2: the quantum computer 100 includes a controller 110 and a qubit system 120 having a plurality of qubits; the controller 110 includes a server 130, a plurality of signal processing units 140-1, a clock distribution unit 150, and a master 160; upon receipt of an instruction input from a user, the server 130 calculates a waveform signal required for state manipulation of the qubits of the qubit system 120 or for readout from the qubit system 120, and outputs the waveform signal to each of the signal processing units 140-1; the clock distribution unit 150 distributes a common clock to the signal processing units 140-I; the master 160 distributes a common time to the signal processing units 140-i in accordance with a time synchronization protocol; each of the signal processing units 140-i is designed by integrating the functions of the baseband circuits 40, the oscillation circuit 50, and the analog circuit 60 of the conventional quantum computer shown in FIG. 1 into a single unit, and generates, based on the waveform signal calculated by the server 130, a microwave signal (electromagnetic wave signal) with which the qubit system 120 is irradiated; ¶¶ [0055]-[0063] with FIG. 3: the dividers 372 are respectively provided at the output stages of the filter/multiplier units 370; the microwave signal from the filter/multiplier unit 370 is divided into two signals (a first microwave signal OUT1 and a second microwave signal OUT2) by the divider 372; the first microwave signal OUT1 is emitted onto the qubits of the qubit system 120 through a cable, and the second microwave signal OUT2 is output to the feedback circuit 380; some of the plurality of first microwave signals OUT1 are control signals for manipulating the states of the qubits, and the remaining first microwave signals OUT1 include a read pulse for reading the qubits and a pump pulse for amplifying the read signal; when the second microwave signal OUT2 is selected, the second microwave signal OUT2 is used for correcting the baseband signal as described below; on the other hand, when the external signal EXT from the other signal processing unit 140-j is selected, the external signal EXT is used for monitoring synchronization between different signal processing units 140-i and 140-j (i≠j); when the monitor signal corresponds to the second microwave signal OUT2, the receiving logic 318 calculates a difference between the monitor signal and the baseband signal output from the transmitting logic 316, and sets a correction parameter for eliminating the difference, as a parameter 316a for the transmitting logic 316; the transmitting logic 316 corrects, in accordance with the parameter 316a, the baseband signal generated from the waveform signal held in the HBM 314, and outputs the corrected baseband signal; with the automatic calibration based on the monitor signal as described above, it is possible to improve usability, and achieve high performance and high stability; when the monitor signal corresponds to the external signal EXT input from the other signal processing unit 140-j to the signal processing unit 140-i (i≠j), the receiving logic 318 of the signal processing unit 140-i compares the monitor signal with a reference signal to analyze the synchronization between the different signal processing units 140-i and 140-j, and writes the analysis result into the HBM 314; ¶¶ [0066]-[0069] with FIGS. 3, 5, and 7B: the clock distribution unit 150 includes a clock generation source 510, a first clock generator 521, a second clock generator 522, and a third clock generator 523; the clock generation source 510 generates a clock with a given frequency (e.g., 10 MHz); the clock generated by the clock generation source 510 is distributed into the first clock generator 521, the second clock generator 522, and the third clock generator 523; each of the first clock generator 521, the second clock generator 522, and the third clock generator 523 includes a phase-locked loop (PLL), a frequency divider circuit, and the like; the first clock generator 521, the second clock generator 522, and the third clock generator 523 generate a first clock, a second clock, and a third clock, respectively, having different frequencies from one another; the first clock, the second clock, and the third clock are distributed to all the signal processing units 140-1, 140-2, …, and 140-N, through signal lines 531, 532, and 533, respectively; the first clock is a system operation clock with a first frequency (e.g., 125 MHz); the second clock is a clock with a second frequency (e.g., 62.5 kHz) having a longer period than the first clock, and is used for synchronization in different channels between the logic device 310 and the DAC/ADC module 330 (see FIG. 7B); the third clock is a reference clock with a third frequency (e.g., 100 MHz), on which the oscillation signals of the oscillators (NCOs, LO) are based; the logic device 310 of each of the signal processing units 140-i generates, from the first clock, an operation clock with a higher frequency than the first clock).
Szmuk and Negoro are analogous art because they are from the same field of endeavor, a system and a method relating to a quantum computer controller. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to apply the teaching of Negoro to Szmuk. Motivation for doing so would provide better synchronization (Negoro, ¶¶ [0013], [0062], [0068]-[0069], [0071]-[0075], and [088]).
Claim 11
Szmuk in view of Negoro discloses all the elements as stated in Claim 10 and further discloses an IQ demodulator that multiplies the microwave pulse with the LO output sine wave and the LO output cosine wave and demodulates it into I demodulation signal and Q demodulation signal (Szmuk, ¶¶ [0031]-[0037] with FIGS. 2A-D: port(s) 266 represent RF input ports via which pulses are received from the readout elements of the quantum processor (in the example of FIG. 2A, 266 corresponds to 227); port(s) 272 represent IF output ports via which pulses from readout elements are sent to controller module 250 (in the example of FIG. 2A, 272 corresponds to 217 in FIG.2B/223 in FIG. 2D); each IF input port 221 is configured to receive an independent pulse or multi-pulse pair (e.g., an IQ pair of pulses comprising an in-phase pulse and quadrature-phase pulse); in the latter case, the front-end circuitry 254 is operable to perform IQ upconversion; the mixer 2705 uses the LO received via port 2295 to downconvert the RF signal received via port 227 to generate the IF IQ pair output via port 217 in FIG. 2B/223 in FIG. 2D; in each of examples 1, 2, and 3, the 4-8 GHz synthesized signal may be used for upconversion of the readout element control signal that is output via port 2250 , and for downconversion of the readout element return signal received via port 227; ¶¶ [0040]-[0054] with FIG. 3: pulser 302l may process the inbound signal AIl to determine the state of certain quantum element(s) in the quantum processor 218 and use this state information for making decisions such as, for example, which raw outbound pulse CP'l to generate next, when to generate it, and what control signals to generate to affect the characteristics of that raw outbound pulse appropriately; pulser 302l may use the signal f_dmodl for determining how to process inbound pulse signal Ali; as an example, when pulser 302l needs to process an inbound signal AIl from quantum element 1223, it can send a dmod_scltl signal that directs pulse operations manager 356 to send, on f_dmodl, settings to be used for demodulation of an inbound signal AI3 ( e.g., the pulse operations manager 356 may send the value cos( ω3*TS*Tclk1 +ϕ3 ), where ω3 is the frequency of quantum element 1223, TS is amount of time passed since the reference point, for instance the time at which a pulse program started running, and ϕ3 is the phase of the total frame rotation of quantum element 1223 , i.e. the accumulated phase of all frame rotations since the reference point); ¶¶ [0055]-[0059] with FIG. 4: the compute and/or signal processing circuitry (CSP) 410 is operable to perform computational and/or signal processing functions, which may comprise, for example Boolean-algebra based logic and arithmetic functions and demodulation (e.g., of inbound signals AI1); the CSP 410 may comprise memory in which are stored instructions for performing the functions and demodulation; the instructions may be specific to a particular pulse generation program and be generated during compilation of the program; ¶¶ [0060]-[0071] with IFG. 5: two of the pulsers 3020-302L-1 may generate two raw outbound pulses which are a phase-quadrature pulse pair; assuming CP1 and CP2 are a phase-quadrature pulse pair to be output; in this example, pulse operations circuitry 358 may process CP1 and CP2 by multiplying a vector representation of CP'1 and CP'2 by one or more 2 by 2 matrices to: (a) perform single-sideband-modulation, where ω is the frequency of the single side band modulation and TS is the time passed since the reference time (e.g. the beginning of a certain control protocol); (b) keep track of frame-of-reference rotations, where ϕ is the total phase that the frame of reference accumulated since the reference time; and/or (c) perform an IQ-mixer correction where C00, C01, C10, and C11 are the elements of a matrix that corrects for IQ-mixer imperfections; each modification settings circuit, 504k, contains registers that contain the matrix elements of three matrices: an IQ-mixer correction matrix Ck; a single sideband frequency modulation matrix Sk; and a frame rotation matrix Fk, which rotates the IQ axes around the axis perpendicular to the IQ plane (i.e. the z-axis if I and Q are the x-axis and y-axis); each pulse modification circuit 508r is operable to process two raw outbound pulses CP'2r and CP'2r+1; such processing may comprise adjusting a phase, frequency, and/or amplitude of the raw outbound pulses CP'2r and CP'2r+1; the control circuitry 502 is operable to exchange information with the puller circuits 3020-302L-1 to generate values of ops_confg0-ops_confgL-1 and f_demod0 -f_demodmL-1 , to control routing circuitry 506 based on signals ops_slct0-ops_slctL-l and dmod_slct0-dmod_slctL-1, and to update pulse modification settings 5040-504K-1 based on IF0-IFL-1 and F0-FL-1 such that pulse modification settings output to pulse operations circuitry 358 are specifically tailored to each raw outbound pulse (e.g., to which quantum element 226 or 228 the pulse is destined, to which input port 221 of front-end circuitry 254 the pulse is destined, etc.) to be processed by pulse operations circuitry 358; each path a pulse may travel to the quantum processor 218 via frontend circuitry 254 may have particular characteristics (e.g., non-idealities of interconnect, mixers, switches, attenuators, amplifiers, and/or circuits along the paths) to be accounted for by the pulse modification operations; similarly, each quantum element 1220-122k may have a particular characteristics (e.g. resonance frequency, frame of reference, etc.); when pulse generation circuit 302l needs to demodulate a pulse signal AIl from quantum element 122k, it will send a dmod_scltl signal instructing the pulse operation manager 356 to rout the element SFk00=cos(ωk*time_stamp+ϕk) from modification settings circuit 504k to pulser 3021 (as f_dmodl); ¶¶ [0072]-[0079] with FIGS.3 and 6A-B: each CORDIC circuit 602k is operable to compute cosine and sine of its input, θk, thus generating two signals cos(θk) and sin(θk); the phase generation circuitry 604 is operable to generate the CORD IC input parameters θ0-θk-1 based on: (a) the frequency setting signals IF0-IFL-1 from the pulsers 3020-302L-1; and (b) the contents, TS, of the timestamp register 606; the timestamp register 606 comprises circuitry (e.g., a counter incremented on each cycle of the clock signal clk1) operable to track the number of cycles of clk1 since a reference point in time (e.g., power up of the quantum controller 210, start of execution of set of instructions of a pulse generation program by the quantum controller 210, etc.); the phase generation circuitry 604 sets θ0=2πf0(TS)(dtclk1), where f0 is a frequency determined from the signal IF0, TS is the number of clock cycles counted from the reference point and dtclk1 is the duration of a single clock cycle of clk1; this leads to the CORD IC outputs being a pair of phase-quadrature reference signals, cos(2πf0(TS)(dtclk1)) and sin(2πf0(TS)(dtclk1)), as in the example shown, which are used to generate the S0 rotation matrix that rotates at a frequency f0; as shown in FIG. 6B, the signal IFI may comprise an update component and an fI component; when updateI is asserted then the phase generation circuitry updates one of more of f0-fk-1 to be the value of fI; the S-matrix generation circuitry 608 is operable to build the matrices S0-SK-1 from the outputs of the CORDIC circuits 6020-602K-1; the S-matrix generation circuit 608 is operable to synchronize changes to the S matrices such that any matrix update occurs on a desired cycle of clock clk1 (which may be determined by the control information IF0-IFL- 1); in instances that more than K frequencies are needed over the course of a set of instructions, the phase generation circuit 604 is operable to change the input parameter θk of one or more of the CORDIC circuits 6020-602K-1 to stop generating one frequency and start generating the K+1th frequency; it may be necessary for the new frequency to start at a phase θ that would have been the phase if the new frequency was being generated from the initial reference time (e.g., because the new frequency would be used to address a quantum element that has a resonance at the new frequency and that was coherent since the reference point); in some other instances, it might be necessary to start the new frequency from the phase that the old frequency ended in;¶ [0140]: the quantum control interconnect circuitry may comprises a third mixer (e.g., 270s) configured to downconvert the return pulses using the variable-frequency reference signal received. The quantum control interconnect circuitry may comprise a third output ( e.g., 223) configured to convey downconverted return pulses from the third mixer to the quantum control pulse generation circuitry ), an ADC that converts the I demodulation signal and the Q demodulation signal from analog to digital data and outputs I demodulation data and Q demodulation data (Szmuk, ¶¶ [0041]-[0042] with FIGS. 2A and 3: the receive analog frontend 350 comprises circuitry operable to concurrently process up to M (an integer≥1) analog inbound signals (RP'0-RP'M-1) from one or more outputs of front end circuitry 220 to generate up to M concurrent inbound signals (RP0-RPM-1) to be output to input manager 352 via one or more signal paths; such processing may comprise, e.g., analog-to-digital conversion, filtering, upconversion, downconversion, amplification, attenuation, time division multiplexing/demultiplexing, frequency division multiplexing/demultiplexing, and/or the like; the input manager 352 comprises circuitry operable to route any one or more of signals (RP0-RPM-1) to any one or more of pulsers 3020-302L-1 (as signal(s) AI0-AIL-1) and/or to other circuits (e.g. as signal io_mgr to I/O manager 368); the input manager 352 comprises one or more switch networks, multiplexers, and/or the like for dynamically reconfiguring which signals RP0-RPM-1 are routed to which pulsers 3020-302L-1; this may enable time division multiplexing multiple of the signals RP0-RPM-1 onto a single signal Ali and/or time division demultiplexing components (e.g., time slices) of a signal RPm onto multiple of the signals AI0-AIL-1; input manager 352 comprises one or more mixers and/or filters for frequency division multiplexing multiple of the signals RP0-RPM-1 onto a single signal Ali and/or frequency division demultiplexing components (e.g., frequency bands) of a signal RP m onto mu!- tiple of the signals AI0-AIL-1), and
a calibration circuit that acquires the I demodulation data and Q demodulation data, calculates the IQ gain error and phase error, and outputs the IQ correction data to the logic circuit, wherein the logic circuit corrects the cosine and sine waves using the IQ correction data (Szmuk, ¶¶ [0062]-[0071] with FIGS. 3 and 5: perform an IQ-mixer correction, where C00, C01 , C10, and C11 are the elements of a matrix that corrects for IQ-mixer imperfections; the digital signal IFl instructs the pulse operations manager 356 to update a frequency setting of the modification settings circuit 504k indicated by ops_slctl; the frequency setting is the matrix Sk (described above) and the signal IFl carries new values indicating the new ωk to be used in the elements of the matrix Sk; the new values may, e.g., be determined during a calibration routine (e.g., performed as an initial portion of the pulse generation program) in which one or more of the pulsers 3020-302L-1 sends a series of outbound pulses CP, each at a different carrier frequency, and then measures the corresponding inbound signals AI; each signal Ck may comprise a matrix to be multiplied by a matrix representation of a raw outbound pulse CP'l such that the resulting output outbound pulse is pre-compensated for errors (e.g., resulting from imperfections in mixers, amplifiers, wiring, etc.) introduced as the outbound pulse propagates along the signal path; the result of the pre-compensation is that output outbound pulse CPl will have the propercharacteristics upon arriving at the quantum processor 218; the signals C0-CK-1 may, e.g., be calculated by the quantum controller 210 itself, by the programming subsystem 202, and/or by external calibration equipment and provided via I/O manager 368; the calculation of signals may be done as part of a calibration routine which may be performed before execution of a pulse generation program and/or may be determined/adapted in real-time as part of a pulse generation program (e.g., to compensate for temperature changes during runtime of the pulse generation program); ¶ [0105] with FIG. 2A: an element that a quantum machine may contain is a mixer of front-end circuitry 254; to correct for mixer imbalances, the in-phase/quadrature (10) waveforms of the pulse can be multiplied by a 2x2 mixer correction matrix before being sent to the output ports; this mixer correction matrix, determined via a calibration routine, may be frequency dependent; thus, a mixer definition may include the mixer's name and a list of one or more frequencies and the correction matrix to be used at each frequency; in one example implementation, the correction matrix is loaded into corresponding pulse modification circuit during compilation; similarly, an element definition may include an intermediate frequency with which every pulse sent to the element is to be modulated) (Negoro, ¶¶ [0056]-[0062] and [0088] with FIG. 3: when the monitor signal corresponds to the second microwave signal OUT2, the receiving logic 318 calculates a difference between the monitor signal and the baseband signal output from the transmitting logic 316, and sets a correction parameter for eliminating the difference, as a parameter 316a for the transmitting logic 316.; the transmitting logic 316 corrects, in accordance with the parameter 316a, the baseband signal generated from the waveform signal held in the HBM 314, and outputs the corrected baseband signal. With the automatic calibration based on the monitor signal as described above, it is possible to improve usability, and achieve high performance and high stability).
Independent Claim 12
Szmuk teaches a microwave pulse generator that outputs a microwave pulse that quantum manipulates a quantum bit selected from a quantum bit array and shifted in angular frequency, comprising: a logic circuit that outputs pulse data with a set pulse width and amplitude, a frequency generator that outputs a sine wave having the same frequency as the selected quantum bit (Szmuk, ¶¶ [0026]-[0039] with FIGS. 2A-D: the quantum programming subsystem 202 comprises circuitry operable to generate a pulse generation program and quantum machine specification 206 which configures the quantum controller 210 and includes instructions the quantum controller 210 can execute to carry out the quantum algorithm (i.e., generate the necessary outbound quantum control pulse(s)) with little or no human intervention during runtime; the quantum programming subsystem 202 is coupled to the quantum controller 210 which comprises circuitry operable to load the machine code from the programming subsystem 202, and then execute the machine code to generate the necessary outbound quantum control pulse(s) that correspond to the desired operations to be performed on the quantum processor 218 (e.g., sent to qubit(s) for manipulating a state of the qubit(s) or to readout resonator(s) for reading the state of the qubit(s), etc.) and/or process inbound pulses returning from the quantum processor 218 via front-end circuitry 254; whether to transmit one or more outbound pulse and/or characteristics of one or more outbound pulse to be transmitted may be predetermined at design time and/or may be determined during runtime; the quantum controller 210 is coupled to front-end circuitry 254; the quantum controller 210 may comprise a plurality of interconnected, but physically separate quantum control modules 250; the number of quantum control modules 250 needed for a particular quantum system may be determined based on the number of qubits of the quantum processor 218 and their architecture (tunability, connectivity, coupling elements and readout architecture); in general, the quantum processor 218 comprises K (an integer) quantum elements 122, which includes qubits (which could be of any type such as superconducting, spin qubits, ion trapped, etc.), and, where applicable, any other element( s) for processing quantum information, storing quantum information (e.g. storage resonator), and/or coupling outbound quantum control pulses from front-end circuitry 254 and inbound quantum control pulses to the front-end circuitry 254; the quantum processor 218 comprises 4 readout elements 226 and 4 qubits 22; port(s) 262 represent RF output ports via which pulses are sent to qubits of the quantum processor (in the example of FIG. 2A, 262 corresponds to 2251-2254); port(s) 264 represent RF output ports via which pulses are sent to readout elements of the quantum processor (in the example of FIG. 2A, 264 corresponds to 2250); port(s) 268 represent IF input ports via which pulses to be sent to qubits of the quantum processor 218 are received from a controller module 250 (in the example of FIG. 2A, 268 corresponds to one or more of 2211-2214); port(s) 270 represent IF input ports via which pulses to be sent to readout elements of the quantum processor 218 are received from a controller module 250 (in the example of FIG. 2A, 270 corresponds to 2210); the front-end circuitry 254 is operable to receive outbound intermediate frequency (IF) pulses from quantum controller 210 via one or more ports 221, upconvert the IF pulses to RF using the local oscillator signals received via one or more LO ports 229, and output the RF pulses to quantum processor 218 via one or more output ports 225; the number of front-end-circuitry modules needed for a particular quantum system may be determined based on the number of qubits of the quantum processor 218 and their architecture (tunability, connectivity, preparation, trapping, coupling elements and readout architecture); a signal 259 from the quantum programming subsystem 202 and/or a signal 257 from the quantum controller module 250 may open and close switching elements of the circuitry 254, adjust gains within the circuitry 254, adjust coefficients of filters within the circuitry 254, and/or otherwise configure the RF, IF, and/or LO signal paths of circuitry 254; the multi-tone generator 222 is operable to generate one or more signals at one or more desired frequencies, which will typically be dictated by the particular quantum processor 218 (e.g., based on the resonant frequencies of quantum elements of the quantum processor 218); two types of outputs are provided by quantum multi-tone generator 222: (a) one or more fixed frequency continuous wave (CW) tones 223; and (b) one or more synthesized frequency signals 231; allows splitting a tone 223 into up to six LO signals using a suitable power splitting circuit, without any additional active RF components; e.g., there are eight tones with f0=500 MHz and thus the tones 223 range from 2.5 GHz to 6 GHz in steps of 500 MHz; this, together with the ability of the quantum controller 210 to accurately and dynamically control the frequencies of IF pulses it generates (see e.g., FIGS. 6A and 6B, below), enables addressing qubits within a band of frequencies that covers all currently known and proposed superconducting qubit implementations; the synthesized signal or signals 231 output an adjustable frequency RF tone within a band of frequencies that contains, e.g., the band 4 GHz to 8 GHz; this, together with the ability of the quantum controller 210 to accurately and dynamically control the frequencies of IF pulses it generates (see e.g., FIGS. 6A and 6B, below), enables, for example, addressing various readout elements that use a wide range of frequencies; of course, different and/or other frequencies can be used to accommodate different qubit implementations; the connectivity circuitry 224 is operable to couple the outputs of the multi-tone generator 222 to the inputs of the front-end circuitry 254; because the desired connections between multi-tone generator 222 and quantum processor 218 depends on the architecture and operating frequencies of the quantum processor 218, the connectivity circuitry 224 is configurable by the user to support whatever configurations users may need for their particular quantum algorithms and particular quantum processor 218; the signal 253 from the quantum programming subsystem 202 and/or a signal 255 from the quantum controller module 250 may configure signal paths within circuitry 224 (e.g., by opening and closing switches, adjusting gains, adjusting filter coefficients, and/or the like); the reference generator circuit 219 provides a reference signal that the multi-tone generator 222 splits, frequency multiplies, amplifies and filters to generate signals 2230 -2237 and 231; in an example implementation, the low-phase-noise reference generator 219 is an oven-controlled crystal oscillator (OCXO) or other low-phase-noise reference generator 219; ¶¶ [0040]-[0054] with FIGS. 2A and 3: the quantum controller 210 comprises pulsers 3021 -302L-1, receive analog frontend 350, input manager 352, digital manager 354, pulse operations manager 356, pulse operations 358, output manager 360, transmit analog frontend 362, data exchange 364, synchronization manager 366, and input/output ("I/O") manager 368; the signal routing and multiplexing/demultiplexing functions performed by the input manager 352 enables: a particular pulser 302I to process different inbound pulses from different quantum elements at different times; a particular pulser 302I to process different inbound pulses from different quantum elements at the same time; and multiple of the pulsers 3020-302L-1 to processes the same inbound pulse at the same time; each pulser circuit 302I (I between 0 and L-1) comprises circuitry operable to generate outbound pulses according to quantum control operations to be performed on the quantum processor 218; this involves very precisely controlling characteristics such as phase, frequency, amplitude, and timing of the outbound pulses; the outbound pulses may be, e.g., control pulses sent to the quantum processor 218 to manipulate one or more properties of one or more quantum elements — e.g., manipulate a state of one or more qubits, manipulate a frequency of a qubit using flux biasing, etc., and/or readout a state of one or more quantum elements; the characteristics of an outbound pulse generated at any particular time may be determined, at least in part, on inbound pulses received from the quantum processor 218 via frontend circuitry 220 at a prior time; the time required to close the feedback loop (i.e., time from receiving a first pulse on an output 217 of front-end circuitry 254 to sending a second pulse (e.g., at an input 221 of front-end circuitry 254), where the second pulse is based on the first pulse, is significantly less than the coherence time of the qubits of the quantum processor 218; pulser 302I may process the inbound signal AII to determine the state of certain quantum element(s) in the quantum processor 218 and use this state information for making decisions such as, e.g., which raw outbound pulse CP'I to generate next, when to generate it, and what control signals to generate to affect the characteristics of that raw outbound pulse appropriately; the pulse operations circuitry 358 is operable to process the raw outbound pulses CP'0 -CP'L-1 to generate corresponding output outbound pulses CP0-CPL-1; this may comprise, e.g.,, manipulating the amplitude, phase, and/or frequency of the raw pulse CP'I; the output manager 360 enables: routing outbound pulses from a particular pulser 3021 to different ones input ports 221 at different times; routing outbound pulses from a particular pulser 3021 to multiple of the input ports 221 at the same time; and multiple of the pulsers 3020 -302L-1 generating pulses for the same input port 221 at the same time; at any given time, the output manager 360 is operable to concurrently route K of the digital signals CP0-CPL-1 as K independent outbound pulses, concurrently route K/2 of the digital signals CP0-CPL-1 as two-pulse pairs, or route some of signals CP0-CPL-1 as independent outbound pulses and some others of the signals CP0-CPL-1 as multi-pulse sets (at different times and/or concurrently); the digital manager 354 comprises circuitry operable to process and/or route digital control signals (DigCtrl0-DigCtrlJ-1) to various circuits of the quantum controller 210 and/or external circuits coupled to the quantum controller 210; each destination of the digital signals may require different operations to be performed on the digital signal (such as delay, broadening, or digital convolution with a given digital pattern); these operations may be performed by the digital manager 354 and may be specified by control signals from the pulsers 3020-302L-1; this allows each pulser 3021 to generate digital signals to different destinations and allows different ones of pulsers 3020-302L-1 to generate digital signals to the same destination while saving resources; the data exchange circuitry 364 is operable to manage exchange of data among the various circuits shown in FIG. 3; pulser 3021 may need to share, with pulser 3022, the characteristics of an inbound signal AI1 that it just processed so that pulser 3022 can generate a raw outbound pulse CP'2 based on the characteristics of AI1; ¶¶ [0055]-[0059] with FIG. 4: each pulse template stored in memory 404 comprises a sequence of one or more samples of any arbitrary shape (e.g., Gaussian, sine, impulse, etc.) representing the pulses to be sent to pulse operation circuitry 358; ¶¶ [0060]-[0071] with FIGS. 2A, 3 and 5: the pulse operations circuitry 358 comprises a plurality of pulse modification circuits 5080-508R-1 (R is an integer≥1 in general, and R=L/2 in the example shown); the pulse operations manager 356 comprises control circuitry 502, routing circuitry 506, and a plurality of modification settings circuits 5040-504K-1; assuming CP1 and CP2 are a phase-quadrature pulse pair to be output; in this example, pulse operations circuitry 358 may process CP1 and CP2 by multiplying a vector representation of CP'1 and CP'2 by one or more 2 by 2 matrices to: (a) perform single-sideband-modulation, where ω is the frequency of the single side band modulation and TS is the time passed since the reference time (e.g. the beginning of a certain control protocol); (b) keep track of frame-of-reference rotations, where ϕ is the total phase that the frame of reference accumulated since the reference time; and/or (c) perform an IQ-mixer correction where C00, C01, C10, and C11 are the elements of a matrix that corrects for IQ-mixer imperfections; each modification settings circuit, 504k, contains registers that contain the matrix elements of three matrices: an IQ-mixer correction matrix Ck; a single sideband frequency modulation matrix Sk; and a frame rotation matrix Fk, which rotates the IQ axes around the axis perpendicular to the IQ plane (i.e. the z-axis if I and Q are the x-axis and y-axis); each pulse modification circuit 508r is operable to process two raw outbound pulses CP'2r and CP'2r+1; such processing may comprise adjusting a phase, frequency, and/or amplitude of the raw outbound pulses CP'2r and CP'2r+1; pulse modification settings output to pulse operations circuitry 358 are specifically tailored to each raw outbound pulse (e.g., to which quantum element 226 or 228 the pulse is destined, to which input port 221 of front-end circuitry 254 the pulse is destined, etc.) to be processed by pulse operations circuitry 358; each path a pulse may travel to the quantum processor 218 via frontend circuitry 254 may have particular characteristics (e.g., non-idealities of interconnect, mixers, switches, attenuators, amplifiers, and/or circuits along the paths) to be accounted for by the pulse modification operations; similarly, each quantum element 1220-122k may have a particular characteristics (e.g. resonance frequency, frame of reference, etc.); the routing circuitry 506 is operable to route modification settings from the modification settings circuits 5040 -504L-1 to the pulse operations circuit 358 and to the pulsers 3020-302L-1; the pulser 3021 may determine ops_slct1 based on the particular quantum element 122k and/or signal path to which the pulse is to be transmitted (e.g., the resonant frequency of the quantum element, frame of reference, and/or mixer correction); the determination of which quantum element and/or signal path to which a particular pulser 3021 is to send an outbound pulse at a particular time may be predetermined in the pulse generation program and quantum machine specification 206 or may be determined based on calculations performed by the pulser 3021 and/or others of the pulsers 3020-302L-1 during runtime; the digital signal IFI instructs the pulse operations manager 356 to update a frequency setting of the modification settings circuit 504k indicated by ops_slct1; ¶¶ [0072]-[0079] with FIGS.3 and 6A-B: the frequency generation circuitry is part of control circuitry 502 of pulse operations manager circuitry 356; each CORDIC circuit 602k is operable to compute cosine and sine of its input, θk, thus generating two signals cos(θk) and sin(θk); the phase generation circuitry 604 is operable to generate the CORD IC input parameters θ0-θk-1 based on: (a) the frequency setting signals IF0-IFL-1 from the pulsers 3020-302L-1; and (b) the contents, TS, of the timestamp register 606; the timestamp register 606 comprises circuitry (e.g., a counter incremented on each cycle of the clock signal clk1) operable to track the number of cycles of clk1 since a reference point in time (e.g., power up of the quantum controller 210, start of execution of set of instructions of a pulse generation program by the quantum controller 210, etc.); the phase generation circuitry 604 sets θ0=2πf0(TS)(dtclk1), where f0 is a frequency determined from the signal IF0, TS is the number of clock cycles counted from the reference point and dtclk1 is the duration of a single clock cycle of clk1; this leads to the CORD IC outputs being a pair of phase-quadrature reference signals, cos(2πf0(TS)(dtclk1)) and sin(2πf0(TS)(dtclk1)), as in the example shown, which are used to generate the S0 rotation matrix that rotates at a frequency f0; as shown in FIG. 6B, the signal IFI may comprise an update component and an fI component; when updateI is asserted then the phase generation circuitry updates one of more of f0-fk-1 to be the value of fI; the S-matrix generation circuitry 608 is operable to build the matrices S0-SK-1 from the outputs of the CORDIC circuits 6020-602K-1; the S-matrix generation circuit 608 is operable to synchronize changes to the S matrices such that any matrix update occurs on a desired cycle of clock clk1 (which may be determined by the control information IF0-IFL- 1); in instances that more than K frequencies are needed over the course of a set of instructions, the phase generation circuit 604 is operable to change the input parameter θk of one or more of the CORDIC circuits 6020-602K-1 to stop generating one frequency and start generating the K+1th frequency; it may be necessary for the new frequency to start at a phase θ that would have been the phase if the new frequency was being generated from the initial reference time (e.g., because the new frequency would be used to address a quantum element that has a resonance at the new frequency and that was coherent since the reference point); in some other instances, it might be necessary to start the new frequency from the phase that the old frequency ended in; ¶ [0093]: patternz of signal Pz may be determined based on: the destination(s) of signal Pz; characteristics of the corresponding quantum control pulse (e.g., any one or more of its frequency, phase, amplitude, and/or duration); and/or process, temperature, and/or voltage variations; ¶¶ [0094]-[0106] with FIGS. 9A-B: FIG. 9A illustrates configuration and control of the quantum controller via the quantum programming subsystem; connected to the inputs and outputs of the quantum controller 210 may be a plurality of external devices (e.g., oscilloscopes, waveform generators, spectrum analyzers, mixers, amplifiers, etc.) and a plurality of quantum elements; the pulse generation program 904 comprises statements that define a sequence of operations to be performed by the quantum machine defined in the specification 902; such operations typically include the generation of one or more analog pulses to be sent to a controlled element, such as a quantum element; such operations typically include measuring one or more return pulses from an element; the pulse generation program is also referred to herein as a QUA program; defines the sequence of statements for: (a) generating, shaping and sending pulses to the quantum device; (b) measuring of pulses returning from the quantum device; (c) performing real-time classical calculations on the measured data and storing results in classical variables; (d) performing real-time classical calculations on classical variables; (e) controlling the flow of the program, including branching statements; and (6) streaming of data from the quantum controller 210 to the quantum programing system 202 and processing and saving it in the quantum programing system 202; a QUA program can define exactly the timing in which pulses are played, down to the single sample level and single clock cycles of the quantum controller 210; during compilation, pulse modification settings for manipulating pulses intended for an element may be generated (for loading into pulse modification settings circuits 504) and the pulse modification setting circuit(s) 504 to which they will be loaded before execution may be chosen and may be allocated to the quantum machine on which the program is to be executed; similarly, parameters and configurations of operations that will be performed on input signals related to an element (e.g. readout/measurement pulses) may be generated during compilation (for loading into compute and signal processing circuits 410); an element that a quantum machine may contain is a mixer of front-end circuitry 254; to correct for mixer imbalances, the in-phase/quadrature (10) waveforms of the pulse can be multiplied by a 2x2 mixer correction matrix before being sent to the output ports; this mixer correction matrix, determined via a calibration routine, may be frequency dependent; thus, a mixer definition may include the mixer's name and a list of one or more frequencies and the correction matrix to be used at each frequency; in one example implementation, the correction matrix is loaded into corresponding pulse modification circuit during compilation; similarly, an element definition may include an intermediate frequency with which every pulse sent to the element is to be modulated; when generating local oscillators for quantum control, it is desirable to minimize phase noise at offset from the carrier frequency that are determined by typical quantum gate(s) times, and typical quantum element coherence times; e.g., for one quantum system with shorter gate time it may be desirable to minimize phase noise in the range of 10 MHz to 100 MHz, whereas for another quantum system with longer gate times, it may be desirable to minimize phase noise in the range of 100 Hz to 100 kHz; also, the tolerable amount of phase noise may depend on the quantum system being controlled and/or the quantum algorithm being performed; some systems and/or algorithms can tolerate higher phase noise' laboratories using these systems and/or running these algorithms could benefit from a lower-cost implementation of multi-tone generator 222), a converter that converts the pulse data into an analog signal (Szmuk, ¶ [0049] with FIGS. 2A and 3: the transmit analog frontend 362 comprises circuitry operable to concurrently process up to K digital signals DOk to generate up to K concurrent analog signals AOk to be output to inputs 221 of the front-end circuitry 254; such processing may comprise, e.g., digital-to analog conversion, filtering, upconversion, downconversion, amplification, attenuation, time division multiplexing/demultiplexing, frequency division multiplexing/demultiplexing and/or the like; the transmit analog frontend 362 is operable to process digital signals DO0-DOK-1 as K independent outbound pulses, as K/2 two-pulse pairs, or process some of signals DO0-DOK-1 as independent outbound pulses and some signals DO0-DOK-1 as two-pulse pairs (at different times and/or concurrently)), modulates it with the sine wave, and outputs a signal having the frequency of the sine wave as the center frequency as a microwave pulse (Szmuk, ¶¶ [0032]-[0039] with FIG. 2A-D: the front-end circuitry 254 is operable to receive outbound intermediate frequency (IF) pulses from quantum controller 210 via one or more ports 221, upconvert the IF pulses to RF using the local oscillator signals received via one or more LO ports 229, and output the RF pulses to quantum processor 218 via one or more output ports 225; each IF input port 221 is configured to receive an independent pulse or multi-pulse pair (e.g., an IQ pair of pulses comprising an in-phase pulse and quadrature-phase pulse); in the latter case, the front-end circuitry 254 is operable to perform IQ upconversion; in FIG. 2D, the circuitry 254 comprises 6 IQ mixers 270; each of mixers 2700-2704 receives an IQ pair of IF signals via a respective one of ports 2210-2214, and uses an LO signal received via a respective one of ports 2290-2294 to upconvert the IQ pair to a corresponding RF signal output via a respective one of ports 2250 -2254; the multi-tone generator 222 is operable to generate one or more signals at one or more desired frequencies, which will typically be dictated by the particular quantum processor 218 (e.g., based on the resonant frequencies of quantum elements of the quantum processor 218); two types of outputs are provided by quantum multi-tone generator 222: (a) one or more fixed frequency continuous wave (CW) tones 223; and (b) one or more synthesized frequency signals 231; the connectivity circuitry 224 is operable to couple the outputs of the multi-tone generator 222 to the inputs of the front-end circuitry 254; the connectivity circuitry 224 can connect any one or more of the signals 2230 -2237 and 231 to any one or more of the input ports 2290 -2295 of front-end circuitry 254), and a frequency divider that (Szmuk, ¶ [0050] with FIGS. 2A and 3: the output manager 360 comprises circuitry operable to route any one or more of signals CP0-CPL-1 to any one or more input ports 221 of the front-end circuitry 254; the output manager 360 comprises one or more switch networks, multiplexers, and/or the like for dynamically reconfiguring which one or more signals CP0-CPL-1 are routed to which input port(s) 221 of the front-end 220; this may enable time division multiplexing multiple of the signals CP0-CPL-1 onto a single input port 221 of the front-end circuit 220 and/or time division demultiplexing components (e.g., time slices) of a signal CP m onto multiple of the input ports 221 of the front-end circuitry 254; the output manager 360 comprises one or more mixers and/or filters for frequency division multiplexing multiple of the signals CP0-CPM-1 onto a single input port 221 of front-end circuitry 254 and/or frequency division demultiplexing components (e.g., frequency bands) of a signal CPm onto multiple of the input ports 221 of the front-end circuitry 254; ¶¶ [0034] and [0038] with FIG. 2A: allows splitting a tone 223 into up to six LO signals using a suitable power splitting circuit, without any additional active RF components; the reference generator circuit 219 provides a reference signal that the multi-tone generator 222 splits, frequency multiplies, amplifies and filters to generate signals 2230 -2237 and 231; ¶¶ [0075]-[0078]: the timestamp register 606 comprises circuitry (e.g., a counter incremented on each cycle of the clock signal clk1) operable to track the number of cycles of clk1 since a reference point in time (e.g., power up of the quantum controller 210, start of execution of set of instructions of a pulse generation program by the quantum controller 210, etc.); a desired cycle of clock clk1 (which may be determined by the control information IF0-IFL- 1); ¶ [0107] with FIG. 10: the signal processing circuitry is operable to perform splitting, frequency multiplication, gain adjustment, filtering, and/or other signal processing operations to generate M+1 local oscillator signals 1003 from the OCXO output 1001), wherein the frequency generator operates at the same frequency as the quantum bit other than the selected quantum bit except when the microwave pulse is output (Szmuk, ¶¶ [0042]-[0050] with FIGS. 2A and 3: the signal routing and multiplexing/demultiplexing functions performed by the input manager 352 enables: a particular pulser 302I to process different inbound pulses from different quantum elements at different times; a particular pulser 302I to process different inbound pulses from different quantum elements at the same time; and multiple of the pulsers 3020-302L-1 to processes the same inbound pulse at the same time; each pulser circuit 302I (I between 0 and L-1) comprises circuitry operable to generate outbound pulses according to quantum control operations to be performed on the quantum processor 218; this involves very precisely controlling characteristics such as phase, frequency, amplitude, and timing of the outbound pulses; the outbound pulses may be, e.g., control pulses sent to the quantum processor 218 to manipulate one or more properties of one or more quantum elements — e.g., manipulate a state of one or more qubits, manipulate a frequency of a qubit using flux biasing, etc., and/or readout a state of one or more quantum elements; the characteristics of an outbound pulse generated at any particular time may be determined, at least in part, on inbound pulses received from the quantum processor 218 via frontend circuitry 220 at a prior time; ¶¶ [0107]-[0111] with FIGS. 2A and 10: a quantum control multi-tone generator (e.g., multi-tone generator 222) comprising oven-controlled crystal oscillator (OCXO) and signal processing circuitry 1002; the signal processing circuitry is operable to perform splitting, frequency multiplication, gain adjustment, filtering, and/or other signal processing operations to generate M+1 local oscillator signals 1003 from the OCXO output 1001; the signal 1001 is at frequency fi, ID is a multiple of fi, each of the signals 223 is at a multiple of ID, and each of k and M are integers; the use of multiple fixed-frequency tones, avoids the need for the voltage controlled oscillators and phase locked loops used in the signal generators conventionally used for driving quantum systems, which has the benefit of greatly reducing phase noise in the circuitry 222 (in general VCOs introduce additional phase noise as compared to OCXOs); the quantum control multi-tone generator 222 also comprises a variable frequency signal generator 1004 operable to output a signal 231 having a variable (i.e., tunable) frequency; the variable frequency generator 1004 may be driven by the same reference signal that is input to the OCXO 1000 (e.g., a 10 MHz signal) and/or may be driven by the signal 1001 output by OXCO 1000 (e.g., a 1000 MHz signal); the use of a single fundamental frequency, fi, which is then upconverted to the output frequencies using mixers, amplifiers, and bandpass filters provides positive phase correlation between the phase noises of the outputs; this generation of coherent tones through multiplication and filtering of a common reference signal may increase quantum gate fidelity in scenarios where multiple sequential single-gate operations are applied to qubits that are operating using different frequency tones, as well as two-qubit gate operations; the signal processing circuit 1002 performs fanout, frequency multiplication, amplification, and filtration functions; ¶¶ [0112]-[0141] with FIGS. 11A-D: a quantum control multi-tone generator in FIG. 11A including the OCXO 1000 and the circuit 1002 which outputs M multiples of the fi; each of the outputs of circuit 1002 is then input to circuitry comprising a PLL and DRO 1120 in a feedback arrangement to generate a signal 223; the DROs have the effect of lowering phase noise in the signals 223 at frequencies far from the carrier frequency; a quantum control multi-tone generator in FIG. 11B uses only a single DRO 1120 and PLL 1104; the outputs of circuit 1002 and the DRO 1120 feed a signal processing circuit 1122 which mixes the signals 11060-1106N-1 (N is an integer) to generate signals 2230-223M-1; which of the N+1 signals 11060-1106N-1 is selected as signal 1106q (q is an integer where 0≤q≤N-1) to be input to the PLL 1104 may be determined (e.g., preconfigured or controlled programmatically during operation via signal(s) 253, 255, 257, and/or 259) based on the desired frequencies of the signals 2230-223M; the number of signals 223 and/or the frequency spacing of the signals 223 may be determined based on the range of frequencies that the control circuitry 502 of quantum controller 210 is configured to generate; the circuit 1002 may comprise one or more frequency multiplier circuits 1052; each circuit 1150 comprises M, an integer, multiplier circuits 1052, each of which generates an output signal that is an integer multiple of its input signal (in addition to the frequency multiplication, each circuit 1052 may also perform filtering and/or other signal conditioning operations such as current and/or voltage amplification to make the output signal suitable for driving one or more of: another multiplication circuit 1052, a PLL such as 1104, mixer(s) of the circuit 1122, and/or one or more inputs of the circuit 224; the circuit 1122 may comprise one or more mixer circuits 1152; through setting (either at design time or in the field using jumpers, variable resistors, switches, etc.) the multiplication factors of each multiplier 1052, the number of circuits 1150, the number of circuits 1152, and/or the interconnection of the circuits 1150 and 1152, a wide range of frequencies and channel spacings can be achieved to support a wide range of quantum processors and a wide range of quantum controllers; e.g., the multipliers are configured and connected to achieve 24 output frequencies spaced at 4fi, as follows: (a) circuit 11500 outputs: (i) fi, which drives an output port of the multitone generator 222; (ii) 4fi, which drives the input of circuit 11501, and is the basis for the frequency spacing; and (iii) 10fi, which drives an output port of the multitone generator 222; (b) circuit 11501 outputs: (i) 4fi, which drives an input of each of circuits 11520 , 11521 , and 11522; (ii) 8fi, which drives an input of each of circuits 11520 , 11521 , and 11522; (iii) 12fi, which drives an input of each of circuits 11520 , 11521 , and 11522; and (iv) 16fi, which drives an input of circuit 11502; (c) circuit 11502 outputs: (i) 16fi, which drives an output port of the multitone generator 222; (ii) 32fi, which drives an input of circuit 11520; (iii) 48fi, which drives an input of circuit 11521; (iii) 64fi which drives an input of circuit 11522; and (iv) 80fi, which drives an output port of the multitone generator 222; (d)circuit 11520 receives 4fi, 8fi, 12fi, and 32fi and outputs 28fi, 36fi, 40fi, 24fi, 44fi, and 20fi; (e) circuit 11521 receives 4fi, 8fi, 12fi, and 48fi and outputs 52fi, 44fi, 56fi, 40fi, 60fi, and 36fi; and (f) circuit 11522 receives 4fi, 8fi, 12fi, and 64fi and outputs 68fi, 60fi, 72fi, 56fi, 76fi, and 52fi; the multi-tone generator is operable to generate a plurality of fixed-frequency signals from a single fixed-frequency reference signal (e.g., 2230 -2237), and output the plurality of fixed-frequency signals via a corresponding plurality of output ports (e.g., ports of 222); each of the plurality of fixed-frequency signals may be at a different one of a plurality of frequencies from a first frequency (e.g., 2.5 GHz) to a second frequency (e.g., 6 GHz); the frequency spacing between frequency-adjacent signals of the plurality of fixed-frequency signals may be less than or equal to a range of frequencies (e.g., a range of 500 MHz) at which the quantum control pulse generation circuitry is configured to generate a pulse signal (e.g., AO0) such that any frequency in the range from the first frequency to the second frequency for controlling quantum elements can be achieved through tuning of the pulse signal and mixing of the pulse signal with one of the plurality of fixed-frequency signals; the quantum control pulse generation circuit may be operable to generate baseband pulses, and upconvert the baseband pulses to an intermediate frequency to generate the quantum control pulses, wherein the intermediate frequency is tunable over a range at least as large as the first frequency spacing), and the logic circuit operates in synchronization with the system clock (Szmuk, ¶ [0052] with FIG. 3: the synchronization manager 366 comprises circuitry operable to manage synchronization of the various circuits shown in FIG. 3; such synchronization is advantageous in a modular and dynamic system, such as quantum controller 210, where different ones of pulsers 3020-302L-1 generate, receive, and process pulses to and from different quantum elements at different times; e.g., a pulse generation program may require that a first pulser circuit 3021 and a second pulser circuit 3022 sometimes need to transmit pulses at precisely the same time, and at other times transmit pulses independently of one another; the synchronization manager 366 reduces the overhead involved in performing such synchronization; ¶ [0078] with FIGS. 6A-B: the S-matrix generation circuit 608 is operable to synchronize changes to the S matrices such that any matrix update occurs on a desired cycle of clock clk1 (which may be determined by the control information IF0-IFL- 1); ¶ [0086] with FIGS. 3 and 7: each of the controlled circuits 7100-710J-1 and input manager 372 is a circuit which, at least some of the time, needs to operate synchronously with quantum control pulses generated by one or more of pulsers 3020-302L-1 (possibly a reflection/return pulse from a quantum processor in the case of input manager 372); accordingly, each of the control circuits 7100-710J-1 receives a respective one of control signals DigOut0-DigCtrlJ-1 that is synchronized with a respective quantum control pulse).
Szmuk fails to explicitly disclose a frequency divider that outputs a system clock divided by the frequency of the wave.
Negoro teaches a system and a method relating to a quantum computer controller (Negoro, ¶ [0001]), wherein a frequency divider that outputs a system clock divided by the frequency of the wave (Negoro, ¶¶ [0027]-[0032] with FIG. 2: the quantum computer 100 includes a controller 110 and a qubit system 120 having a plurality of qubits; the controller 110 includes a server 130, a plurality of signal processing units 140-1, a clock distribution unit 150, and a master 160; upon receipt of an instruction input from a user, the server 130 calculates a waveform signal required for state manipulation of the qubits of the qubit system 120 or for readout from the qubit system 120, and outputs the waveform signal to each of the signal processing units 140-1; the clock distribution unit 150 distributes a common clock to the signal processing units 140-I; the master 160 distributes a common time to the signal processing units 140-i in accordance with a time synchronization protocol; each of the signal processing units 140-i is designed by integrating the functions of the baseband circuits 40, the oscillation circuit 50, and the analog circuit 60 of the conventional quantum computer shown in FIG. 1 into a single unit, and generates, based on the waveform signal calculated by the server 130, a microwave signal (electromagnetic wave signal) with which the qubit system 120 is irradiated; ¶¶ [0055]-[0063] with FIG. 3: the dividers 372 are respectively provided at the output stages of the filter/multiplier units 370; the microwave signal from the filter/multiplier unit 370 is divided into two signals (a first microwave signal OUT1 and a second microwave signal OUT2) by the divider 372; the first microwave signal OUT1 is emitted onto the qubits of the qubit system 120 through a cable, and the second microwave signal OUT2 is output to the feedback circuit 380; some of the plurality of first microwave signals OUT1 are control signals for manipulating the states of the qubits, and the remaining first microwave signals OUT1 include a read pulse for reading the qubits and a pump pulse for amplifying the read signal; when the second microwave signal OUT2 is selected, the second microwave signal OUT2 is used for correcting the baseband signal as described below; on the other hand, when the external signal EXT from the other signal processing unit 140-j is selected, the external signal EXT is used for monitoring synchronization between different signal processing units 140-i and 140-j (i≠j); when the monitor signal corresponds to the second microwave signal OUT2, the receiving logic 318 calculates a difference between the monitor signal and the baseband signal output from the transmitting logic 316, and sets a correction parameter for eliminating the difference, as a parameter 316a for the transmitting logic 316; the transmitting logic 316 corrects, in accordance with the parameter 316a, the baseband signal generated from the waveform signal held in the HBM 314, and outputs the corrected baseband signal; with the automatic calibration based on the monitor signal as described above, it is possible to improve usability, and achieve high performance and high stability; when the monitor signal corresponds to the external signal EXT input from the other signal processing unit 140-j to the signal processing unit 140-i (i≠j), the receiving logic 318 of the signal processing unit 140-i compares the monitor signal with a reference signal to analyze the synchronization between the different signal processing units 140-i and 140-j, and writes the analysis result into the HBM 314; ¶¶ [0066]-[0069] with FIGS. 3, 5, and 7B: the clock distribution unit 150 includes a clock generation source 510, a first clock generator 521, a second clock generator 522, and a third clock generator 523; the clock generation source 510 generates a clock with a given frequency (e.g., 10 MHz); the clock generated by the clock generation source 510 is distributed into the first clock generator 521, the second clock generator 522, and the third clock generator 523; each of the first clock generator 521, the second clock generator 522, and the third clock generator 523 includes a phase-locked loop (PLL), a frequency divider circuit, and the like; the first clock generator 521, the second clock generator 522, and the third clock generator 523 generate a first clock, a second clock, and a third clock, respectively, having different frequencies from one another; the first clock, the second clock, and the third clock are distributed to all the signal processing units 140-1, 140-2, …, and 140-N, through signal lines 531, 532, and 533, respectively; the first clock is a system operation clock with a first frequency (e.g., 125 MHz); the second clock is a clock with a second frequency (e.g., 62.5 kHz) having a longer period than the first clock, and is used for synchronization in different channels between the logic device 310 and the DAC/ADC module 330 (see FIG. 7B); the third clock is a reference clock with a third frequency (e.g., 100 MHz), on which the oscillation signals of the oscillators (NCOs, LO) are based; the logic device 310 of each of the signal processing units 140-i generates, from the first clock, an operation clock with a higher frequency than the first clock).
Szmuk and Negoro are analogous art because they are from the same field of endeavor, a system and a method relating to a quantum computer controller. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to apply the teaching of Negoro to Szmuk. Motivation for doing so would provide better synchronization (Negoro, ¶¶ [0013], [0062], [0068]-[0069], [0071]-[0075], and [088]).
Claims 4, 6, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Szmuk in view of Negoro as applied to Claims 2, 2, and 13 respectively above, and further in view of Cohen et al. (US 2021/0036692 A1, pub. date: 02/04/2021), hereinafter Cohen'692.
Claims 4 and 15
Szmuk in view of Negoro discloses all the elements as stated in Claims 2 and 13 respectively and further discloses wherein the logic circuit outputs a frequency modulation signal based on the frequency of the selected quantum bit, and then outputs a frequency modulation signal based on the frequency of the selected quantum bit multiplied by a (Szmuk, ¶¶ [0032]-[0039] with FIG. 2A-D: the front-end circuitry 254 is operable to receive outbound intermediate frequency (IF) pulses from quantum controller 210 via one or more ports 221, upconvert the IF pulses to RF using the local oscillator signals received via one or more LO ports 229, and output the RF pulses to quantum processor 218 via one or more output ports 225; each IF input port 221 is configured to receive an independent pulse or multi-pulse pair (e.g., an IQ pair of pulses comprising an in-phase pulse and quadrature-phase pulse); in the latter case, the front-end circuitry 254 is operable to perform IQ upconversion; in FIG. 2D, the circuitry 254 comprises 6 IQ mixers 270; each of mixers 2700-2704 receives an IQ pair of IF signals via a respective one of ports 2210-2214, and uses an LO signal received via a respective one of ports 2290-2294 to upconvert the IQ pair to a corresponding RF signal output via a respective one of ports 2250 -2254; the multi-tone generator 222 is operable to generate one or more signals at one or more desired frequencies, which will typically be dictated by the particular quantum processor 218 (e.g., based on the resonant frequencies of quantum elements of the quantum processor 218); two types of outputs are provided by quantum multi-tone generator 222: (a) one or more fixed frequency continuous wave (CW) tones 223; and (b) one or more synthesized frequency signals 231; the connectivity circuitry 224 is operable to couple the outputs of the multi-tone generator 222 to the inputs of the front-end circuitry 254; the connectivity circuitry 224 can connect any one or more of the signals 2230 -2237 and 231 to any one or more of the input ports 2290 -2295 of front-end circuitry 254; ¶ [0056] with FIG. 4: each pulse template stored in memory 404 comprises a sequence of one or more samples of any arbitrary shape (e.g., Gaussian, sine, impulse, etc.) representing the pulses to be sent to pulse operation circuitry 358; ¶¶ [0060]-[0071] with FIGS. 2A, 3 and 5: the pulse operations circuitry 358 comprises a plurality of pulse modification circuits 5080-508R-1 (R is an integer≥1 in general, and R=L/2 in the example shown); the pulse operations manager 356 comprises control circuitry 502, routing circuitry 506, and a plurality of modification settings circuits 5040-504K-1; two of the pulsers 3020-302L-1 may generate two raw outbound pulses which are a phase-quadrature pulse pair; assuming CP1 and CP2 are a phase-quadrature pulse pair to be output; in this example, pulse operations circuitry 358 may process CP1 and CP2 by multiplying a vector representation of CP'1 and CP'2 by one or more 2 by 2 matrices to: (a) perform single-sideband-modulation, where ω is the frequency of the single side band modulation and TS is the time passed since the reference time (e.g. the beginning of a certain control protocol); (b) keep track of frame-of-reference rotations, where ϕ is the total phase that the frame of reference accumulated since the reference time; and/or (c) perform an IQ-mixer correction where C00, C01, C10, and C11 are the elements of a matrix that corrects for IQ-mixer imperfections; each modification settings circuit, 504k, contains registers that contain the matrix elements of three matrices: an IQ-mixer correction matrix Ck; a single sideband frequency modulation matrix Sk; and a frame rotation matrix Fk, which rotates the IQ axes around the axis perpendicular to the IQ plane (i.e. the z-axis if I and Q are the x-axis and y-axis); each pulse modification circuit 508r is operable to process two raw outbound pulses CP'2r and CP'2r+1; such processing may comprise adjusting a phase, frequency, and/or amplitude of the raw outbound pulses CP'2r and CP'2r+1; pulse modification settings output to pulse operations circuitry 358 are specifically tailored to each raw outbound pulse (e.g., to which quantum element 226 or 228 the pulse is destined, to which input port 221 of front-end circuitry 254 the pulse is destined, etc.) to be processed by pulse operations circuitry 358; each path a pulse may travel to the quantum processor 218 via frontend circuitry 254 may have particular characteristics (e.g., non-idealities of interconnect, mixers, switches, attenuators, amplifiers, and/or circuits along the paths) to be accounted for by the pulse modification operations; similarly, each quantum element 1220-122k may have a particular characteristics (e.g. resonance frequency, frame of reference, etc.); the routing circuitry 506 is operable to route modification settings from the modification settings circuits 5040 -504L-1 to the pulse operations circuit 358 and to the pulsers 3020-302L-1; the pulser 3021 may determine ops_slct1 based on the particular quantum element 122k and/or signal path to which the pulse is to be transmitted (e.g., the resonant frequency of the quantum element, frame of reference, and/or mixer correction); the determination of which quantum element and/or signal path to which a particular pulser 3021 is to send an outbound pulse at a particular time may be predetermined in the pulse generation program and quantum machine specification 206 or may be determined based on calculations performed by the pulser 3021 and/or others of the pulsers 3020-302L-1 during runtime; the digital signal IFI instructs the pulse operations manager 356 to update a frequency setting of the modification settings circuit 504k indicated by ops_slct1; ¶¶ [0072]-[0079] with FIGS.3 and 6A-B: the frequency generation circuitry is part of control circuitry 502 of pulse operations manager circuitry 356; each CORDIC circuit 602k is operable to compute cosine and sine of its input, θk, thus generating two signals cos(θk) and sin(θk); the phase generation circuitry 604 is operable to generate the CORD IC input parameters θ0-θk-1 based on: (a) the frequency setting signals IF0-IFL-1 from the pulsers 3020-302L-1; and (b) the contents, TS, of the timestamp register 606; the timestamp register 606 comprises circuitry (e.g., a counter incremented on each cycle of the clock signal clk1) operable to track the number of cycles of clk1 since a reference point in time (e.g., power up of the quantum controller 210, start of execution of set of instructions of a pulse generation program by the quantum controller 210, etc.); the phase generation circuitry 604 sets θ0=2πf0(TS)(dtclk1), where f0 is a frequency determined from the signal IF0, TS is the number of clock cycles counted from the reference point and dtclk1 is the duration of a single clock cycle of clk1; this leads to the CORD IC outputs being a pair of phase-quadrature reference signals, cos(2πf0(TS)(dtclk1)) and sin(2πf0(TS)(dtclk1)), as in the example shown, which are used to generate the S0 rotation matrix that rotates at a frequency f0; as shown in FIG. 6B, the signal IFI may comprise an update component and an fI component; when updateI is asserted then the phase generation circuitry updates one of more of f0-fk-1 to be the value of fI; the S-matrix generation circuitry 608 is operable to build the matrices S0-SK-1 from the outputs of the CORDIC circuits 6020-602K-1; the S-matrix generation circuit 608 is operable to synchronize changes to the S matrices such that any matrix update occurs on a desired cycle of clock clk1 (which may be determined by the control information IF0-IFL- 1); in instances that more than K frequencies are needed over the course of a set of instructions, the phase generation circuit 604 is operable to change the input parameter θk of one or more of the CORDIC circuits 6020-602K-1 to stop generating one frequency and start generating the K+1th frequency; it may be necessary for the new frequency to start at a phase θ that would have been the phase if the new frequency was being generated from the initial reference time (e.g., because the new frequency would be used to address a quantum element that has a resonance at the new frequency and that was coherent since the reference point); in some other instances, it might be necessary to start the new frequency from the phase that the old frequency ended in; ¶ [0105] with FIG. 2A: an element that a quantum machine may contain is a mixer of front-end circuitry 254; to correct for mixer imbalances, the in-phase/quadrature (10) waveforms of the pulse can be multiplied by a 2x2 mixer correction matrix before being sent to the output ports; this mixer correction matrix, determined via a calibration routine, may be frequency dependent; thus, a mixer definition may include the mixer's name and a list of one or more frequencies and the correction matrix to be used at each frequency; in one example implementation, the correction matrix is loaded into corresponding pulse modification circuit during compilation; similarly, an element definition may include an intermediate frequency with which every pulse sent to the element is to be modulated; ¶¶ [0107]-[0111] with FIGS. 2A and 10: a quantum control multi-tone generator (e.g., multi-tone generator 222) comprising oven-controlled crystal oscillator (OCXO) and signal processing circuitry 1002; the signal processing circuitry is operable to perform splitting, frequency multiplication, gain adjustment, filtering, and/or other signal processing operations to generate M+1 local oscillator signals 1003 from the OCXO output 1001; the signal 1001 is at frequency fi, ID is a multiple of fi, each of the signals 223 is at a multiple of ID, and each of k and M are integers; the use of multiple fixed-frequency tones, avoids the need for the voltage controlled oscillators and phase locked loops used in the signal generators conventionally used for driving quantum systems, which has the benefit of greatly reducing phase noise in the circuitry 222 (in general VCOs introduce additional phase noise as compared to OCXOs); the quantum control multi-tone generator 222 also comprises a variable frequency signal generator 1004 operable to output a signal 231 having a variable (i.e., tunable) frequency; the variable frequency generator 1004 may be driven by the same reference signal that is input to the OCXO 1000 (e.g., a 10 MHz signal) and/or may be driven by the signal 1001 output by OXCO 1000 (e.g., a 1000 MHz signal); the use of a single fundamental frequency, fi, which is then upconverted to the output frequencies using mixers, amplifiers, and bandpass filters provides positive phase correlation between the phase noises of the outputs; this generation of coherent tones through multiplication and filtering of a common reference signal may increase quantum gate fidelity in scenarios where multiple sequential single-gate operations are applied to qubits that are operating using different frequency tones, as well as two-qubit gate operations; the signal processing circuit 1002 performs fanout, frequency multiplication, amplification, and filtration functions; ¶¶ [0112]-[0141] with FIGS. 11A-D: a quantum control multi-tone generator in FIG. 11A including the OCXO 1000 and the circuit 1002 which outputs M multiples of the fi; each of the outputs of circuit 1002 is then input to circuitry comprising a PLL and DRO 1120 in a feedback arrangement to generate a signal 223; the DROs have the effect of lowering phase noise in the signals 223 at frequencies far from the carrier frequency; a quantum control multi-tone generator in FIG. 11B uses only a single DRO 1120 and PLL 1104; the outputs of circuit 1002 and the DRO 1120 feed a signal processing circuit 1122 which mixes the signals 11060-1106N-1 (N is an integer) to generate signals 2230-223M-1; which of the N+1 signals 11060-1106N-1 is selected as signal 1106q (q is an integer where 0≤q≤N-1) to be input to the PLL 1104 may be determined (e.g., preconfigured or controlled programmatically during operation via signal(s) 253, 255, 257, and/or 259) based on the desired frequencies of the signals 2230-223M; the number of signals 223 and/or the frequency spacing of the signals 223 may be determined based on the range of frequencies that the control circuitry 502 of quantum controller 210 is configured to generate; the circuit 1002 may comprise one or more frequency multiplier circuits 1052; each circuit 1150 comprises M, an integer, multiplier circuits 1052, each of which generates an output signal that is an integer multiple of its input signal (in addition to the frequency multiplication, each circuit 1052 may also perform filtering and/or other signal conditioning operations such as current and/or voltage amplification to make the output signal suitable for driving one or more of: another multiplication circuit 1052, a PLL such as 1104, mixer(s) of the circuit 1122, and/or one or more inputs of the circuit 224; the circuit 1122 may comprise one or more mixer circuits 1152; through setting (either at design time or in the field using jumpers, variable resistors, switches, etc.) the multiplication factors of each multiplier 1052, the number of circuits 1150, the number of circuits 1152, and/or the interconnection of the circuits 1150 and 1152, a wide range of frequencies and channel spacings can be achieved to support a wide range of quantum processors and a wide range of quantum controllers; e.g., the multipliers are configured and connected to achieve 24 output frequencies spaced at 4fi, as follows: (a) circuit 11500 outputs: (i) fi, which drives an output port of the multitone generator 222; (ii) 4fi, which drives the input of circuit 11501, and is the basis for the frequency spacing; and (iii) 10fi, which drives an output port of the multitone generator 222; (b) circuit 11501 outputs: (i) 4fi, which drives an input of each of circuits 11520 , 11521 , and 11522; (ii) 8fi, which drives an input of each of circuits 11520 , 11521 , and 11522; (iii) 12fi, which drives an input of each of circuits 11520 , 11521 , and 11522; and (iv) 16fi, which drives an input of circuit 11502; (c) circuit 11502 outputs: (i) 16fi, which drives an output port of the multitone generator 222; (ii) 32fi, which drives an input of circuit 11520; (iii) 48fi, which drives an input of circuit 11521; (iii) 64fi which drives an input of circuit 11522; and (iv) 80fi, which drives an output port of the multitone generator 222; (d)circuit 11520 receives 4fi, 8fi, 12fi, and 32fi and outputs 28fi, 36fi, 40fi, 24fi, 44fi, and 20fi; (e) circuit 11521 receives 4fi, 8fi, 12fi, and 48fi and outputs 52fi, 44fi, 56fi, 40fi, 60fi, and 36fi; and (f) circuit 11522 receives 4fi, 8fi, 12fi, and 64fi and outputs 68fi, 60fi, 72fi, 56fi, 76fi, and 52fi; the multi-tone generator is operable to generate a plurality of fixed-frequency signals from a single fixed-frequency reference signal (e.g., 2230 -2237), and output the plurality of fixed-frequency signals via a corresponding plurality of output ports (e.g., ports of 222); each of the plurality of fixed-frequency signals may be at a different one of a plurality of frequencies from a first frequency (e.g., 2.5 GHz) to a second frequency (e.g., 6 GHz); the frequency spacing between frequency-adjacent signals of the plurality of fixed-frequency signals may be less than or equal to a range of frequencies (e.g., a range of 500 MHz) at which the quantum control pulse generation circuitry is configured to generate a pulse signal (e.g., AO0) such that any frequency in the range from the first frequency to the second frequency for controlling quantum elements can be achieved through tuning of the pulse signal and mixing of the pulse signal with one of the plurality of fixed-frequency signals; the quantum control pulse generation circuit may be operable to generate baseband pulses, and upconvert the baseband pulses to an intermediate frequency to generate the quantum control pulses, wherein the intermediate frequency is tunable over a range at least as large as the first frequency spacing).
Szmuk in view of Negoro fails to explicitly disclose wherein the logic circuit outputs a frequency modulation signal based on the frequency of the selected quantum bit multiplied by a negative value.
Cohen'692 teaches a system and a method relating to frequency generation in a quantum controller (Cohen'692, ¶ [0003]), wherein the logic circuit outputs a frequency modulation signal based on the frequency of the selected quantum bit multiplied by a negative value (Cohen'692, ¶¶ [0071]-[0079] and [0094] with FIGS. 6A-B and 12A-B: the phase generation circuitry 604 can also generate CORDIC input parameters 80-8K-l that depend on time in a non-linear manner in order, for example, to generate an S-matrix that rotates at a frequency that increases or decreases in time (chirp); a chirp is a signal of the form s(t)=cos(ω(t)t), meaning that the frequency changes with time; a linear chirp can be written as ω(t)= ω0+at at for some constant a, so that s(t)=cos(ωt+at2); generate a signal having such a phase without having to do the whole multiplication every time; instead such systems can increment the phase every cycle; e.g., in the case of a signal with a fixed frequency (not a chirp), the phase is incremented by θinc=2πfk(dclk1) every clock cycle; the frequency can be provided by the pulser itself via the IFI signal along the chirp; in FIG. 6A, e.g., S0 could be chirped by pulser 3020 changing the frequency f0 on each clock cycle so that f=f0+(δf0)(TS-TSc); one advantage of this approach is that, because f0 is calculated by the pulser 3020 and pulser 3020 comprises circuitry for performing complex calculations, then complicated chirps such as nonlinear chirps ( chirps with different rates of frequency change), can be achieved; an example frequency generation circuitry operable to generate chirps; the signal IFI comprises two additional signals beyond those shown in FIG. 6B: (1) chirpl which indicates when a chirp is to start (e.g., is high during a chirp and low otherwise); and (2) δfl which indicates the rate of frequency change for the chirp (a positive value of δfk resulting in an upchrip and a negative value of δfk resulting in a down chirp); the phase generation circuitry 604 then generates θk=2πfk(dtclk1)+2π (δfk)(TS-TSkc)(TS)dtclk1, where TSkc is the clock cycle at which the chirp starts; when a chirp is not in progress (e.g., indicated by chirpk being low) then the second term in θk is 0, resulting in a constant frequency signal; θk may be fixed for each chirp; the phase generation circuitry 604 may reach δfk on each clock cycle for which chirp is high and thus the pulser that is generating δfk can manipulate δfk to achieve non-linear chirps).
Szmuk in view of Negoro, and Cohen'692 are analogous art because they are from the same field of endeavor, a system and a method relating to frequency generation in a quantum controller. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to apply the teaching of Cohen'692 to Szmuk in view of Negoro. Motivation for doing so would allow circuitry .
Claim 6
Szmuk in view of Negoro discloses all the elements as stated in Claim 2 and further discloses wherein the logic circuit acquires from an external source the frequency offset setting signal of the frequency of the selected quantum bit and the frequency offset signal of the frequency of the selected quantum bit multiplied by a (Szmuk, ¶¶ [0032]-[0039] with FIG. 2A-D: the front-end circuitry 254 is operable to receive outbound intermediate frequency (IF) pulses from quantum controller 210 via one or more ports 221, upconvert the IF pulses to RF using the local oscillator signals received via one or more LO ports 229, and output the RF pulses to quantum processor 218 via one or more output ports 225; each IF input port 221 is configured to receive an independent pulse or multi-pulse pair (e.g., an IQ pair of pulses comprising an in-phase pulse and quadrature-phase pulse); in the latter case, the front-end circuitry 254 is operable to perform IQ upconversion; in FIG. 2D, the circuitry 254 comprises 6 IQ mixers 270; each of mixers 2700-2704 receives an IQ pair of IF signals via a respective one of ports 2210-2214, and uses an LO signal received via a respective one of ports 2290-2294 to upconvert the IQ pair to a corresponding RF signal output via a respective one of ports 2250 -2254; the multi-tone generator 222 is operable to generate one or more signals at one or more desired frequencies, which will typically be dictated by the particular quantum processor 218 (e.g., based on the resonant frequencies of quantum elements of the quantum processor 218); two types of outputs are provided by quantum multi-tone generator 222: (a) one or more fixed frequency continuous wave (CW) tones 223; and (b) one or more synthesized frequency signals 231; the connectivity circuitry 224 is operable to couple the outputs of the multi-tone generator 222 to the inputs of the front-end circuitry 254; the connectivity circuitry 224 can connect any one or more of the signals 2230 -2237 and 231 to any one or more of the input ports 2290 -2295 of front-end circuitry 254; ¶ [0056] with FIG. 4: each pulse template stored in memory 404 comprises a sequence of one or more samples of any arbitrary shape (e.g., Gaussian, sine, impulse, etc.) representing the pulses to be sent to pulse operation circuitry 358; ¶¶ [0060]-[0071] with FIGS. 2A, 3 and 5: the pulse operations circuitry 358 comprises a plurality of pulse modification circuits 5080-508R-1 (R is an integer≥1 in general, and R=L/2 in the example shown); the pulse operations manager 356 comprises control circuitry 502, routing circuitry 506, and a plurality of modification settings circuits 5040-504K-1; two of the pulsers 3020-302L-1 may generate two raw outbound pulses which are a phase-quadrature pulse pair; assuming CP1 and CP2 are a phase-quadrature pulse pair to be output; in this example, pulse operations circuitry 358 may process CP1 and CP2 by multiplying a vector representation of CP'1 and CP'2 by one or more 2 by 2 matrices to: (a) perform single-sideband-modulation, where ω is the frequency of the single side band modulation and TS is the time passed since the reference time (e.g. the beginning of a certain control protocol); (b) keep track of frame-of-reference rotations, where ϕ is the total phase that the frame of reference accumulated since the reference time; and/or (c) perform an IQ-mixer correction where C00, C01, C10, and C11 are the elements of a matrix that corrects for IQ-mixer imperfections; each modification settings circuit, 504k, contains registers that contain the matrix elements of three matrices: an IQ-mixer correction matrix Ck; a single sideband frequency modulation matrix Sk; and a frame rotation matrix Fk, which rotates the IQ axes around the axis perpendicular to the IQ plane (i.e. the z-axis if I and Q are the x-axis and y-axis); each pulse modification circuit 508r is operable to process two raw outbound pulses CP'2r and CP'2r+1; such processing may comprise adjusting a phase, frequency, and/or amplitude of the raw outbound pulses CP'2r and CP'2r+1; pulse modification settings output to pulse operations circuitry 358 are specifically tailored to each raw outbound pulse (e.g., to which quantum element 226 or 228 the pulse is destined, to which input port 221 of front-end circuitry 254 the pulse is destined, etc.) to be processed by pulse operations circuitry 358; each path a pulse may travel to the quantum processor 218 via frontend circuitry 254 may have particular characteristics (e.g., non-idealities of interconnect, mixers, switches, attenuators, amplifiers, and/or circuits along the paths) to be accounted for by the pulse modification operations; similarly, each quantum element 1220-122k may have a particular characteristics (e.g. resonance frequency, frame of reference, etc.); the routing circuitry 506 is operable to route modification settings from the modification settings circuits 5040 -504L-1 to the pulse operations circuit 358 and to the pulsers 3020-302L-1; the pulser 3021 may determine ops_slct1 based on the particular quantum element 122k and/or signal path to which the pulse is to be transmitted (e.g., the resonant frequency of the quantum element, frame of reference, and/or mixer correction); the determination of which quantum element and/or signal path to which a particular pulser 3021 is to send an outbound pulse at a particular time may be predetermined in the pulse generation program and quantum machine specification 206 or may be determined based on calculations performed by the pulser 3021 and/or others of the pulsers 3020-302L-1 during runtime; the digital signal IFI instructs the pulse operations manager 356 to update a frequency setting of the modification settings circuit 504k indicated by ops_slct1; ¶¶ [0072]-[0079] with FIGS.3 and 6A-B: the frequency generation circuitry is part of control circuitry 502 of pulse operations manager circuitry 356; each CORDIC circuit 602k is operable to compute cosine and sine of its input, θk, thus generating two signals cos(θk) and sin(θk); the phase generation circuitry 604 is operable to generate the CORD IC input parameters θ0-θk-1 based on: (a) the frequency setting signals IF0-IFL-1 from the pulsers 3020-302L-1; and (b) the contents, TS, of the timestamp register 606; the timestamp register 606 comprises circuitry (e.g., a counter incremented on each cycle of the clock signal clk1) operable to track the number of cycles of clk1 since a reference point in time (e.g., power up of the quantum controller 210, start of execution of set of instructions of a pulse generation program by the quantum controller 210, etc.); the phase generation circuitry 604 sets θ0=2πf0(TS)(dtclk1), where f0 is a frequency determined from the signal IF0, TS is the number of clock cycles counted from the reference point and dtclk1 is the duration of a single clock cycle of clk1; this leads to the CORD IC outputs being a pair of phase-quadrature reference signals, cos(2πf0(TS)(dtclk1)) and sin(2πf0(TS)(dtclk1)), as in the example shown, which are used to generate the S0 rotation matrix that rotates at a frequency f0; as shown in FIG. 6B, the signal IFI may comprise an update component and an fI component; when updateI is asserted then the phase generation circuitry updates one of more of f0-fk-1 to be the value of fI; the S-matrix generation circuitry 608 is operable to build the matrices S0-SK-1 from the outputs of the CORDIC circuits 6020-602K-1; the S-matrix generation circuit 608 is operable to synchronize changes to the S matrices such that any matrix update occurs on a desired cycle of clock clk1 (which may be determined by the control information IF0-IFL- 1); in instances that more than K frequencies are needed over the course of a set of instructions, the phase generation circuit 604 is operable to change the input parameter θk of one or more of the CORDIC circuits 6020-602K-1 to stop generating one frequency and start generating the K+1th frequency; it may be necessary for the new frequency to start at a phase θ that would have been the phase if the new frequency was being generated from the initial reference time (e.g., because the new frequency would be used to address a quantum element that has a resonance at the new frequency and that was coherent since the reference point); in some other instances, it might be necessary to start the new frequency from the phase that the old frequency ended in; ¶ [0105] with FIG. 2A: an element that a quantum machine may contain is a mixer of front-end circuitry 254; to correct for mixer imbalances, the in-phase/quadrature (10) waveforms of the pulse can be multiplied by a 2x2 mixer correction matrix before being sent to the output ports; this mixer correction matrix, determined via a calibration routine, may be frequency dependent; thus, a mixer definition may include the mixer's name and a list of one or more frequencies and the correction matrix to be used at each frequency; in one example implementation, the correction matrix is loaded into corresponding pulse modification circuit during compilation; similarly, an element definition may include an intermediate frequency with which every pulse sent to the element is to be modulated; ¶¶ [0107]-[0111] with FIGS. 2A and 10: a quantum control multi-tone generator (e.g., multi-tone generator 222) comprising oven-controlled crystal oscillator (OCXO) and signal processing circuitry 1002; the signal processing circuitry is operable to perform splitting, frequency multiplication, gain adjustment, filtering, and/or other signal processing operations to generate M+1 local oscillator signals 1003 from the OCXO output 1001; the signal 1001 is at frequency fi, ID is a multiple of fi, each of the signals 223 is at a multiple of ID, and each of k and M are integers; the use of multiple fixed-frequency tones, avoids the need for the voltage controlled oscillators and phase locked loops used in the signal generators conventionally used for driving quantum systems, which has the benefit of greatly reducing phase noise in the circuitry 222 (in general VCOs introduce additional phase noise as compared to OCXOs); the quantum control multi-tone generator 222 also comprises a variable frequency signal generator 1004 operable to output a signal 231 having a variable (i.e., tunable) frequency; the variable frequency generator 1004 may be driven by the same reference signal that is input to the OCXO 1000 (e.g., a 10 MHz signal) and/or may be driven by the signal 1001 output by OXCO 1000 (e.g., a 1000 MHz signal); the use of a single fundamental frequency, fi, which is then upconverted to the output frequencies using mixers, amplifiers, and bandpass filters provides positive phase correlation between the phase noises of the outputs; this generation of coherent tones through multiplication and filtering of a common reference signal may increase quantum gate fidelity in scenarios where multiple sequential single-gate operations are applied to qubits that are operating using different frequency tones, as well as two-qubit gate operations; the signal processing circuit 1002 performs fanout, frequency multiplication, amplification, and filtration functions; ¶¶ [0112]-[0141] with FIGS. 11A-D: a quantum control multi-tone generator in FIG. 11A including the OCXO 1000 and the circuit 1002 which outputs M multiples of the fi; each of the outputs of circuit 1002 is then input to circuitry comprising a PLL and DRO 1120 in a feedback arrangement to generate a signal 223; the DROs have the effect of lowering phase noise in the signals 223 at frequencies far from the carrier frequency; a quantum control multi-tone generator in FIG. 11B uses only a single DRO 1120 and PLL 1104; the outputs of circuit 1002 and the DRO 1120 feed a signal processing circuit 1122 which mixes the signals 11060-1106N-1 (N is an integer) to generate signals 2230-223M-1; which of the N+1 signals 11060-1106N-1 is selected as signal 1106q (q is an integer where 0≤q≤N-1) to be input to the PLL 1104 may be determined (e.g., preconfigured or controlled programmatically during operation via signal(s) 253, 255, 257, and/or 259) based on the desired frequencies of the signals 2230-223M; the number of signals 223 and/or the frequency spacing of the signals 223 may be determined based on the range of frequencies that the control circuitry 502 of quantum controller 210 is configured to generate; the circuit 1002 may comprise one or more frequency multiplier circuits 1052; each circuit 1150 comprises M, an integer, multiplier circuits 1052, each of which generates an output signal that is an integer multiple of its input signal (in addition to the frequency multiplication, each circuit 1052 may also perform filtering and/or other signal conditioning operations such as current and/or voltage amplification to make the output signal suitable for driving one or more of: another multiplication circuit 1052, a PLL such as 1104, mixer(s) of the circuit 1122, and/or one or more inputs of the circuit 224; the circuit 1122 may comprise one or more mixer circuits 1152; through setting (either at design time or in the field using jumpers, variable resistors, switches, etc.) the multiplication factors of each multiplier 1052, the number of circuits 1150, the number of circuits 1152, and/or the interconnection of the circuits 1150 and 1152, a wide range of frequencies and channel spacings can be achieved to support a wide range of quantum processors and a wide range of quantum controllers; e.g., the multipliers are configured and connected to achieve 24 output frequencies spaced at 4fi, as follows: (a) circuit 11500 outputs: (i) fi, which drives an output port of the multitone generator 222; (ii) 4fi, which drives the input of circuit 11501, and is the basis for the frequency spacing; and (iii) 10fi, which drives an output port of the multitone generator 222; (b) circuit 11501 outputs: (i) 4fi, which drives an input of each of circuits 11520 , 11521 , and 11522; (ii) 8fi, which drives an input of each of circuits 11520 , 11521 , and 11522; (iii) 12fi, which drives an input of each of circuits 11520 , 11521 , and 11522; and (iv) 16fi, which drives an input of circuit 11502; (c) circuit 11502 outputs: (i) 16fi, which drives an output port of the multitone generator 222; (ii) 32fi, which drives an input of circuit 11520; (iii) 48fi, which drives an input of circuit 11521; (iii) 64fi which drives an input of circuit 11522; and (iv) 80fi, which drives an output port of the multitone generator 222; (d)circuit 11520 receives 4fi, 8fi, 12fi, and 32fi and outputs 28fi, 36fi, 40fi, 24fi, 44fi, and 20fi; (e) circuit 11521 receives 4fi, 8fi, 12fi, and 48fi and outputs 52fi, 44fi, 56fi, 40fi, 60fi, and 36fi; and (f) circuit 11522 receives 4fi, 8fi, 12fi, and 64fi and outputs 68fi, 60fi, 72fi, 56fi, 76fi, and 52fi; the multi-tone generator is operable to generate a plurality of fixed-frequency signals from a single fixed-frequency reference signal (e.g., 2230 -2237), and output the plurality of fixed-frequency signals via a corresponding plurality of output ports (e.g., ports of 222); each of the plurality of fixed-frequency signals may be at a different one of a plurality of frequencies from a first frequency (e.g., 2.5 GHz) to a second frequency (e.g., 6 GHz); the frequency spacing between frequency-adjacent signals of the plurality of fixed-frequency signals may be less than or equal to a range of frequencies (e.g., a range of 500 MHz) at which the quantum control pulse generation circuitry is configured to generate a pulse signal (e.g., AO0) such that any frequency in the range from the first frequency to the second frequency for controlling quantum elements can be achieved through tuning of the pulse signal and mixing of the pulse signal with one of the plurality of fixed-frequency signals; the quantum control pulse generation circuit may be operable to generate baseband pulses, and upconvert the baseband pulses to an intermediate frequency to generate the quantum control pulses, wherein the intermediate frequency is tunable over a range at least as large as the first frequency spacing).
Szmuk in view of Negoro fails to explicitly disclose wherein the logic circuit acquires the frequency offset signal of the frequency of the selected quantum bit multiplied by a negative value.
Cohen'692 teaches a system and a method relating to frequency generation in a quantum controller (Cohen'692, ¶ [0003]), wherein the logic circuit acquires the frequency offset signal of the frequency of the selected quantum bit multiplied by a negative value (Cohen'692, ¶¶ [0071]-[0079] and [0094] with FIGS. 6A-B and 12A-B: the phase generation circuitry 604 can also generate CORDIC input parameters 80-8K-l that depend on time in a non-linear manner in order, for example, to generate an S-matrix that rotates at a frequency that increases or decreases in time (chirp); a chirp is a signal of the form s(t)=cos(ω(t)t), meaning that the frequency changes with time; a linear chirp can be written as ω(t)= ω0+at at for some constant a, so that s(t)=cos(ωt+at2); generate a signal having such a phase without having to do the whole multiplication every time; instead such systems can increment the phase every cycle; e.g., in the case of a signal with a fixed frequency (not a chirp), the phase is incremented by θinc=2πfk(dclk1) every clock cycle; the frequency can be provided by the pulser itself via the IFI signal along the chirp; in FIG. 6A, e.g., S0 could be chirped by pulser 3020 changing the frequency f0 on each clock cycle so that f=f0+(δf0)(TS-TSc); one advantage of this approach is that, because f0 is calculated by the pulser 3020 and pulser 3020 comprises circuitry for performing complex calculations, then complicated chirps such as nonlinear chirps ( chirps with different rates of frequency change), can be achieved; an example frequency generation circuitry operable to generate chirps; the signal IFI comprises two additional signals beyond those shown in FIG. 6B: (1) chirpl which indicates when a chirp is to start (e.g., is high during a chirp and low otherwise); and (2) δfl which indicates the rate of frequency change for the chirp (a positive value of δfk resulting in an upchrip and a negative value of δfk resulting in a down chirp); the phase generation circuitry 604 then generates θk=2πfk(dtclk1)+2π (δfk)(TS-TSkc)(TS)dtclk1, where TSkc is the clock cycle at which the chirp starts; when a chirp is not in progress (e.g., indicated by chirpk being low) then the second term in θk is 0, resulting in a constant frequency signal; θk may be fixed for each chirp; the phase generation circuitry 604 may reach δfk on each clock cycle for which chirp is high and thus the pulser that is generating δfk can manipulate δfk to achieve non-linear chirps).
Szmuk in view of Negoro, and Cohen'692 are analogous art because they are from the same field of endeavor, a system and a method relating to frequency generation in a quantum controller. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to apply the teaching of Cohen'692 to Szmuk in view of Negoro. Motivation for doing so would allow circuitry to be capable for performing complex calculations (Negoro.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Szmuk in view of Negoro as applied to Claim 2 above, and further in view of Herrmann et al. ("Frequency Up-Conversion Schemes for Controlling Superconducting Qubits", arXiv:2210.02513v1, Oct. 5, 2022), hereinafter Herrmann.
Claim 8
Szmuk in view of Negoro discloses all the elements as stated in Claim 2 and further discloses wherein the converter is an (Szmuk, ¶ [0049] with FIGS. 2A and 3: the transmit analog frontend 362 comprises circuitry operable to concurrently process up to K digital signals DOk to generate up to K concurrent analog signals AOk to be output to inputs 221 of the front-end circuitry 254; such processing may comprise, e.g., digital-to analog conversion, filtering, upconversion, downconversion, amplification, attenuation, time division multiplexing/demultiplexing, frequency division multiplexing/demultiplexing and/or the like; the transmit analog frontend 362 is operable to process digital signals DO0-DOK-1 as K independent outbound pulses, as K/2 two-pulse pairs, or process some of signals DO0-DOK-1 as independent outbound pulses and some signals DO0-DOK-1 as two-pulse pairs (at different times and/or concurrently))( Negoro, ¶ [0004] with FIG. 1: a digital-analog converter/analog-digital converter (DAC/ADC) 44 that performs conversion between an analog signal and a digital signal; ¶¶ [0033] and [0040]-[0041] with FIG. 3: Each of the signal processing units 140-i includes a logic device 310, a DAC/ADC module 330, and a radio-frequency (RF) circuit 350; the DAC/ADC module 330 includes a digital-analog converter (DAC) unit 332 and an analog-digital converter (ADC) unit 334; The DAC unit 332 generates an intermediate frequency (IF) signal from the baseband signal generated by the transmitting logic 316, performs digital-to-analog conversion on the IF signal, and outputs the resultant analog signal to the RF circuit 350; ¶¶ [0042]-[0046[ with FIG. 4A: FIG. 4A shows a partial circuit configuration within the DAC unit 332, which illustrates an example of the circuit that generates one IF signal from two baseband signals (hereinafter referred to as first and second baseband signals); the DAC unit 332 includes mixers 410, 420, and 440, a combiner 430, numerically controlled oscillators (NCOs) 412, 422, and 442 that are digital oscillators, and a DAC 450. The NCOs 412, 422, and 442 all generate digital oscillation signals in a given frequency band (e.g., 1 to 3 GHz) as carrier waves, with their oscillation frequencies being different from one another).
Szmuk in view of Negoro fails to explicitly disclose wherein the converter is an RFDAC.
Herrmann teaches a system and a method relating to control of superconducting qubits (Herrmann, Abstract), wherein the converter is an RFDAC (Herrmann, Abstract of Page 1: high-fidelity control of superconducting qubits requires the generation of microwave-frequency pulses precisely tailored on nanosecond timescales; these pulses are most commonly synthesized by up-converting and superimposing two narrow-band intermediate-frequency signals referred to as the in-phase (I) and quadrature (Q) components; while the calibration of their DC-offsets, relative amplitude and phase allows one to cancel unwanted sideband and carrier leakage, this IQ mixing approach suffers from the presence of additional spurious frequency components; study an alternative approach based on double frequency conversion, which overcomes this challenge and circumvents the need for IQ-calibration; we find a spurious-free dynamic range of more than 70 dB and compare the quality of pulse generation against a state-of-the-art IQ mixing scheme by performing repeated single-qubit randomized benchmarking on a superconducting qubit; Section I of Page 1: microwave pulse generation typically employs a radio frequency mixer to up-convert pulses generated by an arbitrary waveform generator (AWG) at an intermediate megahertz frequency to the typical gigahertz transition frequency range of the superconducting qubit [17]; compared to the direct digital synthesis (DDS) of control pulses [18, 19], frequency up-conversion allows for using AWGs with lower sampling rate, which relaxes resource requirements and thereby eases the scale-up to large channel numbers [20]; conventional frequency up-conversion schemes utilize an IQ mixer, which up-converts an in-phase and a quadrature component to destructively interfere unwanted sideband and carrier leakages, which can ultimately limit the achievable single-qubit gate fidelity; however, realistic IQ mixers require extensive calibration of the IQ components to achieve optimal performance, and the up-converted output spectrum exhibits additional spurious frequency components, which cannot be canceled by the interference mechanism; here, we control a superconducting qubit with an alternative microwave pulse generation scheme, which makes use of two frequency conversion stages and uses analog filters to remove the unwanted sideband and carrier leakages from the up-converted control pulse; we compare the signal quality of this double frequency conversion scheme to a conventional IQ mixing scheme, and find the output of the double-conversion stage to exhibit smaller spurious frequency components and to be less affected by variations in the ambient temperature; we also find a slight improvement in the single-qubit gate fidelity when using the double frequency conversion scheme to generate the control pulses; for our study, we use a high-density IQ converter (HDIQ) and a super-high-frequency signal generator (SHFSG) to investigate the two schemes; Section II with FIG. 1(a) of Pages 1-2: to generate the control pulse at frequency ω by upconversion, we multiply an intermediate frequency signal generated by an AWG with a local oscillator continuously running at frequency ωLO in the gigahertz range; the IF signal consists of the two independent pulse envelope functions
v
I
~
(
t
)
and
v
Q
~
(
t
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defined in software and modulated digitally at frequency ωIF; we multiply the IF signal with the LO using a radio frequency mixer resulting in an output spectrum S(ω) featuring two sidebands centered around the frequencies ωLO ± ωIF, see Fig. 1(a); we use the convention of driving the qubit with the upper sideband at frequency ω = ωLO + ωIF and consider the frequency component ωLO - ωIF the undesired image of the control pulse, which, when present in the spectrum of the qubit drive pulse, induces a gate error; Section III with FIGS. 1(b) and 2(a)-(d) of Pages 2-3: an established method to eliminate the image component is IQ mixing [17, 22], as shown in Fig. 1(b); here, two parallel up-conversion paths, for two IF signal waveforms
v
I
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(
t
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and
v
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(
t
)
, are equipped with radio frequency (RF) mixers which share a local oscillator signal through a hybrid splitter which adds a 90º-phase shift to the signal driving the Q port mixer; the signals from the two parallel mixing paths are superimposed in a microwave combiner, where ideally one of the two up-converted sidebands is canceled out by destructive interference; under realistic conditions, however, the implementation of an IQ mixer is subject to imperfections, such as amplitude and phase imbalances between the two parallel mixing paths [17, 23]; these imperfections result in an up-converted spectrum that exhibits unwanted sideband and carrier leakage, which we compensate for by calibrating the relative phase, amplitude and DC offsets of the IF signals; second, imbalances in the relative amplitude and phase between the two parallel mixing paths modeled by the scaling factor
α
~
∙
e
i
ϕ
~
can result in an imperfect destructive interference of the image component at frequency ωIM = ωLO - ωIF, such that the residual amplitude of the image signal is shown in Eq. (4); we compensate for this imperfection by modifying the IF signals vI(t) = cos(ωIFt) and vQ = sin(ωIFt) to v'I(t) = cos(ωIFt) and v'Q(t) = α-1 sin(ωIFt-ϕ) where α and ϕ are the compensation parameters [17, 24] resulting in a total image amplitude YIM (Eq. (5)) at the output of the mixer, which vanishes for
α
~
α
=
1
and
ϕ
-
ϕ
~
=
2
π
n
with n [Symbol font/0xCE]
N
; to find the optimal compensation parameters, we measure the amplitude YIM for varying α and ϕ, see Fig. 2(c), and fit Eq. (5) to the measured data set similarly as in the calibration procedure of the carrier leakage, see Fig. 2(d); Section IV of Pages 3-4 with FIG. 1(c) in Pages 3-4: an alternative approach to cancel the image component uses analog filtering instead of destructive interference; an implementation that overcomes these technical challenges uses a double frequency conversion scheme [25], which makes use of two separate mixing stages fed by two different local oscillators, see Fig. 1(c); by keeping the frequency of the first LO fixed and having the second LO tunable, a bandpass filter with a fixed center frequency can be used to effectively eliminate sideband and carrier leakage; to generate the qubit control signal, we digitally define the control pulse at an intermediate frequency of fIF1 = 1.5 to 2:5 GHz, see Fig. 1(c); for that purpose, we employ an RF digital-to-analog converter (RFDAC) with a sampling rate of fS = 6 GSa/s resulting in a first Nyquist frequency of fS/2 = 3 GHz; we use a subsequent 2.5 GHz low-pass filter to remove the alias spectra which arise from defining the signal with the RFDAC, and we up-convert the filtered signal with a fixed-frequency LO, which is continuously running at fLO1 = 10 GHz, see spectrum S1(f) in Fig. 1(c); we remove the emerging image component at the frequency fLO1-fIF1 using an analog bandpass filter with a pass-band frequency of approximately 12 GHz±500MHz; then, we down-convert the filtered signal using a second LO with an adjustable frequency range of fLO2 = 13 to 20 GHz; the image component emerging in the down-converted spectrum ranges from 24:5 to 32:5GHz and is thus far detuned from the targeted frequency band of 0:5 to 8:5 GHz, see spectrum S2(f) in Fig. 1(c); due to the large detuning, we can use a subsequent low-pass filter to suppress unwanted image components in the qubit control pulse spectrum; we note that the up-converted spectrum of the qubit control signal is mirrored compared to the spectrum of the initial IF signal since the final down-conversion uses an LO which is higher in frequency than the signal in the previous stage, see also the sketch of the spectrum S2(f) in Fig. 1(c); we correct for this effect in software by inverting the sign of the IF frequency fIF1 prior to the digital up-conversion before the RFDAC).
Szmuk in view of Negoro, and Herrmann are analogous art because they are from the same field of endeavor, a system and a method relating to control of superconducting qubits. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to apply the teaching of Herrmann to Szmuk in view of Negoro. Motivation for doing so would (1) eliminate.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Singhal et al. ("SQ-CARS: A Scalable Quantum Control and Readout System", arXiv:2203.01523v2, Apr 18, 2023) discloses in Abstract of Page 1 that (1) we use the evaluation kit ZCU111 to develop a scalable, configurable and phase synchronized system for multi-qubit control and readout; (2) the scalability to a larger number of qubits is realized by synchronizing multiple channels deterministically; (3) all the control and readout features are supported using a python based user interface; (4) this system can synthesize arbitrary vector microwave pulses using the second-Nyquist zone technique for frequencies in the range of 4-6 GHz; (5) it also supports low pass filters of tunable cutoff frequencies and rotation blocks which can be utilized to perform lock-in detection and provide active feedback; and (6) we further perform various time-domain measurements to characterize a superconducting transmon qubit and benchmark our results against traditionally used setups. Singhal further disclose in Section I of Pages 2-4 that (1) this work utilizes a single FPGA board (ZCU111 by Xilinx) that is populated with the XCZU28DR device to develop an integrated framework to support a scalable Quantum Control system; (2) the proposed framework, Scalable Quantum Control and Readout System (SQ-CARS) supports up to four qubits and can be easily scaled to control higher number of qubits; and (3) the main contributions of this work are: (a) phase synchronization of all channels using Multi-Tile Synchronization; (b) direct digital synthesis of microwave pulses using Mix mode technique; (c) arbitrary waveform generation and lock-in detection to microwave quadrature; and (d) a python based programming interface to configure and control the above functionalities. Singhal also discloses in Section II with FIGS. 2-3 of Pages 4-11 that (1) the control side of superconducting quantum system involves generation of microwave pulses of various shapes and duration depending on the experiment at hand. DACs of this board are packaged into 2 tiles (Tile-0 and Tile-1), each tile containing 4 DACs, thus providing total 8 channels; (2) Tile-0 Channels are used to generate control microwave pulses, while Tile-1 DACs are used to generate corresponding readout pulses; (3) Tile-1 DACs can also be used independently to generate control pulses, extending the design's capability to control up to 8-qubits; (4) each of the DACs can be controlled independently by the Arbitrary Wave Generator (AWG) block which is shown in Figure 2; (5) the parameters that control the shape, amplitude, duration etc. of the microwave signals are controlled by this block; (6) the mode allows to play continuous waveform or a fixed number of pulses depending on the experiment requirement, thus catering to a wide spectrum of quantum experiments; (7) the loop parameters help to run an experiment multiple times repeatedly to collect as many measurements as required; (8) the Controller also controls the generation of a trigger which facilitates for the timely capture on the readout side; (9) the timing parameters decide the delay of the trigger and width of the arbitrary wave pulses which are fully programmable; (10) the sample data read from BRAM is sent to Data Splitter and the amplitude of each sample is scaled by the Scaler block. These scaled samples are further merged and the interleaved I and Q samples are fed to the RF-DAC; (11) the Channel Select allows us to select whether control or readout pulses be played through DACs; (12) the RF-DAC consists of a First In First Out (FIFO), an interpolation filter, a mixer, and a DAC as shown in Figure 1; (13) the scaled sample values from the Arbitrary Wave Generator are fed into AXI Stream (AXIS) FIFO of the corresponding DAC channel; (14) at higher sampling rates of Data Converters, the data streaming clock of the DAC cannot be pushed in the orders of their sampling rates; (15) do a digital upsampling is necessary; (16) this function on the DAC side is realized by the Interpolation Filters. The interpolation rate can be chosen among 1x, 2x, 4x, and 8x; (17) the RFSoC supports two modes of operation: Normal mode or Non-Return-to-Zero (NRZ) mode and Mix mode or Return-to-Complement (RTC) mode which determines R(ω); (18) the major advantage of this approach is that RF signal is generated using NCO and a digital IQ-mixer, therefore, it allows a full vector control of amplitude and phase; (19) to control and measure multiple qubits, the output waveforms of multiple ADC and DAC channels requires to be synchronized both in time and phase; and (20) the RF-ADC and RF-DAC constitute dual clock FIFOs.
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/HWEI-MIN LU/Primary Examiner, Art Unit 2142
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