DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-23 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Applicant has amendment the claims to overcome the previous rejection. As a result, further search was conducted and the claims are rejected over new prior art. Claims 1, 19 & 21-23 are rejected, claims 2-9 & 20 are objected to and claims 10-18 are allowable.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claim 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Upadhyaya (US 2021/0408911).
With regard to claim 1, Upadhyaya, in Figure 5, discloses a circuit, comprising: a power stage (50, paragraph 0037) including: switching circuitry (Power Switches) having a control input (PMWx) and a switching output (SW); and fault detection circuitry (66) having a detection input (58) and a reference input (65), in which the detection input is coupled to the switching output (through voltage divider R2 & R3) and the reference input is coupled to a reference voltage terminal (THD), the fault detection circuitry configurable to output a signal (68) indicative of whether a fault condition is detected responsive to a comparison between a voltage of the switching output and a reference voltage (paragraph 0043).
Claims 19, 21 & 22 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shao (US 2023/0299687).
With regard to claims 19, 21 & 22, Shao, in Figure 8, discloses a circuit comprising: a trans-inductor voltage regulator (800, paragraph 0039) including a power stage (40-1), the power stage including switching circuitry (MH1 & ML1) having a switching output (common node between the two switches); and fault detection circuitry (ICS1 & 16-1) coupled to the switching output and configurable to detect an open in a secondary side of the trans-inductor voltage regulator, and provide a signal indicative of whether the open is detected (paragraph 0040 & 0041) (re claim 19), wherein the power stage is a first instance of the power stage (40-1), the switching output is a first switching output, the first instance of the power stage is configurable to provide a first phase voltage at the first switching output responsive to a the first control signal, and the circuit further comprises :a second instance of the power stage (40-2) configurable to provide a second phase voltage at a second switching output responsive to a second control signal; a first transformer (T-1) having respective primary and secondary windings, in which the primary winding of the first transformer is coupled between the first switching output and an output terminal (Vo); and a second transformer (T-2) having respective primary and secondary windings, in which the primary winding of the second transformer is coupled between the second switching output and the output terminal (Vo), wherein the secondary windings of the first and second transformers are coupled in series with a compensation inductor (Lc) to form a compensation path (paragraph 0039), and the open in the secondary side includes an open in the compensation path; and a controller (14) configurable to provide the first and second control signals to regulate a voltage at the output terminal based on the first and second phase voltages (re claim 21), wherein: the first instance of the power stage includes a first current sense circuit (ICS1) configured to provide a first current sense signal at a first report output thereof representative of a measure of current through the primary winding of the first transformer, the second instance of the power stage includes a second current sense circuit (ICS2) configured to provide a second current sense signal at a second report output thereof representative of a measure of current through the primary winding of the second transformer, and the controller includes first and second sense terminals (positive terminals of comparators 16-1 & 16-2), in which the first sense terminal coupled to the report output of the first instance of the power stage, the second sense terminal is coupled to a report output of the second instance of the power stage, and the controller is configured to: detect the open in the compensation path or determine the measure of current through the primary winding of the first transformer responsive to on a first signal at the first sense terminal; and detect the open in the compensation path or determine the measure of current through the primary winding of the second transformer responsive to a second signal at the second sense terminal (paragraphs 0039 & 0040) (re claim 22).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 23 is rejected under 35 U.S.C. 103 as being unpatentable over Shao in view of Hebert (US 2017/0053904).
With regard to claim 23, Shao teaches the circuit of claim 19.
Shao does not teach an integrated circuit that includes the power stage (paragraph 0015) encapsulated in a molding compound (112, paragraph 0025).
Hebert, in Figure 1, teaches a power stage (104) formed as an integrated circuit encapsulated in a molding compound.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Shao with Hebert, by forming the circuit of Shao as an IC in a molding compound, for the purpose of allowing the device to have a small size that is easily mountable to a circuit board.
Allowable Subject Matter
Claims 2-9 & 20 would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 2 would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because the prior art of record does not teach or fairly suggest a circuit comprising all the features as recited in the claims and in combination with a logic circuitry having first and second logic inputs and a logic output, in which the first logic input is coupled to the comparator output, the second logic input coupled to the control input, and the logic output is coupled to a report terminal, the logic circuitry configurable to provide the signal at the report terminal.
Claim 3 would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because it depends on claim 2 which would also be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 4 would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because the prior art of record does not teach or fairly suggest a circuit comprising all the features as recited in the claims and in combination with the signal being a first signal, the fault detection circuitry includes detection logic having a detection control input, a detection control output and a report terminal, the detection control input is coupled to the control input, and the detection logic is configurable to enable the fault detection circuitry to provide the signal at the report terminal responsive to a second signal at the detection control input.
Claim 5 would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because it depends on claim 4 which would also be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 6 would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because the prior art of record does not teach or fairly suggest a circuit comprising all the features as recited in the claims and in combination with a second power stage, the second power stage including: second switching circuitry having a second control input and a second switching output; and second open fault detection circuitry having third and fourth inputs, in which the third input is coupled to the second switching output and the fourth input is coupled to the reference voltage terminal, the second fault detection circuitry configurable to output a second signal indicative of whether the fault condition is detected responsive to a comparison between a voltage at the second switching output and the reference voltage; and wherein the circuit further comprises further comprising a controller having first and second control outputs and first and second sense terminals, in which the first control output is coupled to the first control input, the second control output is coupled to the second control input, the first sense terminal is coupled to a first report output of the first power stage, and the second sense terminal is coupled to a second report output of the second power stage.
Claims 7-9 would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because they depend on claim 6 which would also be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 20 would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because the prior art of record does not teach or fairly suggest a circuit comprising all the features as recited in the claims and in combination with the fault detection circuitry being enabled to provide the signal responsive to the modulated signal having a first state to disable one of the first or second switches, and disabled from providing the signal responsive to the modulated signal having a second state that enables the one of the first or second switches.
Claims 10-18 are allowable.
Claim 10 is allowable because the prior art of record does not teach or fairly suggest a multiphase power converter circuit comprising all the features as recited in the claims and in combination with the first power stage including first fault detection circuitry configurable to enable at least one of detection or reporting of a fault condition responsive to the first control signal having a state to disable a first switch of the first power stage; and a second power stage configurable to provide a second phase output signal at a second switching output responsive to a second control signal, the second power stage including second open fault detection circuitry configurable to enable at least one of detection or reporting of the fault condition responsive to the second control signal having a state to disable a second switch of the second power stage.
Claims 11-18 are allowable as they depend from claim 10, which is also allowable.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SCOTT BAUER whose telephone number is (571)272-5986. The examiner can normally be reached M-F 12pm - 8pm EST.
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/Scott Bauer/Primary Examiner, Art Unit 2838
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