CTNF 18/585,945 CTNF 81254 DETAILED ACTION General Remarks 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. When responding to this office action, applicants are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs. Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification. For Examiner’s Interview fill out the online Automated Interview Request (AIR) form (http://www.uspto.gov/patent/uspto-automated-interview-request-air-form.html). Status of claim(s) to be treated in this office action: Independent: 1, 11 and 20. Pending: 1-20. Information Disclosure Statement Applicant’s IDS(s) submitted on 2/23/2024 is/are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement has/have considered by the examiner and made of record. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.— The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. 07-34-01 AIA Claim 17-18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. Dependent Claim 17 (and dependent claim(s) 18), recite(s) the limitation " the second front insulating film region " in Claim 17, lines 1-2. There is insufficient antecedent basis for this limitation in the claim. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. 07-12-aia AIA (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 07-15-aia AIA Claim(s) 1-7, 10-16 and 20 is/are rejected under 35 U.S.C. 102 (a)(1) and 35 U.S.C. 102(a)(2) as being anticipated by Hwang et al., US PG pub. 20200135699 A1 . Re: Independent Claim 1, Hwang discloses a buffer die (210, fig. 3 and fig. 5); an intermediate core die (100A,100B,100C, fig. 3) stack stacked on the buffer die (210, fig. 3 and fig. 5), the intermediate core die (100A,100B,100C, fig. 3) stack including a plurality of intermediate core dies (100A,100B,100C, fig. 3) and a first gap filling portion (180 portion next to region 100A-100C, fig. 3) covering outer surfaces of the plurality of intermediate core dies (100A,100B,100C, fig. 3); and a top core die (110D, fig. 3) stack stacked on the intermediate core die (100A,100B,100C, fig. 3) stack, the top core die (110D, fig. 3) stack including a top core die (110D, fig. 3) and a second gap filling portion (180 portion next to region 100D, fig. 3) covering an outer surface of the top core die (110D, fig. 3), wherein the first gap filling portion (180 portion next to region 100A-100C, fig. 3) and the second gap filling portion (180 portion next to region 100D, fig. 3) are directly bonded to each other. Re: Claim 2, Hwang disclose(s) all the limitations of claim 1 on which this claim depends. Hwang further discloses: wherein each of the intermediate core dies (100A,100B,100C, fig. 3) includes, a substrate (110 in chip 100A, 100B, 100C, fig. 3); a front insulating layer (120, fig. 4) provided on a front surface of the substrate (110 in chip 100A, 100B, 100C, fig. 3); a first bonding pad (140, fig. 3) formed in the front insulating layer (120, fig. 4); and a backside insulating layer (162 and 164, fig. 3) provided on a backside surface of the substrate (110 in chip 100A, 100B, 100C, fig. 3); and a second bonding pad (152 and 154, fig. 3) formed in the backside insulating layer (162 and 164, fig. 3). Re: Claim 3, Hwang disclose(s) all the limitations of claim 2 on which this claim depends. Hwang further discloses: wherein the backside insulating layer (162 and 164, fig. 3) of a first intermediate core die (100A, fig. 3) among the plurality of intermediate core dies (100A,100B,100C, fig. 3) and the front insulating layer (120, fig. 4) of a second intermediate core die (100B, fig. 3) stacked on the first intermediate core die (100A, fig. 3) are directly bonded to each other, and wherein the second bonding pad (152 and 154, fig. 3) of the first intermediate core die (100A, fig. 3) and the first bonding pad (140, fig. 3) of the second intermediate core die (100B, fig. 3) are directly bonded to each other. Re: Claim 4, Hwang disclose(s) all the limitations of claim 2 on which this claim depends. Hwang further discloses: wherein the front insulating layer (120, fig. 4) and the backside insulating layer (162 and 164, fig. 3) include silicon oxide, silicon nitride, or silicon carbonitride (¶0028). Re: Claim 5, Hwang disclose(s) all the limitations of claim 2 on which this claim depends. Hwang further discloses: wherein each of the intermediate core dies (100A,100B,100C, fig. 3) further includes a through electrode (130, fig. 3) that penetrates the substrate (110 in chip 100A, 100B, 100C, fig. 3) and is electrically connected to the first and second bonding pads (140, 152 and 154, fig. 3). Re: Claim 6, Hwang disclose(s) all the limitations of claim 1 on which this claim depends. Hwang further discloses: wherein the first gap filling portion (180 portion next to region 100A-100C, fig. 3) includes an inorganic dielectric or an organic dielectric. Re: Claim 7, Hwang disclose(s) all the limitations of claim 1 on which this claim depends. Hwang further discloses: wherein the top core die (110D, fig. 3) includes a first substrate region (110 region in chip 100D, fig. 3) and a first front insulating layer (120, fig. 4) region provided on the first substrate region (110 region in chip 100D, fig. 3) , and the second gap filling portion (180 portion next to region 100D, fig. 3) includes a second substrate region (110 in chip 100C, fig. 3) surrounding the first substrate region (110 region in chip 100D, fig. 3) and a second front insulating layer (120, fig. 4) region provided on the second substrate region (110 in chip 100C, fig. 3) and surrounding the first front insulating layer (120, fig. 4) region. Re: Claim 10, Hwang disclose(s) all the limitations of claim 1 on which this claim depends. Hwang further discloses: wherein the second gap filling portion (180 portion next to region 100D, fig. 3) includes an inorganic dielectric or an organic dielectric. Re: Independent Claim 11, Hwang discloses a buffer die (210, fig. 3 and fig. 5); an intermediate core die (100A,100B,100C, fig. 3) stack stacked on the buffer die (210, fig. 3 and fig. 5), the intermediate core die (100A,100B,100C, fig. 3) stack including a plurality of intermediate core dies (100A,100B,100C, fig. 3) and a gap filling portion (180 portion next to region 100A-100C, fig. 3) covering outer surfaces of the plurality of intermediate core dies (100A,100B,100C, fig. 3); and a top core die (110D, fig. 3) stack stacked on the intermediate core die (100A,100B,100C, fig. 3) stack, the top core die (110D, fig. 3) stack including a top core die (110D, fig. 3) and a flexibility compensating portion covering an outer surface of the top core die (110D, fig. 3), wherein each of the plurality of intermediate core dies (100A,100B,100C, fig. 3) includes a substrate (110 in chip 100A, 100B, 100C, fig. 3), a front insulating layer (120, fig. 4) provided on a front surface of the substrate (110 in chip 100A, 100B, 100C, fig. 3), a first bonding pad (140, fig. 3) provided in the front insulating layer (120, fig. 4), a backside insulating layer (162 and 164, fig. 3) provided on a backside surface of the substrate (110 in chip 100A, 100B, 100C, fig. 3), and a second bonding pad (152 and 154, fig. 3) provided in the backside insulating layer (162 and 164, fig. 3), and wherein the gap filling portion (180 portion next to region 100A-100C, fig. 3) and the flexibility compensating portion are directly bonded to each other. Re: Claim 12, Hwang disclose(s) all the limitations of claim 11 on which this claim depends. Hwang further discloses: wherein the backside surface of the substrate (110 in chip 100A, 100B, 100C, fig. 3) of a first intermediate core die (100A, fig. 3) among the plurality of intermediate core dies (100A,100B,100C, fig. 3) and the front surface of the substrate (110 in chip 100A, 100B, 100C, fig. 3) of a second intermediate core die (100B, fig. 3) are arranged to face each other. Re: Claim 13, Hwang disclose(s) all the limitations of claim 12 on which this claim depends. Hwang further discloses: wherein the backside insulating layer (162 and 164, fig. 3) of the first intermediate core die (100A, fig. 3) and the front insulating layer (120, fig. 4) of the second intermediate core die (100B, fig. 3) are directly bonded to each other, and wherein the second bonding pad (152 and 154, fig. 3) of the first intermediate core die (100A, fig. 3) and the first bonding pad (140, fig. 3) of the second intermediate core die (100B, fig. 3) are directly bonded to each other. Re: Claim 14, Hwang disclose(s) all the limitations of claim 11 on which this claim depends. Hwang further discloses: wherein the front insulating layer (120, fig. 4) and the backside insulating layer (162 and 164, fig. 3) include silicon oxide, silicon nitride, or silicon carbonitride (¶0028). Re: Claim 15, Hwang disclose(s) all the limitations of claim 11 on which this claim depends. Hwang further discloses: wherein the first and second bonding pads (140, 152 and 154, fig. 3) include copper (¶0026). Re: Claim 16, Hwang disclose(s) all the limitations of claim 11 on which this claim depends. Hwang further discloses: wherein the top core die (110D, fig. 3) includes a first substrate region (110 region in chip 100D, fig. 3) and a first front insulating layer (120, fig. 4) region provided on the first substrate region (110 region in chip 100D, fig. 3) , and the flexibility compensating portion includes a second substrate region (110 in chip 100C, fig. 3) surrounding the first substrate region (110 region in chip 100D, fig. 3) and a second front insulating layer (120, fig. 4) region provided on the second substrate region (110 in chip 100C, fig. 3) and surrounding the first front insulating layer (120, fig. 4) region. Re: Independent Claim 20, Hwang discloses a buffer die (210, fig. 3 and fig. 5); an intermediate core die (100A,100B,100C, fig. 3) stack stacked on the buffer die (210, fig. 3 and fig. 5); and a top core die (110D, fig. 3) stack stacked on the intermediate core die (100A,100B,100C, fig. 3) stack, wherein the intermediate core die (100A,100B,100C, fig. 3) stack includes a plurality of intermediate core dies (100A,100B,100C, fig. 3) stacked on one another and a gap filling portion (180 portion next to region 100A-100C, fig. 3) covering outer surfaces of the intermediate core dies (100A,100B,100C, fig. 3), wherein the top core die (110D, fig. 3) stack includes a top core die (110D, fig. 3) and a flexibility compensating portion covering an outer surface of the top core die (110D, fig. 3), wherein each of the plurality of intermediate core dies (100A,100B,100C, fig. 3) includes, a substrate (110 in chip 100A, 100B, 100C, fig. 3); a front insulating layer (120, fig. 4) provided on a front surface of the substrate (110 in chip 100A, 100B, 100C, fig. 3); a first bonding pad (140, fig. 3) provided in the front insulating layer (120, fig. 4); a backside insulating layer (162 and 164, fig. 3) provided on a backside surface of the substrate (110 in chip 100A, 100B, 100C, fig. 3); and a second bonding pad (152 and 154, fig. 3) provided in the backside insulating layer (162 and 164, fig. 3). Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 8 and 17 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Hwang et al., US PG pub. 20200135699 A1. Re: Claim 8, Hwang discloses all the limitations of claim 7 on which this claim depends. Hwang further discloses: wherein the second front insulating film/layer (120, fig. 4) region is directly bonded to the first gap filling portion (180 portion next to region 100A-100C, fig. 3). Hwang figure 4 is silent regarding: a bonding interface layer is formed between insulating layer and gap filling portion. Hwang figure 8 teaches a bonding interface layer (164D) between the gap filling portion (180 portion next to region 100A-100C, fig. 3) and front insulating layer (120). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include bonding layer between gap filling and insulating layer thereby increase the bonding strength between the chip layers. Re: Claim 17, Hwang discloses all the limitations of claim 16 on which this claim depends. Hwang further discloses: wherein the second front insulating film/layer (120, fig. 4) region is directly bonded to the first gap filling portion (180 portion next to region 100A-100C, fig. 3). Hwang figure 4 is silent regarding: a bonding interface layer is formed between insulating layer and gap filling portion. Hwang figure 8 teaches a bonding interface layer (164D) between the gap filling portion (180 portion next to region 100A-100C, fig. 3) and front insulating layer (120). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include bonding layer between gap filling and insulating layer thereby increase the bonding strength between the chip layers. Claim(s) 9 and 18 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Hwang et al., US PG pub. 20200135699 A1; in view of Sun et al., US PG pub. 20230361068 A1. Re: Claim 9, Hwang discloses all the limitations of claim 8 on which this claim depends. Hwang is silent regarding: wherein the bonding interface layer (164D, fig. 8) has a thickness in a range of 2 Å to 500 Å. Sun teaches the bonding interface layer 104 between gap filling layer 102 and insulating layer 92 as shown in figure 9-10 (¶0048). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include bonding layer that has a small thickness for example about 30 Å to about 200 Å since this can miniaturize the device. Re: Claim 18, Hwang discloses all the limitations of claim 17 on which this claim depends. Hwang is silent regarding: wherein the bonding interface layer has a thickness in a range of 2 Å to 500 Å. Sun teaches the bonding interface layer 104 between gap filling layer 102 and insulating layer 92 as shown in figure 9-10 (¶0048). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include bonding layer that has a small thickness for example about 30 Å to about 200 Å since this can miniaturize the device. Claim(s) 19 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Hwang et al., US PG pub. 20200135699 A1; in view of Jee et al., US PG pub. 20230074933 A1. Re: Claim 19, Hwang discloses all the limitations of claim 11 on which this claim depends. Hwang is silent regarding: wherein a thickness of the top core die (110D, fig. 3) is in a range of 100 μm to 300 μm, and a thickness of each of the intermediate core dies (100A,100B,100C, fig. 3) is in a range of 20 μm to 50 μm. Jee discloses a thickness of top core die (200H and 400, fig. 1A) can be in a range of 100 μm to 300 μm (H2 and H3 thickness ¶0038 and ¶0049), and a thickness of each of the intermediate core dies (200, fig. 1A) is in a range of 20 μm to 50 μm (¶0038). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include a thicker top core die than each of the intermediate core dies since the thicker thickness of the top core die can protect any external damage from the inner intermediate core dies. * Prior art made of record and not relied upon are considered pertinent to current application disclosure. *(“Suh et al., US Patent 11508685 B2”) discloses a semiconductor package includes a substrate, a first semiconductor chip disposed on the substrate, and a second semiconductor chip disposed on a top surface of the first semiconductor chip. The first semiconductor chip includes a conductive pattern disposed on the top surface of the first semiconductor chip and a first protective layer covering the top surface of the first semiconductor chip and at least partially surrounds the conductive pattern. The second semiconductor chip includes a first pad that contacts a first through electrode on a bottom surface of the second semiconductor chip. A second protective layer surrounds the first pad and covers the bottom surface of the second semiconductor chip. A third protection layer fills a first recess defined in the second protective layer to face the inside of the second protective layer. The first protective layer and the third protective layer contact each other. *(“Yoshida et al., US PG pub. 20110147945 A1”) discloses a semiconductor device includes a chip stacked body where a plurality of semiconductor chips are stacked, and penetration electrodes respectively formed in the semiconductor chips are electrically interconnected in stacking order of the semiconductor chips, a first support member that is disposed to face a first semiconductor chip formed in one end of the chip stacked body, and including electrodes electrically connected to the penetration electrodes of the first semiconductor chip, and a wiring board that is disposed to face a second semiconductor chip formed in an end opposed to the one end of the chip stacked body, and including external electrodes on a surface opposed to a surface facing the second semiconductor chip that is to be electrically connected to the penetration electrodes of the second semiconductor chip. *(“Min et al., US PG pub. 20150048493 A1”) discloses a semiconductor package includes a circuit substrate, a plurality of semiconductor chips stacked on the circuit substrate, insulating adhesive patterns interposed between the semiconductor chips, a heat slug provided on an uppermost semiconductor chip and adhered to the uppermost semiconductor chip by a heat dissipative adhesive pattern, and a mold structure provided on the circuit substrate to cover sidewalls of the semiconductor chips, the insulating adhesive patterns, the heat dissipative adhesive pattern and the heat slug. A failure of the semiconductor package during a manufacturing process of the mold structure may be reduced. The semiconductor package may therefore have good operating characteristics and reliability. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to TSZ CHIU whose telephone number is 571-272-8656. The examiner can normally be reached on M-F, 9:00AM to 5:00PM (EST). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at https://www.uspto.gov/patent/uspto-automated-interview-request-air-form.html. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Leonard Chang can be reached on 571-270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /TSZ K CHIU/Examiner, Art Unit 2898 Tsz.Chiu@uspto.gov /Leonard Chang/Supervisory Patent Examiner, Art Unit 2898 Application/Control Number: 18/585,945 Page 2 Art Unit: 2898 Application/Control Number: 18/585,945 Page 3 Art Unit: 2898 Application/Control Number: 18/585,945 Page 4 Art Unit: 2898 Application/Control Number: 18/585,945 Page 5 Art Unit: 2898 Application/Control Number: 18/585,945 Page 6 Art Unit: 2898 Application/Control Number: 18/585,945 Page 7 Art Unit: 2898 Application/Control Number: 18/585,945 Page 8 Art Unit: 2898 Application/Control Number: 18/585,945 Page 9 Art Unit: 2898 Application/Control Number: 18/585,945 Page 10 Art Unit: 2898 Application/Control Number: 18/585,945 Page 11 Art Unit: 2898 Application/Control Number: 18/585,945 Page 12 Art Unit: 2898 Application/Control Number: 18/585,945 Page 13 Art Unit: 2898 Application/Control Number: 18/585,945 Page 14 Art Unit: 2898
Prosecution Insights