DETAILED ACTION
The office action is in response to original application filed on 11-14-25. Claims 1-19 are pending in the application and have been examined.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-19 are rejected under 35 U.S.C. 103 (a) as being unpatentable over US 10,153,710 to Barbosa et al. (“Barbosa”) in view of US 8,680,830 to Kudo et al. (“Kudo”).
Regarding claim 1, Barbosa disclose a load sharing control method (figs. 1-6) comprising: generating a first control signal (Col. 4, lines 8-10, The control circuit 160 is electrically coupled to the power modules Ma, Mb, and Mc, and configured to output driving signals DSl a, DSl b, DSl c) which controls an output current (Col. 4, lines 4-6, output corresponding output currents Io a, lob, loc via the DC-DC converters 140a, 140b, 140c, in order to supply the load) of a power supply device (modules Ma, Mb, and Mc and a control circuit 160), by using the output current of the power supply device and a current of a load share bus (Col. 8, lines 9-13, the control circuit 160 is configured to calculate the output current reference value Iodc_la base on a difference of the DC supply voltage Vo and the DC supply voltage reference value Vo_ref.); and generating a second control signal (Col. 8, feed-forward current adjustment signal Iadj_la and the output current reference value Iodc_la) which controls an output voltage of the power supply device (Col. 1, lines 60-64, The first converter is configured to convert the corresponding phase input voltage into an intermediate bus voltage. The second converter is configured to output a DC supply voltage according to the intermediate bus voltage), by using a target voltage (Col. 4, lines 55-56, a target value for the intermediate bus voltage Vbusa) of the power supply deviceand a control voltage (Col. 4, DC-DC converters 140a, 140b, 140c are configured to output the DC supply voltage Vo according to the intermediate bus voltages Vbusa, Vbusb, Vbusc) according to the first control signal, wherein the step of generating the first control signal comprises generating the first control signal so that the output current is identical to the current of the load share bus, and limiting the output current to a threshold current (Col. 6, lines 17-20, control circuit 160 is configured to amplify the difference between the adjusted output current reference value Ioref_a and the output current Ioa by a current gain Gide to obtain a current error amplification signal) or less.
But, Barbosa does not disclose a feedback voltage received as feedback from the output voltage of the power supply device,
However, Kudo discloses a feedback voltage received as feedback from the output voltage of the power supply device (Col. 13, lines 21-26, output voltage of the output power supply node Vol is detected by the amplifier circuit AMP11 in the analog controller unit ACU. A difference between the result of detection (feedback signal FB1) and the output volt age set signal VR1 (e.g., IV or the like) is amplified by the error amplifier circuit EA1),
Therefore, it would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to modify Barbosa by adding feedback signal as part of its configuration as taught by Kudo, in order to either adds to the normal input or subtracts and correct the error amplifier circuit then power supply voltage of the load.
Regarding claim 2, Barbosa disclose the step of generating the first control signal (output driving signals DSl a, DSl b, DSl c) comprises: comparing the output current with the current of the load share bus (Col. 6, lines 8-12, the control circuit 160 is configured to accordingly sum up the feed-forward current adjustment signal Iadj_a and an output current reference value Iodc_a of the corresponding power module Ma to calculate an adjusted output current reference value Ioref_a); calculating a difference between the output current and the current of the load share bus (Col. 8, lines 5-8, the difference between the adjusted output current reference value Ioref_la and the output current Iola of the power supply unit PSUla); and generating the first control signal (driving signal DSl_la) according to the difference between the output current and the current of the load share bus.
Regarding claim 3, Barbosa disclose all the claim limitation as set forth in the rejection of claims above.
But, Barbosa does not disclose the step of generating the first control signal comprises generating the first control signal for controlling a level of the feedback voltage.
However, Kudo discloses the step of generating the first control signal comprises generating the first control signal for controlling a level of the feedback voltage (Col. 13, lines 21-26, output voltage of the output power supply node Vol is detected by the amplifier circuit AMP11 in the analog controller unit ACU. A difference between the result of detection (feedback signal FB1) and the output volt age set signal VR1 (e.g., IV or the like) is amplified by the error amplifier circuit EA1).
Therefore, it would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to modify Barbosa by adding feedback signal as part of its configuration as taught by Kudo, in order to either adds to the normal input or subtracts and correct the error amplifier circuit then power supply voltage of the load.
Regarding claim 4, Barbosa disclose the step of generating the first control signal (driving signal DSl_la) comprises comparing the output current and the threshold current (Col. 8, lines 5-8, the difference between the adjusted output current reference value Ioref_la and the output current Iola of the power supply unit PSUla).
Regarding claim 5, Barbosa disclose the step of generating the second control signal (Col. 8, feed-forward current adjustment signal Iadj_la and the output current reference value Iodc_la) comprises: and the control voltage according to the first control signal; and generating the second control signal (Col. 8, feed-forward current adjustment signal Iadj_la and the output current reference value Iodc_la),
But, Barbosa does not disclose calculating a difference between the feedback voltage and the control voltage according to the first control signal; calculating a difference between the target voltage and the difference between the feedback voltage for controlling the output voltage of the power supply device according to the difference between the target voltage and the difference between the feedback voltage and the control voltage according to the first control signal.
However, Kudo discloses calculating a difference between the feedback voltage and the control voltage (Col. 25, FIG. 2, and a value of an output voltage detection signal DFOl obtained by feeding back the power supply voltage of the load LOD. Thus, when the power supply voltage (DFOl) of the load LOD is made higher than the set value (VRl) by the predetermined voltage (VOFml)) according to the first control signal; calculating a difference between the target voltage and the difference between the feedback voltage (Col. 13, lines 21-26, output voltage of the output power supply node Vol is detected by the amplifier circuit AMP11 in the analog controller unit ACU. A difference between the result of detection (feedback signal FB1) and the output volt age set signal VR1 (e.g., IV or the like) is amplified by the error amplifier circuit EA1) for controlling the output voltage of the power supply device according to the difference between the target voltage and the difference between the feedback voltage and the control voltage according to the first control signal (Col. 25-Col. 26).
Therefore, it would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to modify Barbosa by adding feedback signal as part of its configuration as taught by Kudo, in order to either adds to the normal input or subtracts and correct the error amplifier circuit then power supply voltage of the load.
Regarding claim 6, Barbosa disclose wherein the step of generating the first control signal comprises controlling a duty of the power supply device (Col. 5, lines 10-12, driving signal DSla is generated with pulse width modulation (PWM) according to the current error amplification signal).
Regarding claim 7, Barbosa disclose at least one of the target voltages and the threshold current is adjusted (Col. 6, lines 17-20, control circuit 160 is configured to amplify the difference between the adjusted output current reference value Ioref_a and the output current Ioa by a current gain Gide to obtain a current error amplification signal) according to a limited power (Col. 6, lines 35-37, the intermediate bus voltage Vbusa of the corresponding power module Ma also converges to the average reference) of the power supply device.
Regarding claim 8, Barbosa disclose the load sharing control method controls a load sharing control device (160) included in each of multiple power supply devices being connected to a load in parallel (Col. 6, lines 59-61, power supply units PSUla, PSU2a-PSUna in the same power module Ma are electrically coupled in parallel).
Regarding claim 9, Barbosa disclose the load sharing control device comprises a CV circuit (Col. 2, bus voltage average value is calculated by the control circuit according to the intermediate bus voltages of the power supply units, and the first driving signals for the power supply units are generated according to the bus voltage average value) or CC-CV circuit.
Regarding claim 10, Barbosa disclose outputting a larger voltage (Col. 4, lines 60-63, the control circuit 160 is configured to amplify the difference between the bus voltage reference value Vbusref and the bus voltage average value Vbusavg by an error amplifier gain Gv to obtain an error amplification signal) between an output current sensing voltage sensing (Col. 2, lines 6-11, The power supply control method includes detecting a plurality of intermediate bus voltages of a plurality of power modules of a power supply respectively; calculating, by a control circuit of the power supply, a bus voltage average value according to the intermediate bus voltages of the power modules) an output current Col. 4, lines 4-6, output corresponding output currents Io a, lob, loc via the DC-DC converters 140a, 140b, 140c, in order to supply the load) of a power supply device modules Ma, Mb, and Mc and a control circuit 160) and a voltage of a load share bus (Col. 4, DC-DC converters 140a, 140b, 140c are configured to output the DC supply voltage Vo according to the intermediate bus voltages Vbusa, Vbusb, Vbusc); outputting a smaller voltage between the larger voltage and a voltage according to a threshold current (Col. 6, lines 17-20, control circuit 160 is configured to amplify the difference between the adjusted output current reference value Ioref_a and the output current Ioa by a current gain Gide to obtain a current error amplification signal); and amplifying a difference between the output current sensing voltage (Col. 5, lines 6-13, the control circuit 160 is configured to amplify the difference between the input current reference value Iaref and the actual phase input current Ia by a current gain Gi to obtain a current error amplification signal, and then the driving signal DSla is generated with pulse width modulation (PWM) according to the current error amplification signal) and terminal of a CV circuit (Col. 2, bus voltage average value is calculated by the control circuit according to the intermediate bus voltages of the power supply units, and the first driving signals for the power supply units are generated according to the bus voltage average value) or a CC-CV circuit.
But, Barbosa does not disclose the smaller voltage and applying it to CV feedback,
However, Kudo discloses the smaller voltage and applying it to CV feedback (Col. 13, lines 21-26, output voltage of the output power supply node Vol is detected by the amplifier circuit AMP11 in the analog controller unit ACU. A difference between the result of detection (feedback signal FB1) and the output volt age set signal VR1 (e.g., IV or the like) is amplified by the error amplifier circuit EA1),
Therefore, it would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to modify Barbosa by adding feedback signal as part of its configuration as taught by Kudo, in order to either adds to the normal input or subtracts and correct the error amplifier circuit then power supply voltage of the load.
Regarding claim 11, Barbosa disclose the threshold current is a preset value (Col. 7, lines 48-51, control circuit 160 is configured to generate the driving signal DSl_la according to a difference between the input current reference value Ilaref and the input current Ia of the power supply unit PSUla) or a value obtained by subtracting a predetermined value from a reference current of the CC-CV circuit.
Regarding claim 12, Barbosa disclose all the claim limitation as set forth in the rejection of claims above.
But, Barbosa does not disclose the step of outputting the larger voltage comprises receiving the output current sensing voltage via a positive (+) input terminal and receiving the voltage of the load share bus via a negative (-) input terminal by a first comparator; and wherein a first diode of which an anode is connected to an output end of the first comparator, and a cathode is connected to the voltage of the load share bus.
However, Kudo discloses the step of outputting the larger voltage comprises receiving the output current sensing voltage via a positive (+) input terminal and receiving the voltage of the load share bus via a negative (-) input terminal by a first comparator (Col. 11, lines 40-45, The comparator circuit CMPp [1] has a (-) input node to which the error amp signal EOl divided by the resistors Rl [1] and R2 [1] is inputted, and a ( +) input node to which the current detection signal CS [1] with the offset voltage (e.g., 0.1 V or the like) by the VOF [1] added thereof is inputted); and wherein a first diode of which an anode is connected to an output end of the first comparator, and a cathode is connected to the voltage of the load share bus (Col. 32, lines 57-64, comparator circuit CMP41, a diode D2, a switch circuit TSW 43, a bias current source IB4 and a diode group D3g for temperature detection. The diode group D3g is supplied with a bias current by the bias current source IB4. A (+) input node of the amplifier circuit AMP41 is coupled to the anode of the diode group D3g. A (-) input node of the amplifier circuitAMP41 is coupled to the anode of the diode D2 and an external terminal P36).
Therefore, it would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to modify Barbosa by adding comparator as part of its configuration as taught by Kudo, in order to detects that the power supply input voltage is a sufficient voltage level and control the overcurrent.
Regarding claim 13, Barbosa disclose all the claim limitation as set forth in the rejection of claims above.
But, Barbosa does not disclose the step of outputting the smaller voltage comprises receiving a voltage according to the threshold current via a positive (+) input terminal and receiving an output of the maximum current output circuit unit via a negative (-) input terminal by a second comparator; and wherein a second diode of which a cathode is connected to an output end of the second comparator, and an anode is connected to the voltage of the load share bus.
However, Kudo discloses the step of outputting the smaller voltage comprises receiving a voltage according to the threshold current via a positive (+) input terminal and receiving an output of the maximum current output circuit unit via a negative (-) input terminal by a second comparator (fig. 11 and Col. 32, lines 57-64, comparator circuit CMPp, a diode PSW, a switch circuit TSW 43, a bias current source IB4 and a diode group D3g for temperature detection. The diode group D3g is supplied with a bias current by the bias current source IB4. A (+) input node of the amplifier circuit AMP41 is coupled to the anode of the diode group D3g. A (-) input node of the amplifier circuitAMP41 is coupled to the anode of the diode D2 and an external terminal P36); and wherein a second diode of which a cathode is connected to an output end of the second comparator, and an anode is connected to the voltage of the load share bus (Col. 32, lines 64-67, An output node of the amplifiercircuitAMP41 is coupled to the cathode of the diode D2. A temperature detection signal/overcurrent detection signal (TMP/OCP) is generated at the external terminal P36).
Therefore, it would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to modify Barbosa by adding comparator as part of its configuration as taught by Kudo, in order to detects that the power supply input voltage is a sufficient voltage level and control the overcurrent.
Regarding claim 14, Barbosa disclose the step of amplifying the difference between the output current sensing voltage (Col. 5, lines 6-13, the control circuit 160 is configured to amplify the difference between the input current reference value Iaref and the actual phase input current Ia by a current gain Gi to obtain a current error amplification signal, and then the driving signal DSla is generated with pulse width modulation (PWM) according to the current error amplification signal) and the smaller voltage comprises: amplifying a difference between the output current sensing voltage (Col. 4, lines 28-34, control circuit 160 according to the intermediate bus voltages Vbusa, Vbusb, and Vbusc of the power modules Ma, Mb and Mc. Specifically, the intermediate bus voltages Vbusa, Vbusb, and Vbusc are multiplied by a bus voltage sensing gain Kv respectively, and then the mean value is calculated to obtain the bus voltage average value Vbusavg) and the smaller voltage by a first amplifier; amplifier; and amplifying the difference between the output current sensing voltage (Col. 5, lines 6-13, the control circuit 160 is configured to amplify the difference between the input current reference value Iaref and the actual phase input current Ia by a current gain Gi to obtain a current error amplification signal, and then the driving signal DSla is generated with pulse width modulation (PWM) according to the current error amplification signal) and the smaller voltage by a transconductance amplifier (Col. 4, the control circuit 160 is configured to amplify the difference between the bus voltage reference value Vbusref and the bus voltage average value Vbusavg by an error amplifier gain Gv to obtain an error amplification signal);
But, Barbosa does not disclose wherein a transistor of which a base is connected to an output terminal of the first amplifier, an emitter is connected to a negative (-) input terminal of the first amplifier, and a collector is connected to the CV feedback terminal.
However, Kudo discloses wherein a transistor (fig. 11, Q1, QH, QL) of which a base (Q1 base) is connected to an output terminal of the first amplifier (AMP40), an emitter (Q1 connected to AMP40 (-)) is connected to a negative (-) input terminal of the first amplifier, and a collector (down arrow feedback circuit unit FBBKPl) is connected to the CV feedback terminal (figs. 10-11, Col. 9, and Col. 10).
Therefore, it would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to modify Barbosa by adding transistor as part of its configuration as taught by Kudo, in order to input signal at the base to control a much larger current flowing through the collector.
Regarding claim 15, Barbosa disclose the transconductance amplifier has a predetermined offset voltage (Col. 6, lines 33-37, DC supply voltage Vo and the output current Ioa are respectively converge to the proper reference values. Accordingly, the intermediate bus voltage Vbusa of the corresponding power module Ma also converges to the average reference).
Regarding claim 16, Barbosa disclose the step of amplifying the difference between the output current sensing voltage and the smaller voltage comprises amplifying the difference between the output current sensing voltage (Col. 5, lines 6-13, the control circuit 160 is configured to amplify the difference between the input current reference value Iaref and the actual phase input current Ia by a current gain Gi to obtain a current error amplification signal, and then the driving signal DSla is generated with pulse width modulation (PWM) according to the current error amplification signal) and smaller voltage when the difference between the output current sensing voltage (Col. 4, lines 28-34, control circuit 160 according to the intermediate bus voltages Vbusa, Vbusb, and Vbusc of the power modules Ma, Mb and Mc. Specifically, the intermediate bus voltages Vbusa, Vbusb, and Vbusc are multiplied by a bus voltage sensing gain Kv respectively, and then the mean value is calculated to obtain the bus voltage average value Vbusavg) and smaller voltage is equal to or more than the predetermined offset voltage (Col. 6, lines 33-37, DC supply voltage Vo and the output current Ioa are respectively converge to the proper reference values. Accordingly, the intermediate bus voltage Vbusa of the corresponding power module Ma also converges to the average reference).
Regarding claim 17, Barbosa disclose sensing and amplifying the output current (Col. 6, lines 17-20, control circuit 160 is configured to amplify the difference between the adjusted output current reference value Ioref_a and the output current Ioa by a current gain Gide to obtain a current error amplification signal) and outputting the output current sensing voltage (Col. 4, lines 28-34, control circuit 160 according to the intermediate bus voltages Vbusa, Vbusb, and Vbusc of the power modules Ma, Mb and Mc. Specifically, the intermediate bus voltages Vbusa, Vbusb, and Vbusc are multiplied by a bus voltage sensing gain Kv respectively, and then the mean value is calculated to obtain the bus voltage average value Vbusavg).
Regarding claim 18, Barbosa disclose at least one among a reference voltage of the CC-CV circuit, a reference voltage of the CV circuit, or the threshold current is adjusted (Col. 6, lines 17-20, control circuit 160 is configured to amplify the difference between the adjusted output current reference value Ioref_a and the output current Ioa by a current gain Gide to obtain a current error amplification signal) according to a limited power (Col. 6, lines 35-37, the intermediate bus voltage Vbusa of the corresponding power module Ma also converges to the average reference) of the power supply device.
Regarding claim 19, Barbosa disclose the load sharing control method controls a load sharing control circuit (160) included in each of multiple power supply devices being connected to a load in parallel (Col. 6, lines 59-61, power supply units PSUla, PSU2a-PSUna in the same power module Ma are electrically coupled in parallel) and including a CV circuit (Col. 2, bus voltage average value is calculated by the control circuit according to the intermediate bus voltages of the power supply units, and the first driving signals for the power supply units are generated according to the bus voltage average value) or CC-CV circuit.
Response to argument
Applicant’s argument filed on 11-14-25 with respect to claims 1-20 has been fully considered but are moot in view of the new grounds of rejection.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Liu et al. US 2016/0134135 Al- The present invention discloses a high efficiency charging system and a charging circuit therein. The high efficiency charging system includes a power supplier and a power receiver, which are connected via a transmission wire so that power is transmitted from the power supplier to the power receiver. The power receiver includes a voltage conversion circuit and a control circuit. The voltage conversion circuit converts an adjustable input voltage provided by the power supplier to an output voltage and generates an output current for charging a battery. The voltage conversion circuit adaptively adjusts the output current according to a voltage drop between the adjustable input voltage and the output voltage. The control circuit senses the adjustable input voltage and the output voltage and instructs the power supplier to adjust the output voltage according to the voltage drop between the adjustable input voltage and output voltage.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ESAYAS G YESHAW whose telephone number is (571)270-1959. The examiner can normally be reached Mon-Sat 9AM-7PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Menna Youssef can be reached at 5712703684. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ESAYAS G YESHAW/Examiner, Art Unit 2836
/Menatoallah Youssef/SPE, Art Unit 2849