DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 1/21/2026 has been entered.
Status of Claims
Claims 5, 12 and 19 are previously or currently cancelled. New claims 21-23 are added. Claims 1-4,6-11,13-18 and 20-23 are pending, of which all pending claims are rejected.
Response to Arguments
Applicant’s arguments filed on January 21, 2026 with respect to amended claims 1-4, 6-11, 13-18, 21-23 have been considered but are moot in view of new ground(s) of rejection.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-4, 6-11, 13-18, 21-23 are rejected under 35 U.S.C. 103 as being unpatentable over Schaefer et al. (US 2020/0371873 A1) in view of Warnes et al. (US 2017/0192843 A1), (hereinafter Schaefer-Warnes).
Regarding claim 1, Schaefer teaches, a memory device comprising: a set of memory cells (Schaefer: “A memory array 170 may be a collection ( e.g., a grid) of memory cells, with each memory cell being configured to store at least one bit of digital data”. [0032] & [Fig.1, memory array 170-a to 170-N); a buffer operatively coupled to the set of memory cells (Schaefer: ‘the FIFO buffer 410 and the I/O buffers 455-a are used for temporarily holding and/or transferring of read data from the memory cell array 490a’ [Fig.4A]), the buffer to store……., the data stored by the buffer being encoded (Schaefer: ‘the received ECC version and a generated ECC version by encoding are compared for detection or errors in read data’ “During a read operation, the ECC block 365 may perform in-line ECC. Here, the ECC block 365 may receive data and the error detection or correction information (e.g., associated with the data and stored at the array 395) from the I/O logic 385. The ECC block 365 may also generate error detection or correction information based on the data read from the array 395 during the read operation. Further, the ECC block 365 may compare the received error detection or correction information with the generated error detection or correction information. In the event that the received error detection or correction information and the generated error detection or correction information do not match, the ECC block 365 may detect an error”. [0075]) using a low-density parity check (LDPC) encoding (Schaefer: “Some memory devices may be configured to internally detect and in at least some cases correct (repair) such data corruption or errors and thereby recover the data as stored before corruption. Such error detection and correction may rely upon one or more error-correcting codes (ECCs) (e.g., block codes convolutional codes, Hamming codes, low-density parity-check codes, turbo codes, polar codes), and related processes, operations. These techniques may be referred as ECC processes, ECC operations, ECC techniques, or in some cases as simply ECC or ECC”. [0013]); an LDPC decoder operatively coupled to the buffer, the LDPC decoder configured to correct one or more bits in error in the data stored by the buffer by decoding the data based on the data being encoded using the LDPC encoding, the decoding of the data resulting in corrected data, the corrected data being stored by the buffer (Schaefer: ‘LDPC encoding/decoding’ [0013]; ‘the FIFO buffer 410 and the I/O buffers 455-a are used for temporarily holding and/or transferring of corrected read data by decoding’ [Fig.4A, 4B]); and an LDPC encoder operatively coupled to the buffer and the decoder, the LDPC encoder to……, the encoding of the corrected data resulting in encoded corrected data, the encoded corrected data being stored by the buffer prior to being programmed to the set of memory cells (Schaefer: ‘LDPC encoding/decoding’ [0013]; ‘the FIFO buffer 410 and the I/O buffers 455-a are used for temporarily holding and/or transferring of corrected read data by decoding’ [Fig.4A, 4B]).
Schaefer further teaches, “Some memory devices may be configured to internally detect and in at least some cases correct (repair) such data corruption or errors and thereby recover the data as stored before corruption. ….. Error detection and correction conducted internally within a memory device on data stored previously at the memory device may generally be referred to as internal or on-die ECC (whether within a single-die memory device or a multi-die memory device), and memory devices that support internal or on-die ECC may be referred to as ECC memory or on-die ECC memory.”
Schaefer does not explicitly teach, …data read from the set of memory cells without communicating with a memory controller..; encode the corrected data using LDPC encoding without communicating with the memory controller…
However, Warnes teaches in an analogous art, [0012] Some memory modules may include memory devices that have on-die error-correcting code (ECC), which may allow errors in a memory device to be detected and, in some cases, corrected without involvement of a memory controller external to the memory module. For example, volatile memory devices, such as double data rate fourth generation synchronous dynamic random-access memory (DDR4 SDRAM), that have on-die ECC may detect errors in an SDRAM chip without involvement from an external memory controller. [0015] Memory device 104 may be on an IC on memory module 100. In some implementations, memory device 104 may be a volatile memory device, such as a dynamic random-access memory (DRAM) device. In some implementations, memory device 104 may be a non-volatile memory device (e.g. flash memory).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Schaefer’s teachings of ‘an error correction memory device with fast data access’ with Warnes’s teaching of ‘error counters on a memory device’ to provide a method where memory modules may include memory devices that have on-die error-correcting code (ECC), which may allow errors in a memory device to be detected and, in some cases, corrected without involvement of a memory controller external to the memory module. By doing so, using on-die tracking of errors detected by on-die ECC enables more efficient use of memory controller and memory module resources, as well as reduction of OS and application timeouts [0056].
Regarding claim 2, Schaefer-Warnes teaches, the memory device of claim 1, further comprising a processing device coupled to the set of memory cells, the buffer, the LDPC decoder, and the LDPC encoder, the processing device configured to perform operations comprising: programming the set of memory cells with the data; reading the data from the set of memory cells to the buffer; and programming the set of memory cells with the encoded corrected data (Warnes: ‘reprogramming corrected data into memory is well known in the art’ [0012] “Some memory modules may include memory devices that have on-die error-correcting code (ECC), which may allow errors in a memory device to be detected and, in some cases, corrected without involvement of a memory controller external to the memory module” [0012]).
Regarding claim 3, Schaefer-Warnes teaches, the memory device of claim wherein the processing device reads the data from the set of memory cells and programs the encoded corrected data to the set of memory cells without communicating with the memory controller (Warnes: ‘reprogramming corrected data into memory is well known in the art’ [0012] “Some memory modules may include memory devices that have on-die error-correcting code (ECC), which may allow errors in a memory device to be detected and, in some cases, corrected without involvement of a memory controller external to the memory module” [0012]).
Regarding claim 4, Schaefer-Warnes teaches, the memory device of claim 2,wherein: the processing device is further configured to perform operations comprising receiving, from the memory controller, the data for programming to the set of memory cells, the data being included in a command received by the memory controller; and the LDPC encoder is further to encode the data prior to the data being programmed to the set of memory cells (Schaefer: ‘writing operation’ “In some cases, the local memory controller 265 may be configured to perform a write operation (e.g., a programming operation) on one or more memory cells 205 of the memory die 200. During a write operation, a memory cell 205 of the memory die 200 may be programmed to store a desired logic state. In some cases, a plurality of memory cells 205 may be programmed during a single write operation. The local memory controller 265 may identify a target memory cell 205 on which to perform the write operation.” [0064]).
Regarding claim 6, Schaefer-Warnes teaches, the memory device of claim 1. wherein: the LDPC decoder is further to decode the encoded corrected data to correct one or more bits in error in the encoded corrected data, the decoding of the encoded corrected data resulting in further corrected data; and the LDPC encoder is further to encode the further corrected data prior to the further corrected data being programmed to the set of memory cells controller (Warnes: ‘reprogramming corrected data into memory is well known in the art’ [0012] “Some memory modules may include memory devices that have on-die error-correcting code (ECC), which may allow errors in a memory device to be detected and, in some cases, corrected without involvement of a memory controller external to the memory module” [0012]).
Regarding claim 7, Schaefer-Warnes teaches, the memory device of claim 6, wherein the LDPC decoder decodes the encoded corrected data after a predetermined interval (Warnes: ‘periodically read values of error on the memory device’ [0029]).
Regarding claim 8, Schaefer teaches, a method comprising: reading data (Schaefer: ‘data read’ “The ECC block 365 may also generate error detection or correction information based on the data read from the array 395 during the read operation [0075]) from a set of memory cells of a memory device (Schaefer: “A memory array 170 may be a collection ( e.g., a grid) of memory cells, with each memory cell being configured to store at least one bit of digital data”. [0032] & [Fig.1, memory array 170-a to 170-N) to a buffer of the memory device …… the buffer storing the data read from the set of memory cells (Schaefer: ‘the FIFO buffer 410 and the I/O buffers 455-a are used for temporarily holding and/or transferring of read data from the memory cell array 490a’ [Fig.4A]), the data stored by the buffer being encoded using a low-density parity check (LDPC) encoding (Schaefer: “Some memory devices may be configured to internally detect and in at least some cases correct (repair) such data corruption or errors and thereby recover the data as stored before corruption. Such error detection and correction may rely upon one or more error-correcting codes (ECCs) (e.g., block codes convolutional codes, Hamming codes, low-density parity-check codes, turbo codes, polar codes), and related processes, operations. These techniques may be referred as ECC processes, ECC operations, ECC techniques, or in some cases as simply ECC or ECC”. [0013]); correcting one or more bits in error in the data stored by the buffer, the correcting of the one or more bits in error comprising decoding, by an LDPC decoder of the memory device, the data stored by the buffer based on the data being encoded using the LDPC encoding, the LDPC……, the decoding of the data resulting in corrected data (Schaefer: ‘LDPC encoding/decoding’ [0013]; ‘the FIFO buffer 410 and the I/O buffers 455-a are used for temporarily holding and/or transferring of corrected read data by decoding’ [Fig.4A, 4B]); encoding, by an LDPC encoder of the memory device, the corrected data using LDPC……. the encoding of the corrected data resulting in encoded corrected data (Schaefer: ‘LDPC encoding/decoding’ [0013]; ‘the FIFO buffer 410 and the I/O buffers 455-a are used for temporarily holding and/or transferring of corrected read data by decoding’ [Fig.4A, 4B]); and
Schaefer further teaches, “Some memory devices may be configured to internally detect and in at least some cases correct (repair) such data corruption or errors and thereby recover the data as stored before corruption. ….. Error detection and correction conducted internally within a memory device on data stored previously at the memory device may generally be referred to as internal or on-die ECC (whether within a single-die memory device or a multi-die memory device), and memory devices that support internal or on-die ECC may be referred to as ECC memory or on-die ECC memory.”
Schaefer does not explicitly teach, …without communicating with a memory controller; decoder decoding the data without communicating with the memory controller…; …encoding without communicating with the memory controller….; programming the encoded corrected data to the set of memory cells.
However, Warnes teaches in an analogous art, ‘reprogramming corrected data into memory is well known in the art’ [0012] Some memory modules may include memory devices that have on-die error-correcting code (ECC), which may allow errors in a memory device to be detected and, in some cases, corrected without involvement of a memory controller external to the memory module. For example, volatile memory devices, such as double data rate fourth generation synchronous dynamic random-access memory (DDR4 SDRAM), that have on-die ECC may detect errors in an SDRAM chip without involvement from an external memory controller. [0015] Memory device 104 may be on an IC on memory module 100. In some implementations, memory device 104 may be a volatile memory device, such as a dynamic random-access memory (DRAM) device. In some implementations, memory device 104 may be a non-volatile memory device (e.g. flash memory).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Schaefer’s teachings of ‘an error correction memory device with fast data access’ with Warnes’s teaching of ‘error counters on a memory device’ to provide a method where memory modules may include memory devices that have on-die error-correcting code (ECC), which may allow errors in a memory device to be detected and, in some cases, corrected without involvement of a memory controller external to the memory module. By doing so, using on-die tracking of errors detected by on-die ECC enables more efficient use of memory controller and memory module resources, as well as reduction of OS and application timeouts [0056].
Regarding claim 9, Schaefer-Warnes teaches, the method of claim 8, wherein the encoded corrected data is stored by the buffer prior to programming the encoded corrected data to the set of memory cells (Warnes: ‘reprogramming corrected data into memory is well known in the art’ [0012] “Some memory modules may include memory devices that have on-die error-correcting code (ECC), which may allow errors in a memory device to be detected and, in some cases, corrected without involvement of a memory controller external to the memory module” [0012]).
Regarding claim 10, Schaefer-Warnes teaches, the method of claim 8, further comprising: receiving, by the memory device, the data for programming to the set of memory cells, the data being included in a command received by the memory controller and being provided to the memory device by the memory controller; and programming the data to the set of memory cells (Schaefer: ‘data writing operation into memory’ “In some cases, the local memory controller 265 may be configured to perform a write operation (e.g., a programming operation) on one or more memory cells 205 of the memory die 200. During a write operation, a memory cell 205 of the memory die 200 may be programmed to store a desired logic state. In some cases, a plurality of memory cells 205 may be programmed during a single write operation. The local memory controller 265 may identify a target memory cell 205 on which to perform the write operation.” [0064]).
Regarding claim 11, Schaefer-Warnes teaches, the method of claim 10,wherein the set of memory cells is a first set of memory cells, the method further comprising: encoding, by the LDPC encoder, the data prior to programming the data to the set of memory cells (Schaefer: ‘writing operation’ “In some cases, the local memory controller 265 may be configured to perform a write operation (e.g., a programming operation) on one or more memory cells 205 of the memory die 200. During a write operation, a memory cell 205 of the memory die 200 may be programmed to store a desired logic state. In some cases, a plurality of memory cells 205 may be programmed during a single write operation. The local memory controller 265 may identify a target memory cell 205 on which to perform the write operation.” [0064]).
Regarding claim 13, Schaefer-Warnes teaches, the method of claim 8, further comprising: reading the encoded corrected data from the set of memory cells to the buffer of the memory device; correcting one or more additional bits in error in the encoded corrected data stored by the buffer by decoding, by the LDPC decoder of the memory device, the encoded corrected data stored by the buffer, the decoding of the data resulting in further corrected data; encoding, by the LDPC encoder of the memory device, the further corrected data, the encoding of the corrected data resulting in encoded further corrected data; and programming the encoded further corrected data to the set of memory cells (Schaefer: ‘LDPC encoding/decoding process’ [0013]; ‘the FIFO buffer 410 and the I/O buffers 455-a are used for temporarily holding and/or transferring of corrected read data by decoding’ [Fig.4A, 4B]).
Regarding claim 14, Schaefer-Warnes teaches, the method of claim 13. wherein the reading of the encoded corrected data from the set of memory cells is performed after a predetermined interval from programming the encoded corrected data to the set of memory cells (Warnes: ‘periodically read values of error on the memory device’ [0029]).
Regarding claim 15, Schaefer-Warnes teaches, the method of claim 8. wherein the reading of the data from the set of memory cells to the buffer is performed without communicating information over an interface with the memory controller (Warnes: ‘reprogramming corrected data into memory is well known in the art’ [0012] “Some memory modules may include memory devices that have on-die error-correcting code (ECC), which may allow errors in a memory device to be detected and, in some cases, corrected without involvement of a memory controller external to the memory module” [0012]).
Regarding claim 16, Schaefer teaches, a memory sub-system (Schaefer: “[0019] FIG. 1 illustrates an example of a system 100 that utilizes one or more memory devices [0019] & [Fig.1, block 110]) comprising: a memory device (Schaefer: “A memory device 110. [0019, 0032] & [Fig.1, block 110) comprising: a first set of memory cells, a second set of memory cells (Schaefer: “A memory array 170 may be a collection ( e.g., a grid) of memory cells, with each memory cell being configured to store at least one bit of digital data”. [0032] & [Fig.1, memory array 170-a to 170-N), a low-density parity check (LDPC) encoder, an LDPC decoder (Schaefer: “Some memory devices may be configured to internally detect and in at least some cases correct (repair) such data corruption or errors and thereby recover the data as stored before corruption. Such error detection and correction may rely upon one or more error-correcting codes (ECCs) (e.g., block codes convolutional codes, Hamming codes, low-density parity-check codes, turbo codes, polar codes), and related processes, operations. These techniques may be referred as ECC processes, ECC operations, ECC techniques, or in some cases as simply ECC or ECC”. [0013]), and a buffer (Schaefer: ‘the FIFO buffer 410 and the I/O buffers 455-a are used for temporarily holding and/or transferring of read data from the memory cell array 490a’ [Fig.4A]); and a processing device operatively coupled with the memory device, configured to perform operations (Schaefer: “The system 100 may further include a processor 120” [0024] & [Fig.1, block 120) comprising: receiving a command to program data to the memory device; and providing the data to the memory device (Schaefer: “In some cases, the memory device 110 may receive data and/or commands from the external memory controller 105. For example, the memory device 110 may receive a write command indicating that the memory device 110 is to store certain data on behalf of a component of the system 100 (e.g., the processor 120) or a read command indicating that the memory device 110 is to provide certain data stored in a memory die 160 to a component of the system 100 (e.g., the processor 120).” [0034]); the memory device configured to perform operations comprising: encoding, by the LDPC encoder, the data received from the processing device in a first encoding operation using an LDPC encoding, the first encoding operation resulting in first encoded data (Schaefer: ‘LDPC encoding/decoding’ [0013]; ‘the FIFO buffer 410 and the I/O buffers 455-a are used for temporarily holding and/or transferring of corrected read data by decoding’ [Fig.4A, 4B]); programming the first set of memory cells with the first encoded data (Schaefer: ‘writing operation’ “In some cases, the local memory controller 265 may be configured to perform a write operation (e.g., a programming operation) on one or more memory cells 205 of the memory die 200. During a write operation, a memory cell 205 of the memory die 200 may be programmed to store a desired logic state. In some cases, a plurality of memory cells 205 may be programmed during a single write operation. The local memory controller 265 may identify a target memory cell 205 on which to perform the write operation.” [0064]; ‘LDPC encoding’ [0013]); reading the first encoded data from the first set of memory cells to the buffer …… (Schaefer: ‘the FIFO buffer 410 and the I/O buffers 455-a are used for temporarily holding and/or transferring of read data from the memory cell array 490a’ [Fig.4A]); decoding, by the LDPC decoder, the first encoded data based on the first encoded data being encoded using the LDPC encoding, the decoded data being stored by the buffer (Schaefer: ‘LDPC encoding/decoding’ [0013]); encoding, by the LDPC encoder, the decoded data being stored by the buffer in a second encoding operation, the second encoding operation resulting in second encoded data (Schaefer: “Some memory devices may be configured to internally detect and in at least some cases correct (repair) such data corruption or errors and thereby recover the data as stored before corruption. Such error detection and correction may rely upon one or more error-correcting codes (ECCs) (e.g., block codes convolutional codes, Hamming codes, low-density parity-check codes, turbo codes, polar codes), and related processes, operations. These techniques may be referred as ECC processes, ECC operations, ECC techniques, or in some cases as simply ECC or ECC”. [0013]);
Schaefer further teaches, “Some memory devices may be configured to internally detect and in at least some cases correct (repair) such data corruption or errors and thereby recover the data as stored before corruption. ….. Error detection and correction conducted internally within a memory device on data stored previously at the memory device may generally be referred to as internal or on-die ECC (whether within a single-die memory device or a multi-die memory device), and memory devices that support internal or on-die ECC may be referred to as ECC memory or on-die ECC memory.”
Schaefer does not explicitly teach, …without communicating with a memory controller…; programming the second set of memory cells with the second encoded data; performing a first touch up on the second set of memory cells without communicating with the memory controller; and performing a second touch up on the second set of memory cells without communicating with the memory controller.
However, Warnes teaches in an analogous art, ‘reprogramming corrected data into memory is well known in the art’ [0012] Some memory modules may include memory devices that have on-die error-correcting code (ECC), which may allow errors in a memory device to be detected and, in some cases, corrected without involvement of a memory controller external to the memory module. For example, volatile memory devices, such as double data rate fourth generation synchronous dynamic random-access memory (DDR4 SDRAM), that have on-die ECC may detect errors in an SDRAM chip without involvement from an external memory controller. [0015] Memory device 104 may be on an IC on memory module 100. In some implementations, memory device 104 may be a volatile memory device, such as a dynamic random-access memory (DRAM) device. In some implementations, memory device 104 may be a non-volatile memory device (e.g. flash memory).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Schaefer’s teachings of ‘an error correction memory device with fast data access’ with Warnes’s teaching of ‘error counters on a memory device’ to provide a method where memory modules may include memory devices that have on-die error-correcting code (ECC), which may allow errors in a memory device to be detected and, in some cases, corrected without involvement of a memory controller external to the memory module. By doing so, using on-die tracking of errors detected by on-die ECC enables more efficient use of memory controller and memory module resources, as well as reduction of OS and application timeouts [0056].
Regarding claim 17, Schaefer-Warnes teaches, the memory sub-system of claim 16, wherein performing the first touch up on the second set of memory cells comprises :reading the second encoded data from the second set of memory cells to the buffer; correcting one or more bits in error in the second encoded data by decoding. by the decoder, the second encoded data, the decoding of the second encoded data resulting in corrected data; encoding, by the LDPC encoder, the corrected data, the encoding of the corrected data resulting in encoded corrected data; and programming the second set of memory cells with the encoded corrected data (Warnes: ‘reprogramming corrected data into memory is well known in the art’ [0012] “Some memory modules may include memory devices that have on-die error-correcting code (ECC), which may allow errors in a memory device to be detected and, in some cases, corrected without involvement of a memory controller external to the memory module” [0012]).
Regarding claim 18, Schaefer-Warnes teaches, the memory sub-system of claim 17, wherein performing the second touch up on the second set of memory cells comprises: reading the encoded corrected data from the second set of memory cells to the buffer of the memory device; correcting one or more additional bits in error in the encoded corrected data stored by the buffer by decoding. by the LDPC decoder, the encoded corrected data stored by the buffer, the decoding of the data resulting in further corrected data; encoding. by the LDPC encoder, the further corrected data, the encoding of the corrected data resulting in encoded further corrected data; and programming the second set of memory cells with the encoded further corrected data (Schaefer: ‘LDPC encoding/decoding process’ [0013]; ‘the FIFO buffer 410 and the I/O buffers 455-a are used for temporarily holding and/or transferring of corrected read data by decoding’ [Fig.4A, 4B]).
Regarding claim 20, Schaefer-Warnes teaches, the memory sub-system of claim 16, wherein: the memory device comprises a flash memory device; the first set of memory cells comprises single level cell (SLC) memory; and the second set of memory cells comprises quad-level cell (QLC) memory (Schaefer: ‘single/multi-level programmable memory cells’ [0051]).
Regarding claim 21, Schaefer-Warnes teaches, the memory device of claim 1, wherein: the set of memory cells comprises a set of single level cell (SLC) memory cells and a set of quad-level cell (QLC) memory cells; the data read from the set of memory cells comprises data read from the set of SLC memory cells; and the encoded data is stored by the buffer prior to being programmed to the set of QLC memory cells (Schaefer: ‘single/multi-level programmable memory cells’ [0051]).
Regarding claim 22, Schaefer-Warnes teaches, the method of claim 8, wherein: the set of memory cells comprises a set of single level cell (SLC)memory cells and a set of quad-level cell (QLC) memory cells; the data read from the set of memory cells comprises data read from the set of SLC memory cells; and the programming of the encoded corrected data to the set of memory cells comprises programming the encoded corrected data to the set of QLC memory cells (Schaefer: ‘single/multi-level programmable memory cells’ [0051]).
Regarding claim 23, Schaefer-Warnes teaches, the memory sub-system of claim16, wherein the second touch up is performed after performing the first touch up after a predetermined interval (Warnes: ‘periodically read values of error on the memory device’ [0029]).
Citation of Pertinent Prior Art
It is noted that any citations to specific, pages, columns, lines, or figures in the prior art references and any interpretation of the reference should not be considered to be limiting in any way. A reference is relevant for all it contains and may be relied upon for all that it would have reasonably suggested to one having ordinary skill in the art. See MPEP 2123.
Conclusion
The following prior arts made of record, listed on form PTO-892, and not relied upon, if any, are considered pertinent to applicant's disclosure:
Bains et al. (US 2018/0210787 A1) teaches [0025] In one embodiment, the memory devices are capable of performing on-die or internal ECC, where the memory device itself includes ECC logic to perform ECC at the memory device separate from the ECC managed by the memory controller. On-die ECC refers to ECC operations where the memory device itself generates and stores check bits for write data, and applies the check bits to correct data prior to sending the data to the memory controller for read data. Thus, there is a distinction between ECC where the memory controller generates and checks the check bits, and where the memory device itself performs the checking. It will be understood that where a memory device performs internal or on-die ECC, the memory controller does not have visibility into the internal check bits, and may not even know if an error was corrected. [0051] ECC logic 180 of memory device 140 manages one or more errors occurring in the memory resources 160. The use of ECC within memory device 140 may be referred to as internal ECC or on-die ECC, or internal on-die ECC. In general, internal ECC refers to ECC implemented within memory device 140, without command or management of the ECC operations by memory controller 120 or the host. With internal ECC, in response to a write request, ECC logic 180 generates ECC bits to store with the data sent by memory controller 120. In response to a read request, ECC logic 180 checks and corrects an error in the data prior to presenting the data to memory controller 120 to satisfy the request. In one embodiment, SEC data provided from memory device 140 via operations of ECC logic 180 is indistinguishable at memory controller 120 from data with no errors.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ENAMUL MD KABIR whose telephone number is (571)270-7256. The examiner can normally be reached on 10:00-6:30 pm.
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/ENAMUL M KABIR/
Examiner, Art Unit 2112
/ALBERT DECADY/Supervisory Patent Examiner, Art Unit 2112