Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
1. This office action, in response to the amendment received 5/12/2026, is a final office action.
Response to Amendments and Arguments
2. The amendment to claim 12 has overcome the previous rejection under 35 USC 112. The previous rejection of claims 12-16 is withdrawn.
3. The amendment to independent claims 1, 11 and 18 is disclosed by the previously cited prior art. Sankabathula et al (7,656,970) discloses a selector (Column 4, lines 47-49: the baseband processor asserts rate control signal 540 which causes the ADC rate controller 534 to switch to the higher frequency sampling rate such as 80 MHz or 40 MHz.) configured to: receive a first value corresponding to the first frequency of the first clock signal and a second value corresponding to the second frequency of the first clock signal; and select the first value or the second value based on a selection signal to generate a selected value (column 4, lines 40-44: the IQ ADC typically operates at an operational sampling rate of 80 MHZ for each of the I and Q converters of the ADC 524, and this operational rate may be reduced to 20 MHZ until the time that packet energy is detected by the baseband processor. Therefore, the baseband processor receives a first value corresponding to the first frequency that indicates the previous non-operational rate of the system, a second value corresponding to the second frequency indicating the operational rate of the system and receives a selection signal that indicates that the packet energy has been detected. This will select the second value and send the rate control signal 540.). The rejections of the claims are stated below.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
4. Claims 1, 11, 18 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sankabathula et al (7,656,970).
-Regarding claim 1, Sankabathula et a teaches a device (500) (see figure 2), comprising:
an analog-to-digital converter (ADC) (524) configured to: receive a first analog signal (outputted from (514)) (referred to “packet of waveform 608”, col. 6, line 21, and (608) of figure 3A); receive a first clock signal (548) (referred to “sampling clock 548”, col. 4, line 30); and generate a first set of digital values (outputted from (524)) corresponding to the first analog signal (during a time interval between (600) and( 602) shown in figure 3A) based on the first clock signal at a low sampling rate (referred to (618, Low) of figure 3A); and
a control circuit (530, 534) coupled to the ADC and configured to: determine, via (534), that a change (being a change of energy detected in the output of the ADC at the time (602) from a low level (624) to a high level (626) (see (616) of figure 3A)) in the first set of digital values satisfies a first threshold value (being the high level) wherein the satisfactory is determined when the detected energy in the output of the ADC reaches the high level) ; and increase the first clock signal from a first frequency (being the low sampling rate) to a second frequency (being a high sampling rate (referred to ((618, High) of figure 3A) in response to determining that the change in the first set of digital values satisfies the first threshold value (see col. 4, lines 7-37 and col. 5, lines 1-21),
a selector circuit (Column 4, lines 47-49: the baseband processor asserts rate control signal 540 which causes the ADC rate controller 534 to switch to the higher frequency sampling rate such as 80 MHz or 40 MHz.) configured to: receive a first value corresponding to the first frequency of the first clock signal and a second value corresponding to the second frequency of the first clock signal; and select the first value or the second value based on a selection signal to generate a selected value (column 4, lines 40-44: the IQ ADC typically operates at an operational sampling rate of 80 MHZ for each of the I and Q converters of the ADC 524, and this operational rate may be reduced to 20 MHZ until the time that packet energy is detected by the baseband processor. Therefore, the baseband processor receives a first value corresponding to the first frequency that indicates the previous non-operational rate of the system, a second value corresponding to the second frequency indicating the operational rate of the system and receives a signal that indicates that the packet energy has been detected. This will select the second value and send the rate control signal 540.).
-Regarding claim 11, Sankabathula et a teaches method, performed by a device ((500), figure 2), the method (see figure 2) comprising:
receiving, via an analog-to-digital converter (ADC) (524), a first analog signal (outputted from (514));
receiving, via the ADC, a first clock signal (548) (referred to “sampling clock 548”, col. 4, line 30);
generating, via the ADC, a first set of digital values (outputted from (524)) corresponding to the first analog signal (during a time interval between (600) and( 602) shown in figure 3A) based on the first clock signal at a low sampling rate (referred to (618, Low) of figure 3A);
determining, via a control circuit (530, 534), that a change (being a change of energy detected in the output of the ADC at the time (602) from a low level (624) to a high level (626) (see (616) of figure 3A)) in the first set of digital values satisfies a first threshold value (being the high level) wherein the satisfactory is determined when the detected energy in the output of the ADC reaches the high level); and increasing the first clock signal from a first frequency (being the low sampling rate) to a second frequency (being a high sampling rate (referred to ((618, High) of figure 3A) in response to determining that the change in the first set of digital values satisfies the first threshold value (see col. 4, lines 7-37 and col. 5, lines 1-21);
receiving a first value corresponding to the first frequency of the first clock signal and a second value corresponding to the second frequency of the first clock signal; and selecting the first value or the second value based on a selection signal to generate a selected value (Column 4, lines 47-49: the baseband processor asserts rate control signal 540 which causes the ADC rate controller 534 to switch to the higher frequency sampling rate such as 80 MHz or 40 MHz. Column 4, lines 40-44: the IQ ADC typically operates at an operational sampling rate of 80 MHZ for each of the I and Q converters of the ADC 524, and this operational rate may be reduced to 20 MHZ until the time that packet energy is detected by the baseband processor. Therefore, the baseband processor receives a first value corresponding to the first frequency that indicates the previous non-operational rate of the system, a second value corresponding to the second frequency indicating the operational rate of the system and receives a signal that indicates that the packet energy has been detected. This will select the second value and send the rate control signal 540.).
-Regarding claim 18, Sankabathula et a teaches a system (500) (see figure 2), comprising:
a sensor as a wireless sensor (504, 502);
an analog-to-digital converter (ADC) (524) coupled to the sensor and configured to: receive a first analog signal (outputted from (514)) (referred to “packet of waveform 608”, col. 6, line 21, and (608) of figure 3A); receive a first clock signal (548) (referred to “sampling clock 548”, col. 4, line 30); and generate a first set of digital values (outputted from (524)) corresponding to the first analog signal (during a time interval between (600) and( 602) shown in figure 3A) based on the first clock signal at a low sampling rate (referred to (618, Low) of figure 3A); and
a control circuit coupled to the ADC and configured to: determine, via (534), that a change (being a change of energy detected in the output of the ADC at the time (602) from a low level (624) to a high level (626) (see (616) of figure 3A)) in the first set of digital values satisfies a first threshold value (being the high level) wherein the satisfactory is determined when the detected energy in the output of the ADC reaches the high level) ; and increase the first clock signal from a first frequency (being the low sampling rate) to a second frequency (being a high sampling rate (referred to ((618, High) of figure 3A) in response to determining that the change in the first set of digital values satisfies the first threshold value (see col. 4, lines 7-37 and col. 5, lines 1-21);
a selector circuit (Column 4, lines 47-49: the baseband processor asserts rate control signal 540 which causes the ADC rate controller 534 to switch to the higher frequency sampling rate such as 80 MHz or 40 MHz.) configured to: receive a first value corresponding to the first frequency of the first clock signal and a second value corresponding to the second frequency of the first clock signal; and select the first value or the second value based on a selection signal to generate a selected value (column 4, lines 40-44: the IQ ADC typically operates at an operational sampling rate of 80 MHZ for each of the I and Q converters of the ADC 524, and this operational rate may be reduced to 20 MHZ until the time that packet energy is detected by the baseband processor. Therefore, the baseband processor receives a first value corresponding to the first frequency that indicates the previous non-operational rate of the system, a second value corresponding to the second frequency indicating the operational rate of the system and receives a signal that indicates that the packet energy has been detected. This will select the second value and send the rate control signal 540.).
-Regarding claim 20, Sankabathula et a teaches that the sensor includes an antenna (504) as an electrical signal sensor, or namely a voltage/current sensor (see figure 2).
Allowable Subject Matter
5. Claims 2-10, 12-17 and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KEVIN M. BURD whose telephone number is (571)272-3008. The examiner can normally be reached 9:30 - 5:00.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chieh Fan can be reached at 571-272-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/KEVIN M BURD/Primary Examiner, Art Unit 2632 8/24/2026
Prosecution Insights