Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Tu et al. (US 10249756 B2) in view of Koo et al. (US 20230064803 A1) and Yoo (US 20190131458 A1).
Regarding claim 1, Tu et al. disclose a method of manufacturing a semiconductor device, the method comprising:
the substrate including the first region (MA, Fig. 3) and a second region (LA, Fig. 3);
forming a gate insulation layer (29, Fig. 3) on an upper surface of the second region of the substrate (contacts second region LA, Fig. 3);
sequentially stacking a first conductive layer (40) and a second conductive layer (50) on the gate insulation layer (30, Fig. 7A); and
patterning the second conductive layer and the first conductive layer to form first and second gate electrode structures on the first and second regions, respectively, of the substrate (Fig. 6 and Fig. 7 show the results of patterning to form gate electrode structures).
However, Tu does not disclose forming a ferroelectric layer on a first region of a substrate and a gate insulation layer on and contacting an upper surface of the ferroelectric layer.
On the other hand, Koo et al. disclose forming a ferroelectric layer (110) on a first region of a substrate (101) (paragraph 29, Fig. 1).
On the other hand, Yoo discloses a gate insulation layer (140, Fig. 1) on and contacting an upper surface of the ferroelectric layer (120, Fig. 1, paragraph 31).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Tu et al. in view of Koo et al. and Yoo such that a ferroelectric layer is on a first region of a substrate and a gate insulation layer is on and contacting an upper surface of the ferroelectric layer. Doing so would result in better channel control and suppress gate leakage currents.
Regarding claim 10, Tu discloses the first conductive layer (Fe, Fig. 1B) includes doped polysilicon (paragraph 12), and the second conductive layer (150) includes a metal, a metal nitride or a metal silicide (paragraph 16).
Regarding claim 11, Tu discloses the first region of the substrate is a memory region (FA, Fig. 3) on which a memory device is formed, and the second region of the substrate is a logic region (LA, Fig. 3) on which a logic device is formed.
Claims 2-4, 6 are rejected under 35 U.S.C. 103 as being unpatentable over Tu et al. (US 10249756 B2), Koo et al. (US 20230064803 A1) and Yoo (US 20190131458 A1) as applied to claim 1 above, in further view of Ogura et al. (US 20240164112 A1).
Regarding claim 2, Tu, Koo, and Yoo are discussed above. None of these references disclose forming the ferroelectric layer on the first region of a substrate includes: forming a preliminary ferroelectric layer on the first and second regions of the substrate; and removing a portion of the preliminary ferroelectric layer on the second region of the substrate.
However, Ogura et al. disclose forming the ferroelectric layer (AM layer can be ferroelectric, paragraph 94) on the first region of a substrate (1A) includes: forming a preliminary ferroelectric layer on the first and second regions of the substrate (1A, 2A); and removing a portion of the preliminary ferroelectric layer on the second region of the substrate (AM layer is removed in Fig. 10 in second region 2A).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Tu, Koo, and Yoo in view of Ogura such that forming the ferroelectric layer on the first region of a substrate includes: forming a preliminary ferroelectric layer on the first and second regions of the substrate; and removing a portion of the preliminary ferroelectric layer on the second region of the substrate. Doing so would prevent parasitic capacitance and eliminate unwanted short circuits between the logic and memory areas.
Regarding claim 3, Tu, Koo, and Yoo are discussed above. None of these references disclose forming a stress aggressor on the first region of the substrate; and performing a heat treatment process on the substrate having the stress aggressor and the preliminary ferroelectric layer thereon so that a portion of the preliminary ferroelectric layer on the first region of the substrate is converted into the ferroelectric layer.
However, Ogura et al. disclose forming a stress aggressor (RP4) on the first region of the substrate (3A, Fig. 10); and performing a heat treatment process (paragraph 94) on the substrate having the stress aggressor and the preliminary ferroelectric layer (AM) thereon so that a portion of the preliminary ferroelectric layer on the first region of the substrate is converted into the ferroelectric layer (FE, Fig. 10) (paragraph 94, AM layer is subjected to heat treatment to form a ferroelectric layer FE, Fig. 10).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Tu, Koo, Yoo, in view of Ogura such that forming a stress aggressor on the first region of the substrate, and performing a heat treatment process on the substrate having the stress aggressor and the preliminary ferroelectric layer thereon so that a portion of the preliminary ferroelectric layer on the first region of the substrate is converted into the ferroelectric layer. Doing so would induce the necessary crystal phase and relieve defects within the ferroelectric layer.
Regarding claim 4, Tu, Koo, and Yoo are discussed above. None of these references disclose an oxide layer is formed between the substrate and the preliminary ferroelectric layer as the heat treatment process is performed.
However, Ogura discloses an oxide layer (IL, Fig. 10, paragraph 64, layer may be made of oxide material) is formed between the substrate (SUB) and the preliminary ferroelectric layer (AM) as the heat treatment process is performed (paragraph 94).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Tu, Koo, and Yoo in view of Ogura such that an oxide layer is formed between the substrate and the preliminary ferroelectric layer as the heat treatment process is performed. Doing so would drive the chemical oxidation of the underlying substrate.
Regarding claim 6, Ty, Koo, and Yoo are discussed above. Tu discloses wherein the preliminary ferroelectric layer (39) is formed on the first (MA) and second (LA) regions of the substrate (10, Fig. 6).
Tu does not disclose prior to forming the preliminary ferroelectric layer on the first and second regions of the substrate: removing an upper portion of the first region of the substrate to form a recess, and at least partially fills the recess.
However, Yoo discloses prior to forming the preliminary ferroelectric layer on the first and second regions of the substrate: removing an upper portion of the first region of the substrate (601) to form a recess (Fig. 10A, recess is formed in substrate), and at least partially fills the recess (Fig. 10A, Fe layer 620 fills the recess).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Tu, Koo, and Ogura in view of Yoo such that removing an upper portion of the first region of the substrate to form a recess, and a ferroelectric layer at least partially fills the recess. Doing so would improve memory retention, endurance, and programming speeds.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Tu et al. (US 10249756 B2), Koo et al. (US 20230064803 A1) and Yoo (US 20190131458 A1), and Ogura et al. (US 20240164112 A1) as applied to claim 2 above, in further view of Yoo (US 20190019801 A1).
Regarding claim 5, Tu, Koo, Yoo, and Ogura are discussed above. None of these references disclose the stress aggressor includes tungsten or molybdenum.
However, Yoo (‘801) disclose the stress aggressor (140) includes tungsten or molybdenum (paragraph 44).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Tu, Koo, Yoo, and Ogura in view of Yoo (‘801) such that the stress aggressor includes tungsten or molybdenum. Doing so would allow for extreme thermal stability and mechanical strength during heat treatment.
Claims 7-9 are rejected under 35 U.S.C. 103 as being unpatentable over Tu et al. (US 10249756 B2), Koo et al. (US 20230064803 A1), Yoo (US 20190131458 A1), and Ogura et al. (US 20240164112 A1) as applied to claim 6 above, in further view of Wu et al. (US 20200006359 A1).
Regarding claim 7, Tu, Koo, Yoo, and Ogura are discussed above. None of these references disclose wherein removing a portion of the preliminary ferroelectric layer on the second region of the substrate includes performing a planarization process on the preliminary ferroelectric layer.
However, Wu discloses removing a portion of the preliminary ferroelectric layer on the second region of the substrate includes performing a planarization process on the preliminary ferroelectric layer (paragraph 49).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Tu, Koo, Yoo, and Ogura in view of Wu such that removing a portion of the preliminary ferroelectric layer on the second region of the substrate includes performing a planarization process on the preliminary ferroelectric layer. Doing so prevents short-circuiting and ensures a flat surface for depositing subsequent metal gate layers.
Regarding claim 8, Tu, Koo, Yoo, and Ogura are discussed above. None of these references disclose wherein an upper surface of a portion of the preliminary ferroelectric layer in the recess is higher than or substantially coplanar with the upper surface of the second region of the substrate.
However, Wu discloses wherein an upper surface of a portion of the preliminary ferroelectric layer (1202) in the recess (Fig. 12) is higher than or substantially coplanar with the upper surface of the second region (201b) of the substrate (102, Fig. 12).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Tu, Koo, Yoo, and Ogura in view of Wu such that an upper surface of a portion of the preliminary ferroelectric layer in the recess is higher than or substantially coplanar with the upper surface of the second region of the substrate. Doing so would ensure reliable electrical contact and sufficient functional volume.
Regarding claim 9, Tu, Koo, Yoo, and Ogura are discussed above. None of these references disclose an upper surface of a remaining portion of the preliminary ferroelectric layer in the recess, except for a portion of the preliminary ferroelectric layer adjacent to the second region of the substrate, is lower than the upper surface of the second region of the substrate.
However, Wu discloses an upper surface of a remaining portion of the preliminary ferroelectric layer (1202) in the recess (Fig. 12), except for a portion of the preliminary ferroelectric layer adjacent to the second region of the substrate, is lower than the upper surface of the second region of the substrate (partial area of Fe layer 1202 in the recess is lower than substrate in 201b, Fig. 12).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Tu, Koo, Ogura, and Yoo in view of Wu such that an upper surface of a remaining portion of the preliminary ferroelectric layer in the recess, except for a portion of the preliminary ferroelectric layer adjacent to the second region of the substrate, is lower than the upper surface of the second region of the substrate. Doing so would reduce parasitic capacitance and ensure precise gate alignment.
Claims 12-16, 18 are rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. (US 20200006359 A1) in view of Ogura et al. (US 20240164112 A1), and Yoo (US 20190131458 A1).
Regarding claim 12, Wu discloses a method of manufacturing a semiconductor device, the method comprising:
removing an upper portion of a first region of a substrate to form a recess (201a, Fig 12), the substrate including the first region (201a) and a second region (201b);
forming a preliminary ferroelectric layer (1202, Fig. 12) on the first and second regions of the substrate to at least partially fill the recess (Fig. 12);
Wu does not disclose performing a heat treatment process on the substrate so that a portion of the preliminary ferroelectric layer on the first region of the substrate is converted into a ferroelectric layer; removing the preliminary ferroelectric layer to expose an upper surface of the second region of the substrate; forming a gate insulation layer on the ferroelectric layer and the second region of the substrate; and forming first and second gate electrode structures on the first and second regions, respectively, of the substrate.
On the other hand, Ogura discloses performing a heat treatment process on the substrate so that a portion of the preliminary ferroelectric layer (AM, Fig. 10, can be heat treated to form FE layer, paragraph 94) on the first region (3A) of the substrate is converted into a ferroelectric layer (FE);
removing the preliminary ferroelectric layer (AM, Fig. 9) to expose an upper surface of the second region (2A) of the substrate (SUB, Fig. 10) (paragraph 97);
forming a gate insulation layer (GI2) on the second region (2A) of the substrate (SUB, Fig. 11)
and forming first and second gate electrode structures (GE2, SG, MG, Fig. 3) on the first and second regions (2A, 3A, Fig. 3), respectively, of the substrate.
Neither reference discloses forming a gate insulation layer on the ferroelectric layer.
However, Yoo discloses forming a gate insulation layer (140) on the ferroelectric layer (120, Fig. 1).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Wu in view of Ogura and Yoo such that a manufacturing method includes performing a heat treatment process on the substrate so that a portion of the preliminary ferroelectric layer on the first region of the substrate is converted into a ferroelectric layer; removing the preliminary ferroelectric layer to expose an upper surface of the second region of the substrate; forming a gate insulation layer on the ferroelectric layer and the second region of the substrate; and forming first and second gate electrode structures on the first and second regions, respectively, of the substrate. Doing so would prevent degradation at the boundaries of the memory stacks and minimizes short channel effects in advanced nodes.
Regarding claim 13, Wu, Ogura, and Yoo are discussed above. Wu does not disclose after forming the preliminary ferroelectric layer on the first and second regions of the substrate: forming a stress aggressor on the first region of the substrate.
However, Ogura discloses after forming the preliminary ferroelectric layer on the first (3A) and second regions (2A, Fig. 10) of the substrate (AM layer is preliminary FE layer, paragraph 97): forming a stress aggressor (CF, Fig. 12) on the first region of the substrate.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Wu in view of Ogura and Yoo such that after forming the preliminary ferroelectric layer on the first and second regions of the substrate: forming a stress aggressor on the first region of the substrate. Doing this serves to optimize the crystalline phase and electrical performance of the ferroelectric layer.
Regarding claim 14, Wu discloses wherein removing the preliminary ferroelectric layer (1202, Fig. 12) includes performing a planarization process on the preliminary ferroelectric layer (paragraph 49, Fig. 12-13).
Regarding claim 15, Wu discloses an upper surface of a portion of the preliminary ferroelectric layer (1202) in the recess (Fig. 12) is higher than or substantially coplanar with the upper surface of the second region of the substrate (partial area of Fe layer 1202 in the recess is higher than substrate in 201b, Fig. 12).
Regarding claim 16, Wu discloses an upper surface of a remaining portion of the preliminary ferroelectric layer (1202) in the recess (Fig. 12), except for a portion of the preliminary ferroelectric layer adjacent to the second region of the substrate, is lower than the upper surface of the second region of the substrate (partial area of Fe layer 1202 in the recess is lower than substrate in 201b, Fig. 12).
Regarding claim 18, Wu discloses wherein the first region of the substrate is a memory region (201a) on which a memory device is formed, and the second region of the substrate is a logic region (201b) on which a logic device is formed (Fig. 2).
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. (US 20200006359 A1), Ogura et al. (US 20240164112 A1), and Yoo (US 20190131458 A1) as applied to claim 12 above, in further view of Tu et al. (US 10249756 B2).
Regarding claim 17, Wu, Ogura, and Yoo are discussed above. None of these references disclose wherein forming the first and second gate electrode structures on the first and second regions, respectively, of the substrate includes: sequentially stacking a first conductive layer and a second conductive layer on the gate insulation layer; and patterning the second conductive layer and the first conductive layer to form the first and second gate electrode structures on the first and second regions, respectively, of the substrate.
However, Tu discloses wherein forming the first and second gate electrode structures (gate electrode structures formed by gate electrode layer 64 and 69, Fig. 7B) on the first and second regions (MA and LA, Fig. 7B), respectively, of the substrate includes:
sequentially stacking a first conductive layer (40) and a second conductive layer (50) on the gate insulation layer (30, Fig. 7A); and
patterning the second conductive layer and the first conductive layer to form the first and second gate electrode structures on the first and second regions, respectively, of the substrate (Fig. 6 and Fig. 7 show the results of patterning to form gate electrode structures).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Wu, Ogura and Yoo in view of Tu such that forming the first and second gate electrode structures on the first and second regions, respectively, of the substrate includes: sequentially stacking a first conductive layer and a second conductive layer on the gate insulation layer; and patterning the second conductive layer and the first conductive layer to form the first and second gate electrode structures on the first and second regions, respectively, of the substrate. Doing so would enable uniform layer thickness and overlap gate electrodes.
Claims 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Ogura et al. (US 20240164112 A1), Wu et al. (US 20200006359 A1), and Yoo (US 20190131458 A1).
Regarding claim 19, Ogura et al. disclose a method of manufacturing a semiconductor device, the method comprising:
forming a stress aggressor (RP4, Fig. 10) on a portion of the preliminary ferroelectric layer (AM, on the first region (3A) of the substrate (SUB, Fig. 10);
performing a heat treatment process on the substrate so that a portion of the preliminary ferroelectric layer under the stress aggressor is converted into a ferroelectric layer (AM layer is converted into ferroelectric layer, paragraph 94);
forming a gate insulation layer (GI2) on the second region (2A, Fig. 10) of the substrate; and
forming first and second gate electrode structures (GE1, GE2, SG, MG, Fig. 3) on the first and second regions (1A-3A, Fig. 3), respectively, of the substrate.
However, Ogura does not disclose removing an upper portion of a first region of a substrate to form a recess, the substrate including the first region and a second region; forming a preliminary ferroelectric layer on the first and second regions of the substrate to at least partially fill the recess; performing a planarization process on the preliminary ferroelectric layer to expose an upper surface of the second region of the substrate; forming a gate insulation layer on the ferroelectric layer.
On the other hand, Wu et al. disclose removing an upper portion of a first region (201a, Fig. 5) of a substrate (102) to form a recess (recess is formed in Fig. 5), the substrate including the first region (201a) and a second region (201b); forming a preliminary ferroelectric layer (1202, Fig. 12) on the first and second regions (201a, 201b) of the substrate to at least partially fill the recess (Fig. 12); performing a planarization process on the preliminary ferroelectric layer to expose an upper surface of the second region of the substrate (paragraph 49, Fig. 12-13);
Neither Ogura nor Wu disclose forming a gate insulation layer on the ferroelectric layer.
However, Yoo discloses forming a gate insulation layer (140) on the ferroelectric layer (120, Fig. 1).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Ogura in view of Wu and Yoo such that removing an upper portion of a first region of a substrate to form a recess, the substrate including the first region and a second region; forming a preliminary ferroelectric layer on the first and second regions of the substrate to at least partially fill the recess; performing a planarization process on the preliminary ferroelectric layer to expose an upper surface of the second region of the substrate; forming a gate insulation layer on the ferroelectric layer. Doing so would define deeply embedded gate stacks that enhance the transistor’s memory window and reduce short-channel effects.
Regarding claim 20, Ogura, Wu, and Yoo are discussed above. Ogura does not disclose an upper surface of a portion of the preliminary ferroelectric layer in the recess is higher than or substantially coplanar with the upper surface of the second region of the substrate.
However, Wu discloses an upper surface of a portion of the preliminary ferroelectric layer in the recess (1202, recess in 201a of Fig. 12) is higher than or substantially coplanar with the upper surface of the second region (201b) of the substrate (Fig. 12).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Ogura in view of Wu and Yoo such that an upper surface of a portion of the preliminary ferroelectric layer in the recess is higher than or substantially coplanar with the upper surface of the second region of the substrate. Doing so would uniform gate coverage and prevent ferroelectric thinning.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEVE Q PHAN whose telephone number is (571)272-1227. The examiner can normally be reached Monday - Friday 8am - 5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon Fletcher can be reached at (571) 272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/STEVE PHAN/Examiner, Art Unit 2817
/MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817
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