INotice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This office action is responsive to communication(s) filed on December 5, 2025.
Claims 1-17 are presented for examination.
Applicant's arguments with respect to the newly added limitations have been considered but are moot in view of the new ground(s) of rejections as set forth below.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4, 6-8, 10, 13, and 15-17 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Kim (US 2022/0122678 A1) in view of Ohsawa (US 6292424 B1).
Regarding claims 1, 8, and 13: Kim (FIG. 2-3 and 6-7) disclose a memory device (100) comprising: a memory cell array (110, or FIG. 3 including a plurality of memory cells coupled to a selected word line WL1); a voltage generator (121) configured to generate a plurality of operating voltages (Vop, par. 77) for distinguishing a plurality of states (multi levels, par. 96, par. 152, FIG. 7) corresponding to the plurality of memory cells, wherein the plurality of states comprises first states (PV2) and second states (PV1); a row decoder (122) configured to perform an under-drive operation including decreasing a voltage level (to ground before and after applying a verify voltage, for example Vvfy1, FIG. 6) of the selected word line (Selected WL, FIG. 5) and to apply the plurality of operating voltages (Vvfy1-Vvfy3) to the selected word line; and control logic (130) configured to control the row decoder to apply a ground voltage (ground voltage 0V, par. 111; before Vvfy2) to the selected word line during the under-drive operation corresponding to first states (PV2) and to apply an under-drive voltage (ground before Vvfy1) to the selected word line during the under-drive operation corresponding to second states (PV1), wherein the second states have a threshold voltage lower than a threshold voltage corresponding to the first states (FIG. 7).
Kim does not disclose the ground voltage is supplied from ground.
Ohsawa does disclose a DRAM where the block diagram (FIG. 6) shows the ground nodes GND (FIG. 6) of which it is stated that GND=0V (col. 10 ll. 29).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have a ground voltage of Kim to have come from a ground GND where both are defined as 0V.
Regarding claim 2: Kim discloses an internal operation that includes at least one of a read operation (par. 58) and a verify operation (par. 82), and the operating voltage includes at least one of a read voltage (par. 75) and a verify voltage (par. 75).
Regarding claim 3: Kim does disclose the row decoder configured to provide the ground voltage (row decoder applies ground voltage, par. 79).
Kim does not disclose the ground is coupled to the row decoder.
Ohsawa does disclose a ground (GND, FIG. 6) coupled to the row decoder (GND of row circuit 12 coupled to row decoder 21, FIG. 6).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have had the ground configuration of Ohsawa to modify the configuration of Kim to have the aforementioned configuration.
Regarding claim 4: Kim discloses a row decoder that couples the selected word line to the ground voltage during the under-drive operation (row decoder applies ground voltage, par. 79).
Regarding claim 6: Kim discloses an operating voltage having a positive voltage level (Vvfy1 greater than ground voltage, FIG. 6).
Regarding claim 7: Kim discloses, through the under-drive operation, the voltage level of the selected word line is a voltage level corresponding to the ground voltage (Vvfy1 dropping to ground, FIG. 6).
Regarding claim 10: Kim discloses, through the under-drive operation corresponding to the first states (PV2), the control logic is configured to control the row decoder such that the voltage level of the selected word line is a voltage level corresponding to the ground voltage (par. 79).
Regarding claim 15: Kim discloses the first operating voltage comprises applying the first operating voltage having a positive voltage level to the selected word line (Program Loop 1 where Vvfy1 is heightened above ground voltage, FIG. 6).
Regarding claim 16: Kim discloses the second operating voltage comprises applying the second operating voltage having a positive voltage level to the selected word line (another read voltage Vvfy2 applied to selected word line, also at a positive level, FIG. 6).
Regarding claim 17: Kim discloses the ground voltage comprises decreasing the voltage level of the selected word line from the first operating voltage to the ground voltage (ground voltage applied to selected word line after Vvfy1, decreasing the voltage level of selected word to ground, FIG. 6).
Claims 12 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 2022/0122678 A1) in view of Jeong (US 11,923,018 B2).
Kim does not disclose a control logic that is configured to control the row decoder such that the plurality of operating voltages are sequentially applied to the selected word line in descending order of voltage levels.
Jeong does disclose a semiconductor memory device (100) control logic that is configured to control the row decoder such that the plurality of operating voltages are sequentially applied to the selected word line in descending order of voltage levels (after Vpgm and ground, operating voltages Vvr1-VVr3 are ordered sequentially in decreasing voltage level order, FIG 5A).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the memory device of Kim with the configuration of Jeong in order to allow the following operating voltages to be applied in decreasing voltage level order.
Allowable Subject Matter
Claims 5, 9, and 11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons of the indication of allowable subject matter: See previous Office action.
Response to Arguments
Applicants’ arguments have been fully considered but they are not persuasive.
For the above reasons, it is believed that the rejections should be sustained. Feature of an invention not found in the claims can be given no patentable weight in distinguishing the claimed invention over the prior art.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
When responding to the office action, Applicants are advised to provide the examiner with the line numbers and page numbers in the application and/or references cited to assist the examiner to locate the appropriate paragraphs.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANTHONY THINH TANG whose telephone number is (571)272-6845. The examiner can normally be reached Monday-Friday 7:30-5:00 ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at (571)272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ANTHONY THINH TANG/Examiner, Art Unit 2827