Prosecution Insights
Last updated: April 19, 2026
Application No. 18/587,247

REMOTE DIRECT MEMORY ACCESS DATA REPLICATION MODEL

Final Rejection §103
Filed
Feb 26, 2024
Examiner
DALENCOURT, YVES
Art Unit
2457
Tech Center
2400 — Computer Networks
Assignee
Microsoft Technology Licensing, LLC
OA Round
2 (Final)
84%
Grant Probability
Favorable
3-4
OA Rounds
3y 1m
To Grant
79%
With Interview

Examiner Intelligence

Grants 84% — above average
84%
Career Allow Rate
759 granted / 902 resolved
+26.1% vs TC avg
Minimal -6% lift
Without
With
+-5.5%
Interview Lift
resolved cases with interview
Typical timeline
3y 1m
Avg Prosecution
25 currently pending
Career history
927
Total Applications
across all art units

Statute-Specific Performance

§101
7.6%
-32.4% vs TC avg
§103
35.7%
-4.3% vs TC avg
§102
28.7%
-11.3% vs TC avg
§112
14.3%
-25.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 902 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . This office action is responsive to amendment filed on 12/03/2025. Information Disclosure Statement The information disclosure statement (IDS) submitted on 10/03/2025 and 01/05/2026 was filed after the mailing date of the non-final on 08/27/2025. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Response to Amendment The Examiner has acknowledged the amended claims 1, 11, and 17. Response to Arguments Applicant’s arguments with respect to claims 1 - 20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claims 1 – 3, 5 – 6, 9 - 13, 15 – 17, and 19 - 20 are rejected under 35 U.S.C. 103 as being unpatentable over Benhanokh et al (US 2021/0216459; hereinafter Benhanokh) in view of Voigt et al (US 2017/0052723; hereinafter Voigt), and further in view of CRADDOCK et al (US 2012/0054381; hereinafter CRADDOCK). Regarding claim 1, Benhanokh discloses a method implemented in a computer system that includes a processor system (paragraphs [0005], [0033]), comprising: identifying a log for replication to a remote computer system (paragraphs [0005], [0064]; Benhanokh discloses that data structure 500 may be referred to herein as a “cache slot table. “Cache slot table 500 may include a plurality of entries (i.e., rows) 502, each row representing an LSU track (e.g., any of LSU tracks 86-88 in track table 82) identified by an LSU ID in column 504 and an LSU track ID (e.g., number) identified in column 506), the log comprising a data portion and a metadata portion (abstract; paragraphs [0025], [0111], [0163 - 0165]; Benhanokh discloses that each of tables 762, 772, 772′, 782 and 750 may include at least a portion of the metadata stored in 762, 772, 772′, 782 and 750, respectively; e.g., metadata corresponding to physical storage devices 624, and logical storage devices associated therewith, being used for applications running on host system 700); sending the data portion to the remote computer system using a Remote Direct Memory Access (RDMA) write operation (paragraphs [0128 – 0132], [0137]; Benhanokh discloses that a write command message sent from SSI 716 to director 637, for example, as an NVMeoF command capsule, specifying the write operation which may include the logical storage device and one or more data portions and/or logic tracks representing one or more logical address ranges within the logical storage device); sending the metadata portion to the remote computer system using a first RDMA send operation, wherein the first RDMA send operation is issued after sending the data portion to the remote computer system using the RDMA write operation (paragraphs [0043], [0128 – 0132]; Benhanokh discloses that it may be determined whether the storage system (e.g., storage system 620a), or a component thereof pertinent to the data to be read (e.g., a LUN or namespace of the data) is currently in a complex state, for example, based on the metadata accessed in step 814. For example, it may be determined that one or more particular data services (e.g., replication, backup, offline data deduplication, etc.) are currently being performed on the LUN of the data). Benhanokh discloses all the limitations, but fails to specifically disclose identifying a second RDMA send operation received from the remote computer system, the second RDMA send operation signaling completion of the first RDMA send operation; and determining a completion of replication of the log to the remote computer system based on identifying the second RDMA send operation. Voigt, in an analogous art, discloses identifying a second RDMA (Voigt discloses a separate RDMA) send operation received from the remote computer system (paragraphs [0022], [0034]; Voigt discloses that multiple RDMAs may be used to transfer the identified data to the remote storage entity), the second RDMA send operation signaling completion of the first RDMA send operation (paragraph [0041]; Voigt discloses that replication module 406 may transmit a completion notification after the associated with the plurality of sync commands has been replicated. The completion data notification may indicate that an application consistency point has been reached); and determining a completion of replication of the log to the remote computer system based on identifying the second RDMA send operation (paragraphs [0034][0036]; Voigt discloses that An acknowledgment counter value of zero may indicate that execution of an rsync command (e.g., the rsync command in response to which data associated with the plurality of sync commands is replicated) has been completed.). Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the teaching of Benhanokh by identifying a second RDMA send operation received from the remote computer system, the second RDMA send operation signaling completion of the first RDMA send operation; and determining a completion of replication of the log to the remote computer system based on identifying the second RDMA send operation as evidenced by Voigt for the purpose of enabling tracking of completion of a remote synchronization of data in a reliable manner. Benhanokh and Voigt discloses all the limitations, but fail to specifically disclose processing of the first RDMA send operation at the remote computer system ensures completion of the RDMA write operation, thereby ensuring that the data portion is fully written to memory of the remote computer system. CRADDOCK, in an analogous art, discloses that processing of the first RDMA send operation at the remote computer system ensures completion of the RDMA write operation, thereby ensuring that the data portion is fully written to memory of the remote computer system (paragraphs [0055 – 0056], [0058]; CRADDOCK discloses that a DMA read of the last byte or cache line of the RDMA write operation. Normal PCI ordering rules dictate that all preceding DMA writes are to complete before the DMA read data is returned. Responsive to the DMA read operation completing, which indicates that the data has been written to memory and visible by the remote processor, the remote adapter sends an acknowledgment 632 to the sending adapter. This acknowledgment, which is generated responsive to completion of the DMA read operation, guarantees that the data is in memory, since ordering rules adhered to by the interconnect (e.g., PCI) between the adapter and memory mandate that for the read to complete successfully, all the data is to have been stored in memory). Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the teachings of Benhanokh and Voigt by showing that processing of the first RDMA send operation at the remote computer system ensures completion of the RDMA write operation, thereby ensuring that the data portion is fully written to memory of the remote computer system as evidenced by CRADDOCK for the purpose of avoiding a request being sent from the sender adapter to the remote adapter requesting the read, latency is decreased, and therefore, system performance is improved. Regarding claim 2, Benhanokh, Voigt, and CRADDOCK disclose the method of claim 1, wherein the log is stored in a write cache managed by a host cache service (Benhanokh: paragraph [0043]; Benhanokh discloses that write data received at the storage system from a host or other client may be initially written to cache 28 and marked as write pending. For example, cache 28 may be partitioned into one or more portions called cache slots, which may be a of a predefined uniform size, for example, 128 Kbytes). Regarding claim 3, Benhanokh, Voigt, and CRADDOCK disclose the method of claim 2, wherein the write cache is stored in a persistent memory (Benhanokh: paragraphs [0080], [0095]). Regarding claim 5, Benhanokh, Voigt, and CRADDOCK disclose the method of claim 1, wherein a size of the data portion is a multiple of a size of a memory page in the computer system (Benhanokh: paragraph [0043]). Regarding claim 6, Benhanokh, Voigt, and CRADDOCK disclose the method of claim 1, wherein the method further comprises: identifying an input/output (I/O) operation (Benhanokh: paragraphs [0032 - 0033], [0069], [0077]; Benhanokh discloses that the N hosts 14a-n may access the storage system 20a, for example, in performing input/output (IO) operations or data requests, through network 18); generating the log from the I/O operation (Benhanokh: paragraphs [0032 - 0033], [0069], [0077]); and committing the I/O operation based on determining the completion of the replication of the log to the remote computer system (Benhanokh: paragraphs [0101][0138]). Regarding claim 9, Benhanokh, Voigt, and CRADDOCK disclose the method of claim 1, wherein the second RDMA send operation comprises an indication of a success status (Voigt: paragraph [0036]; Voigt discloses that the acknowledgment counter may be incremented each time a sync command is issued, and may be decremented as data associated with a sync command is replicated in a remote storage entity (e.g., as indicated by RDMA completion acknowledgments). An acknowledgment counter value of zero may indicate that execution of an rsync command (e.g., the rsync command in response to which data associated with the plurality of sync commands is replicated) has been completed). Same motivation as in claim 1. Regarding claim 10, Benhanokh, Voigt, and CRADDOCK disclose the method of claim 1, wherein the method further comprises de-staging the log to a backing store (Benhanokh: paragraph [0057]; Benhanokh discloses that storage system 20a, and storage system 620a described in more detail elsewhere herein, may include memory elements (e.g., cache) that hold data stored on physical storage devices or that is currently held (“staged”) and will be stored (“de-staged”) to physical storage devices, and memory elements that store metadata (e.g., any of the metadata described herein) associated with such data.). Claims 4, 14, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Benhanokh, Voigt, and CRADDOCK in view of Anthony Paul Astolfi (US 12,271,625; hereinafter Astolfi). Regarding claim 4, Benhanokh, Voigt, and CRADDOCK disclose all the limitations in claim 1, but fail to specifically disclose that the data portion is stored in a first ring buffer within a memory, and the metadata portion is stored in a second ring buffer within the memory. Astolfi, in an analogous art, discloses that the data portion is stored in a first ring buffer within a memory (440, fig. 4B; col. 3, lines 43 – 61, col. 21, line 13 through col. 22, line 21, col. 54, lines 25 - 49; Astolfi discloses that the write-ahead log can be implemented using the in-memory ring buffer and the flushing of data to disk can implement the writing of updates to the storage structure), and the metadata portion is stored in a second ring buffer within the memory (430, fig. 4B; col. 3, lines 43 – 61, col. 21, line 13 through col. 22, line 21, col. 54, lines 25 - 49). Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the teachings of Benhanokh, Voigt, and CRADDOCK by showing that the data portion is stored in a first ring buffer within a memory, and the metadata portion is stored in a second ring buffer within the memory as evidenced by Astolfi for the purpose of automatically maximizing the amount of concurrent I/O while guaranteeing that all durable data remains consistent in the event of a crash between any two atomic 512-byte block writes; thereby permitting greater parallelization and improved efficiency. Claims 7 – 8, are rejected under 35 U.S.C. 103 as being unpatentable over Benhanokh, Voigt, CRADDOCK, in view of Gabriel Alatorre (US 2012/0278511; hereinafter Alatorre). Regarding claim 7, Benhanokh, Voigt, and CRADDOCK disclose all the limitations in claim 6, but fail to specifically disclose that the I/O operation is identified from a virtual storage controller; and committing the I/O operation comprises notifying the virtual storage controller. Alatorre, in an analogous art, discloses that that the I/O operation is identified from a virtual storage controller (paragraphs [0080], [0085]; Alatorre discloses that computer 30 also includes a performance monitoring program 80, according to the prior art, which tracks the number of I/O reads/writes, response times of the storage subsystems, and other performance parameters of the various storage devices including the virtual storage controller 90, storage subsystems 120 and 130, and storage pools); and committing the I/O operation comprises notifying the virtual storage controller (paragraphs [0107], [0109], and [0112]; Alatorre discloses that the scheduling program 45 cancels the (most recent to begin execution of) currently executing data transfer commands/requests in excess of M migration requests by identifying the (most recent to begin execution of) currently executing data transfer commands/requests in excess of M migration requests sent to the virtual storage controller 99 and notifying the virtual storage controller 99 to stop executing them.). Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the teachings of Benhanokh, Voigt, and CRADDOCK by showing that the I/O operation is identified from a virtual storage controller; and committing the I/O operation comprises notifying the virtual storage controller as evidenced by Alatorre for the purpose of transferring data from a source storage device to another storage device in a convenient and reliable manner. Regarding claim 8, Benhanokh, Voigt, CRADDOCK, and Alatorre disclose the method of claim 7, wherein the virtual storage controller is a virtual Non- Volatile Memory Express (NVMe) controller (Benhanokh: paragraphs [0101], [0153]). Claims 11 – 20 incorporate all the limitations of claims 1 – 10 with minor modifications in the claimed language. The reasons for rejecting claims 1 – 10 apply in claims 11 – 20. Therefore, claims 11 – 20 are rejected for the same reasons. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Contact Information Any inquiry concerning this communication or earlier communications from the examiner should be directed to YVES DALENCOURT whose telephone number is (571)272-3998. The examiner can normally be reached M-F 8AM-5:30PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ario Etienne can be reached at 571-272-4001. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /YVES DALENCOURT/Primary Examiner, Art Unit 2457
Read full office action

Prosecution Timeline

Feb 26, 2024
Application Filed
Aug 23, 2025
Non-Final Rejection — §103
Dec 03, 2025
Response Filed
Feb 02, 2026
Final Rejection — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
84%
Grant Probability
79%
With Interview (-5.5%)
3y 1m
Median Time to Grant
Moderate
PTA Risk
Based on 902 resolved cases by this examiner. Grant probability derived from career allow rate.

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