FIRST NON-FINAL REJECTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
Figure 1 should be designated by a legend such as --Prior Art-- because only that which is old is illustrated. See MPEP § 608.02(g). Corrected drawings in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. The replacement sheet(s) should be labeled “Replacement Sheet” in the page header (as per 37 CFR 1.84(c)) so as not to obstruct any portion of the drawing figures. If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 6-12, 14, and 15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Van Der Wiel U.S. Patent Application Publication 2016/0265999.
With respect to claim 1, Van Der Wiel teaches a semiconductor pressure sensor in a substrate (pressure sensor having a substrate, paragraph 89, figure 10), the semiconductor pressure sensor comprising a membrane (membrane 2, paragraph 132, figure 10), delineated by an edge (the sides of the membrane 2, figure 2), and a group of neighboring piezo resistors (P1-P4, paragraph 132, figure 10), the group comprising: a first pair of piezo resistors (P1), comprising a first piezo resistor (R1) and a second piezo resistor (R2) near the edge of the membrane (figures 7, 8, and 10), and positioned such that center points of the first pair of piezo resistors are located on the membrane (paragraphs 117 and 135), a second pair of piezo resistors (P3), comprising a third piezo resistor (R5) and a fourth piezo resistor (R6) at a position where applied pressure causes reduced surface stress compared to surface stress at the position of the first and the second piezo resistor (interpreted as the position of P3 relative to P1, figure 10), wherein the first and the third piezo resistor (R1 and R5) are substantially orthogonal to the second and the fourth piezo resistor (R2 and R4, figures 7, 8, and 10), wherein the semiconductor pressure sensor is configured such that a signal from the first piezo resistor and a signal from the second piezo resistor, corrected with a signal from the third piezo resistor and a signal from the fourth piezo resistor (output of first bridge is corrected with the second bridge, paragraph 135), are used as a measure of a pressure on the membrane (paragraph 137).
With respect to claim 2, Van Der Wiel teaches wherein the four piezo resistors form a point symmetric layout (figure 10).
With respect to claim 3, Van Der Wiel teaches wherein the first piezo resistor and the third piezo resistor are positioned symmetrically with respect to a mirror line parallel with the edge of the membrane (figure 10), and wherein the second piezo resistor and the fourth piezo resistor are positioned symmetrically with respect to a mirror line parallel with the edge of the membrane (figure 10).
With respect to claims 6 and 7, Van Der Wiel teaches wherein the piezo resistors of the group of neighboring piezo resistors are connected to a common node (P1 and P3 are connected to common nodes, figure 10), and wherein the common node is connected to the substrate (figure 10).
With respect to claim 8, Van Der Wiel teaches wherein the semiconductor pressure sensor is configured for applying, per piezo resistor, a predefined current through the piezo resistors (a first current will flow from A to C through the first branch formed by R1 in series with R2, paragraphs 94 and 113-114).
With respect to claim 9, Van Der Wiel teaches, wherein the predefined current is the same for each piezo resistor (the resistor pairs have connected nodes that allow for a same current path, figure 10).
With respect to claims 10 and 12, Van Der Wiel teaches wherein the signals from the piezo resistors are voltages across the piezo resistors and wherein the semiconductor pressure sensor is configured for obtaining the measure of the pressure on the membrane by calculating the voltage across the second piezo resistor minus the voltage across the first piezo resistor plus the voltage across the third piezo resistor minus the voltage across the fourth piezo resistor (a voltage differential value from the bridge circuits is determined to determine pressure, paragraph 137).
With respect to claim 11, Van Der Wiel teaches wherein an average of the voltage across the third piezo resistor and the voltage across the fourth piezo resistor is used for obtaining the measure of temperature on the resistor combination (bridge values may be averaged, paragraph 145).
With respect to claim 14, Van Der Wiel teaches wherein the neighboring piezo resistors are present in a quarter of the membrane (the piezoresistors R1, R2, R5, R6 are in a quarter of the membrane, figure 10).
With respect to claim 15, Van Der Wiel teaches wherein the semiconductor is configured for comparing the signal of at least two piezo resistors for determining correct functionality of the semiconductor pressure sensor (self test or reliability check is performed, paragraph 145).
Claim(s) 1-3, 6-10, 12, 13, and 14 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Van Der Wiel EP3032235 (hereinafter Van Der Wiel ‘235).
With respect to claim 1, Van Der Wiel ‘235 teaches a semiconductor pressure sensor in a substrate (pressure sensor 400 having a substrate, figure 14), the semiconductor pressure sensor comprising a membrane (membrane 2, figure 14), delineated by an edge (the sides of the membrane 2, figure 14), and a group of neighboring piezo resistors (P1-P4, figure 14), the group comprising: a first pair of piezo resistors (P1), comprising a first piezo resistor (R1) and a second piezo resistor (R2) near the edge of the membrane (figures 9, 10, and 14), and positioned such that center points of the first pair of piezo resistors are located on the membrane (paragraph 119, figure 14), a second pair of piezo resistors (P3), comprising a third piezo resistor (R5) and a fourth piezo resistor (R6) at a position where applied pressure causes reduced surface stress compared to surface stress at the position of the first and the second piezo resistor (interpreted as the position of P3 relative to P1, figure 14), wherein the first and the third piezo resistor (R1 and R5) are substantially orthogonal to the second and the fourth piezo resistor (R2 and R4, figures 9, 10, and 14), wherein the semiconductor pressure sensor is configured such that a signal from the first piezo resistor and a signal from the second piezo resistor, corrected with a signal from the third piezo resistor and a signal from the fourth piezo resistor (paragraph 120), are used as a measure of a pressure on the membrane (paragraph 121-122).
With respect to claim 2, Van Der Wiel ‘235 teaches wherein the four piezo resistors form a point symmetric layout (figure 14).
With respect to claim 3, Van Der Wiel ‘235 teaches wherein the first piezo resistor and the third piezo resistor are positioned symmetrically with respect to a mirror line parallel with the edge of the membrane (figure 14), and wherein the second piezo resistor and the fourth piezo resistor are positioned symmetrically with respect to a mirror line parallel with the edge of the membrane (figure 14).
With respect to claims 6 and 7, Van Der Wiel ‘235 teaches wherein the piezo resistors of the group of neighboring piezo resistors are connected to a common node (P1 and P3 are connected to common nodes, figure 14), and wherein the common node is connected to the substrate (figure 14).
With respect to claim 8, Van Der Wiel ‘235 teaches wherein the semiconductor pressure sensor is configured for applying, per piezo resistor, a predefined current through the piezo resistors (paragraphs 133).
With respect to claim 9, Van Der Wiel ‘235 teaches, wherein the predefined current is the same for each piezo resistor (paragraph 133).
With respect to claims 10 and 12, Van Der Wiel ‘235 teaches wherein the signals from the piezo resistors are voltages across the piezo resistors and wherein the semiconductor pressure sensor is configured for obtaining the measure of the pressure on the membrane by calculating the voltage across the second piezo resistor minus the voltage across the first piezo resistor plus the voltage across the third piezo resistor minus the voltage across the fourth piezo resistor (a voltage differential value from the bridge circuits is determined to determine pressure, paragraph 119).
With respect to claim 13, Van Der Wiel ‘235 teaches wherein the semiconductor pressure sensor comprises a current source per piezo resistor wherein each current source is connected to a separate piezo resistor or wherein the semiconductor pressure sensor comprises a single current source wherein the semiconductor pressure sensor is configured for switching the current source between at least some of the piezo resistors (the first through fourth current sources, paragraphs 132-133).
With respect to claim 14, Van Der Wiel ‘235 teaches wherein the neighboring piezo resistors are present in a quarter of the membrane (the piezoresistors R1, R2, R5, R6 are in a quarter of the membrane, figure 14).
Allowable Subject Matter
Claims 4 and 5 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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FREDDIE KIRKLAND III
Primary Examiner
Art Unit 2855
/Freddie Kirkland III/Primary Examiner, Art Unit 2855 3/4/2026