Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
Claims 1-2 and 4-15 are pending and Claim 3 is canceled in response to the claim amendments filed 06/02/2026.
Response to Applicant’s Remarks
With respect to 35 U.S.C. §102 rejections:
Applicant’s remarks filed 06/02/2026 have been fully considered but are not persuasive. Applicant argues that Chiu fails to teach “the cool down module being of an extreme heat dissipation type for performing extreme heat dissipation on the main circuit element ... wherein when the cool down module cools down the main circuit element, the temperature sensor detects a peripheral temperature of the peripheral circuit element, and wherein when the temperature control module determines the peripheral temperature is lower than the target temperature, the temperature control module control the temperature of the temperature changing module to heat up the peripheral circuit element to reach the target temperature”. Applicant particularly argues that the temperature reduction in Chiu results merely from passive environmental cooling during system inactivity. Chiu neither discloses nor suggests that the temperature decrease is caused by operation of a cooling module that actively performs heat dissipation on another component…the presently claimed invention is directed to a coordinated temperature compensation mechanism in which active extreme cooling of a main circuit element causes unintended cooling of adjacent peripheral circuit elements, and the system dynamically compensates for such cooling by selectively heating the peripheral circuit elements. Chiu does not disclose or suggest such an arrangement. See Remarks at 8-9.
Examiner disagrees. Applicant's argument that Chiu fails to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., the temperature decrease is caused by operation of a cooling module that actively performs heat dissipation on another component and a coordinated temperature compensation mechanism in which active extreme cooling of a main circuit element causes unintended cooling of adjacent peripheral circuit elements, and the system dynamically compensates for such cooling by selectively heating the peripheral circuit elements) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). As such, Chiu teaches the amended limitations “the cool down module being of an extreme heat dissipation type for performing extreme heat dissipation on the main circuit element ... wherein when the cool down module cools down the main circuit element, the temperature sensor detects a peripheral temperature of the peripheral circuit element, and wherein when the temperature control module determines the peripheral temperature is lower than the target temperature, the temperature control module control the temperature of the temperature changing module to heat up the peripheral circuit element to reach the target temperature” as follows.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 3-6 and 9-15 are rejected under 35 U.S.C. 102(a)(1) and/or (a)(2) as being anticipated by Chiu et al. (US-2022/0413573-A1).
With respect to claim 1, Chiu teaches a temperature adjustment module (temperature control circuit of a compute device 100, figs.1-3), comprising:
a temperature changing module (a temperature control element 106-1 includes a switch 212-1 being controlled to adjust the temperature of the hardware component 208-1 being provided in a zone of the compute device 100, fig.6), comprising a temperature changing area (the compute device 100 provides the zone of localized heating of hardware component 208-1 to ensure operation within a target temperature range, [0059]; and the compute device 100 is also subjected to cold weather conditions or hot weather conditions, [0035]), wherein the temperature changing module is in contact with a peripheral circuit element on a mother board through the temperature changing area and a heat conduction material (the temperature control element 106-1 includes the switch 212-1 is in contact with the hardware component 208-1 through the zone of localized heating of hardware component 208-1 to ensure operation within a target temperature range, fig. 6 and [0059]; the hardware component 208-1 includes a super I/O circuit, fig.6 and [0026]); and
a temperature control module comprising a microcontroller unit (compute device 100 includes a controller 104, figs.1 and 3), electrically connected to the temperature changing module, and configured to control a temperature of the temperature changing module to reach a target temperature (controller 104 is connected to the plurality of temperature control elements 106-1 and 106-2 includes plurality of switches 212-1 and 212-2, fig.6; the controller 104 may close a switch circuit [212] to provide a temperature control element 106 with an electric current…where the temperature control element 106 is a heating element, the electric current heats up the heating element…then warms up the hardware components [208] to prevent the hardware components [208] from reaching a non-operational temperature, [0027]; the compute device 100 provides zones of localized heating of hardware components 208 to ensure operation within a target temperature range, [0059]),
a cool down module on a main circuit element of the mother board (a temperature control element 106-2 includes switch 212-2 being controlled to adjust the temperature of the hardware component 208-2 being provided in a zone of the compute device 100, fig.6; the hardware component 208-2 on the compute device 100 includes system-on-chip circuit, fig.6 and [0026]), wherein the cool down module being of an extreme heat dissipation type for performing extreme heat dissipation on the main circuit element (the temperature control element (106) is a cooling element, such as a fan, the electric current may cause the fan blades to rotate. While particular reference is made to certain temperature control elements (106) such as a thin-film resistor and a fan, other heating and cooling elements may be implemented, such as a liquid-cooled cooling element [0027]); and
a temperature sensor, disposed in the temperature changing area, and electrically connected to the temperature control module (thermal sensor 102-1 disposed within the zone of localized heating of the hardware component 208-1 and connected to the controller 104, fig.3; the thermal sensor 102 may be a contact sensor that touches the hardware component. In an example, the thermal sensor 102 may be a thermocouple or a thermistor which contacts the hardware component of which the temperature is to be taken… the thermal sensor 102 may be a thermally sensitive resistor, which is an electrical resistance component that is sensitive to temperature change [0028]);
wherein the temperature changing module (plurality of temperature control elements 106-1 and 106-2 includes plurality of switches 212-1 and 212-2, fig.6) further comprises a printed circuit board in the temperature changing area (it has been interpreted that the switch 212 (i.e., MOSFET, [0043]) and the temperature control element 106 require to be soldered onto a PCB in order to connect to a motherboard of the compute device 100 that also includes the controller 104, the power supply 210, and the hardware components 208, fig.6), and the temperature of the temperature changing module is changed by at least one of a winding wire or an electronic component on the printed circuit board (the temperatures of the components 208 are changed based on the plurality of temperature control elements 106-1 and 106-2 includes plurality of switches 212-1 and 212-2 being in closed circuit [0044] or opened circuit [0063]; the plurality of temperature control elements 106-1 and 106-2 are heating elements, where the electric current heats up the heating elements…then warms up the hardware components [208], [0027]; each of the temperature control element 106 include two plastic sheets covered by a metal coil, [0042]; each of the temperature control elements 106-1 and 106-2 may be activated at the same and/or different temperatures and may be individually controlled, [0060]),
wherein when the cool down module cools down the main circuit element, the temperature sensor detects a peripheral temperature of the peripheral circuit element (as the different hardware components (208) may cool down or heat up at different temperatures, independently controlled temperature control elements (106) provide for customized and flexible temperature control of different hardware components (208) found in a compute device (100), fig.6 and [0056]; the temperature control elements (106) may be heating elements. In this example, the different heating elements may be individually activated, and in some examples at different temperature thresholds. For example, the controller (104) may close a first switch (212-1) to activate the first heating element, when an output of the first thermal sensor (102-1) indicates that the first hardware component (208-1) has a temperature of 10° C. By comparison, the controller (104) may close a second switch (212-2) to activate the second heating element, when an output of the second thermal sensor (102-1) indicates that the first hardware component (208-1) has a temperature of 15° C. In another example, the threshold temperatures that trigger activation of the respective heating elements may be the same. Similarly, the controller (104) may deactivate the respective heating elements at either the same threshold or different thresholds, [0055]), and
wherein when the temperature control module determines the peripheral temperature is lower than the target temperature, the temperature control module control the temperature of the temperature changing module to heat up the peripheral circuit element to reach the target temperature (the threshold temperature against which the measured temperature is compared is a lower bound operational temperature range for the hardware component… the measured temperature from the thermal sensor 102 may be compared against the threshold temperature of 10° C. and a heating element may be activated [0029]; the threshold temperature may be a buffered lower bound threshold of the operational temperature range for the hardware component. In this example, rather than identifying when the measured temperature falls below 10° C., the controller (104) may determine when the measured temperature falls below 15° C. and may activate the heating element at that point [0030]).
With respect to claim 4, Chiu teaches wherein the cool down module cools down the main circuit element to a first temperature, and the first temperature is lower than or equal to the target temperature (the compute device 100 is in a sleep state that these hardware components may cool to below the lower bound temperature threshold or the other cooling components of the compute device 100 are inactive, [0034]).
With respect to claim 5, Chiu teaches wherein the temperature changing module also comprises: a plurality of temperature changing areas, configured to contact a plurality of peripheral circuit elements through the heat conduction material (fig.6 teaches different zones for the plurality of hardware components 20-1,208-28 within the compute device 100 through temperature control elements 106-1 and 106-2, [0054-0059]).
With respect to claim 6, Chiu teaches wherein at least a part of the temperature changing areas corresponds to different target temperatures (the temperature control elements 106-1 and 106-2 may be activated at the same and/or different temperatures and may be individually controlled, [0060]).
With respect to claim 9, Chiu teaches wherein the temperature control module (controller 104, fig.6) is disposed on the mother board (disposed on the motherboard of the compute device 100, fig.6), and the temperature control module is electrically connected to the temperature changing module through a connection line (the controller 104 is connected to the temperature control elements 106-1,106-2 via different switches 212-1 and 212-2, fig.6).
With respect to claim 10, Chiu teaches wherein the temperature control module (controller 104, fig.6) is electrically connected to a plurality of temperature changing modules through a plurality of connection lines (the controller 104 is connected to the plurality of temperature control elements 106-1 and 106-2 includes plurality of switches 212-1 and 212-2 in different zones of localized heating of hardware components 208 to ensure operation within a target temperature range, fig.6 and [0059]).
With respect to claim 11, Chiu teaches wherein the temperature control module (controller 104, fig.6) is disposed on an external circuit board (the controller 104 may be separate from the CPU of the compute device 100, [0034]), and the temperature control module is electrically connected to the temperature changing module through a connection line (the controller 104 is connected to plurality of temperature control elements 106-1 and 106-2 includes plurality of switches 212-1 and 212-2 in different zones of localized heating of hardware components 208 to ensure operation within a target temperature range, fig.6 and [0059]).
With respect to claim 12, Chiu teaches wherein the temperature control module (controller 104, fig.6) is electrically connected to a plurality of temperature changing modules through a plurality of connection lines (the controller 104 is connected to plurality of temperature control elements 106-1 and 106-2 includes plurality of switches 212-1 and 212-2 in different zones of localized heating of hardware components 208 to ensure operation within a target temperature range, fig.6 and [0059]).
With respect to claim 13, Chiu teaches wherein the temperature control module and the temperature changing module are disposed on a same circuit board (the controller 104 and the plurality of temperature control elements 106-1 and 106-2 includes plurality of switches 212-1 and 212-2 are disposed on the same circuit board of the compute device 100, fig.6), and the temperature control module is electrically connected to the temperature changing module through a connection line (the controller 104 is connected to plurality of temperature control elements 106-1 and 106-2 includes plurality of switches 212-1 and 212-2 in different zones of localized heating of hardware components 208 to ensure operation within a target temperature range, fig.6 and [0059]).
With respect to claim 14, Chiu teaches wherein the main circuit element performs an overclocking operation (a hardware component may initially be at a temperature that is lower than the operational temperature range for the hardware component or may initially be at a temperature that is higher than the operational temperature range for the hardware component. As such, the hardware component and/or the compute device may not operate as intended, or may not operate at all. As such, the present specification describes a compute device that regulates the temperature of hardware components of a compute device to ensure that the hardware components are in a target operational range to perform their intended function, even when the compute device is in a sleep state, [0016]).
With respect to claim 15, Chiu teaches wherein the main circuit element comprises at least one of a central processing unit chip, a graphics processing unit chip, and a memory module (hardware components 208 that may be found on the compute device 100 include an embedded controller, a GPU, a CPU, and a memory device among others are interpreted to be disposed on the circuit board of the computing device 100, fig.6 and [0026]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Chiu et al. (US-2022/0413573-A1).
With respect to claims 7-8, Chiu teaches wherein the peripheral circuit element and the main circuit element are disposed on a circuit board (hardware components 208 that may be found on the compute device 100 include an embedded controller, a GPU, a CPU, and a memory device among others are interpreted to be disposed on the circuit board of the computing device 100, fig.6 and [0026]). Chiu does not appear to teach that the peripheral circuit element (Chiu: memory, [0026]) and the main circuit element (Chiu: CPU, [0026]) are disposed on a same side of a same circuit board or on different sides of a same circuit board.
However, it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teaching to solder two different hardware components (Chiu: CPU and memory, [0026]) on the same side of the same circuit board or on the different sides of the same circuit board for the purpose of common design choice in ultra-thin laptops ultra-thin laptops and single-board computers to minimize device thickness and improve signal integrity. This configuration allows the memory to be placed in extremely close proximity to the CPU, reducing interference and enabling higher clock speeds.
Allowable Subject Matter
Claim 2 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The prior art of record, taken alone or in combination, fails to disclose or render obvious, which makes the following claims allowable over the prior art:
With respect to claim 2, wherein the temperature adjustment module also comprises: a metal thermostat, disposed between the temperature changing module and the peripheral circuit element, wherein a first contact area between the metal thermostat and the peripheral circuit element is greater than a second contact area between the metal thermostat and the temperature changing module.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HIEN (CINDY) D KHUU whose telephone number is (571)272-8585. The examiner can normally be reached on Monday-Friday 9am-5:30pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ken Lo can be reached on 571-272-9774. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/HIEN D KHUU/Primary Examiner, Art Unit 2116 July 10, 2026