Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The disclosure is objected to because of the following informalities: - paragraph [0013], lines 3-4 recites, “This mode register may include settings which allow a user to how many additional parity bits…” There is a word missing between “to” and “how”. It seems the word could be “specify” since the following sentence is, “For example a user may specific no additional bits…”- paragraph [0029], line 2, page 9 recites, “bi register”. It appears this should state “bits register.
Appropriate correction is required.
Claim Objections
Claim 7 recites the limitation "the error correction circuit" in lines 1-2. There is insufficient antecedent basis for this limitation in the claim. It should be amended to read, “the error correction code circuit” to accurately refer back to the claimed “error correction code circuit” in claim 1.
Claims 2 and 6 are objected to because of the following informalities: claim 2, line 3 – “to ECC column plane” should be “to the ECC column plane”claim 6, line 2 – “a number of number of” should have one of the “number of” instances removed. claim 15 – the claim is missing an “and” before the last “writing a second portion…” limitation. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 17 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Referring to claim 17, the claim recites, “enabling the second portion of the plurality of parity bits based on a mode register setting.” In this context, the word “enabling” is interpreted to mean “to cause to operate” (https://www.merriam-webster.com/dictionary/enabling). However, given the wording of claim 15 in which claim 17 is dependent on, “the second portion of the plurality of parity bits” are always “enabled” as part of “writing…to the memory array as part of a second access pass.” Therefore, it is not clear what additional “enabling” claim 17 is providing.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, 7, and 15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2013/0024748 A1 to Sharon et al (herein referred to as Sharon).
Referring to claim 1, Sharon discloses an apparatus (Figure 12) comprising: an error correction code (ECC) circuit configured to receive a plurality of data bits and generate a plurality of parity bits as part of a write operation (Figure 12, ECC engine 1308); and a memory array comprising a plurality of data column planes and an ECC column plane (Figure 12, memory 1204 & [0090] describes multi-plane flash memory devices which includes data and ECC columns), wherein a first portion of the plurality of parity bits are written to the ECC column plane and wherein the plurality of data bits and a second portion of the plurality of parity bits are written to the plurality of data column planes ((claims 1 & 9; Figure 16 & paragraphs [0178-0185] describe storing encoded data in two portions, steps 1606/1608).
Referring to claim 2, Sharon discloses wherein the plurality of data bits are written to the plurality of data column planes and the first portion of the plurality of parity bits are written to ECC column plane as part of a first access pass on the memory array and wherein the second portion of the plurality of parity bits are written to the plurality of data column planes as part of a second access pass on the memory array (claims 1 & 9, Figure 16, & paragraphs [0178-0185] describe storing encoded data in two portions, steps 1606/1608 which is performed in two passes).
Referring to claim 7, Sharon discloses wherein as part of a read operation the error correction circuit is configured to perform single error correction, double error detection (SECDED) based on the plurality of data bits and the plurality of parity bits (paragraph [0050], discloses “When one of the sub-codes 131-138 is uncorrectable because a number of bit errors in the sub-code exceeds a correction capability of the sub-code's ECC scheme” which would include correcting a bit, but detecting more than one).
Referring to claim 15, Sharon discloses a method (Figure 12 runs the method of Figure 16 per [0178] comprising: receiving a plurality of data bits as part of a write operation (claims 1 & 9; Figure 1, paragraphs [0178-0185]); generating a plurality of parity bits based on the plurality of data bits (claims 1 & 9; Figure 1, paragraphs [0178-0185]); writing the plurality of data bits and a first portion of the plurality of parity bits to a memory array as part of a first access pass (claims 1 & 9; Figure 1, paragraphs [0178-0185]); writing a second portion of the plurality of parity bits to the memory array as part of a second access pass (claims 1 & 9, Figure 1, paragraphs [0178-0185] describe storing encoded data in two portions, steps 1606/1608, each step is considered a separate “access pass”).
Allowable Subject Matter
Claims 8-14 are allowed.
Claims 3-6 and 16-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims as well as rewritten or amended to overcome the claim objections and/or rejection(s) under 35 U.S.C. 112(b), set forth in this Office action.
The following is a statement of reasons for the indication of allowable subject matter: Regarding claims 8-12, the prior art of record has not taught, either individually or in combination, and together with all other claimed features an apparatus comprising a mode register comprising a setting which specifies a number of extra parity bits; and wherein the specified number of extra parity bits are written to a memory array as part of a second pass.
Conclusion
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Justin R. Knapp
Primary Examiner
Art Unit 2112
/JUSTIN R KNAPP/Primary Examiner, Art Unit 2112