Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 2, 4, 5, 7-13, and 15-19 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by US 2023/0393937 A1 to Oboukhov et al (herein Oboukhov).
Referring to claim 1, Oboukhov discloses an apparatus comprising: a memory array (Figure 3, memory 306) configured to provide data bits and a plurality of parity bits responsive to a first type of read command or a second type of read command, wherein the memory array provides a first number of the plurality of parity bits responsive to the first type of read command or a second number of the plurality of parity bits greater than the first number responsive to the second type of read command (Figure 3, circuitry 300 executes the method depicted in Figure 9; a first command, step 910 provides a first number of plurality of parity bits, step 918; upon decode failure, a second read command reads an extended parity matrix, step 934 for decoding, step 936). an error correction code (ECC) circuit (Figure 3, ECC processor 334) configured to correct one or more errors in the data bits based on the plurality of parity bits (Figure 9, steps 918, 924, 936).
Referring to claim 2, Oboukhov discloses wherein responsive to the first type of read command the ECC circuit is configured to correct one bit of error in the data, and wherein responsive to the second type of read command the ECC circuit is configured to detect and/or correct more than one bit of error in the data (Figure 9, step 918 decodes at least one bit error of data and step 936 decodes using an extended parity matrix which includes more than one bit of error correction).
Referring to claim 4, Oboukhov discloses wherein responsive to the first type of read command the data and the plurality of parity bits are read as part of a single access pass of the memory array and responsive to the second type of read command the data and the plurality of parity bits are read as part of two access passes of the memory array (Figure 9, steps 910-924 would be a first access pass if decoding is a success; steps 910-924 plus steps 928-936 would be a two access pass if initial decoding fails).
Referring to claim 5, Oboukhov discloses wherein responsive to the second type of read command a portion of the plurality of parity bits is read as part of a first access pass and a remainder of the plurality of parity bits and the data is read as part of a second access pass (Figure 9, first pass parity would be steps 916/918 and second pass parity would be steps 930/934).
Referring to claim 7, Oboukhov discloses wherein the ECC circuit is configured to provide an error detected signal responsive to correcting the one or more errors and wherein a controller is configured to provide the second type of read command responsive to the error detected signal (Figure 9, step 924 represents an error detected signal which the circuitry 300 to provide reading extended parity bits in steps 928-936).
Referring to claim 8, Oboukhov discloses a system comprising: a controller (Figure 3, 300) configured to provide a first type of read command or a second type of read command; and a memory device comprising: a memory array configured to provide data and parity bits responsive to the first type of read command or the second type of read command wherein there is a first number of parity bits responsive to the first type of read command and a second number of parity bits responsive to the second type of read command; and an error correction code (ECC) circuit configured to perform a first level of error correction on the data responsive to the first type of read command and to perform a second level of error correction on the data responsive to the second type of read command, wherein more errors are detected or corrected in the second level of error correction than in the first (this claim is rejected similar to the rejection of claim 1 above; Figure 3, circuitry 300 executes the method depicted in Figure 9; a first command, step 910 provides a first number of plurality of parity bits, step 918; upon decode failure, a second read command reads an extended parity matrix, step 934 for decoding, step 936).
Referring to claim 9, Oboukhov discloses wherein the memory is configured to provide an error detected signal if an error is detected or corrected by the ECC circuit, and wherein the controller is configured to provide the second type of read command responsive to the error detected signal (Figure 9, step 924 represents an error detected signal which the circuitry 300 to provide reading extended parity bits in steps 928-936).
Referring to claim 10, Oboukhov discloses wherein the controller is configured to provide the data along with a write command, and wherein the ECC circuit is configured to generate the parity bits based on the data (it is inherent that stored data is stored as directed by a write command, ECC circuit depicted in Figure 3, ECC processor 334 & Parity selector 336).
Referring to claim 11, Oboukhov discloses wherein the ECC circuit is configured to generate the second number of parity bits responsive to the write command, and wherein the first number of the parity bits represents a portion of the second number of parity bits )ECC circuit depicted in Figure 3, ECC processor 334 & Parity selector 336).
Referring to claim 12, Oboukhov discloses wherein the ECC circuit comprises: a first ECC engine configured to provide the first number of parity bits responsive to the write command; and a second ECC engine configured to provide the second number of parity bits responsive to the write command, wherein the first number of parity bits are read responsive to the first type of read command and the second number of parity bits are read responsive to the second type of read command (ECC circuit depicted in Figure 3, ECC processor 334 includes “engines” as parity matrix 334.1, 334.2, etc. & Parity selector 336).
Referring to claim 13, Oboukhov discloses wherein the first level of error correction is single error correction (SEC) (ECC circuit, parity matrix 334.1 can be designed to correct a single error or more).
Referring to claim 15, Oboukhov discloses a method comprising: receiving a read command which is a first type of read command or a second type of read command; reading a first number of parity bits and a plurality of data bits responsive to the first type of read command; performing a first level of error correction on the plurality of data bits based on the first number of parity bits; reading a second number of parity bits and the plurality of data bits responsive to the second type of read command; and performing a second level of error correction on the plurality of data bits based on the second number of parity bits (Figure 9 depicts the claimed method and as explained in similarly rejected claim 1 above).
Referring to claim 16, Oboukhov discloses further comprising: sending the first type of read command from a controller to a memory; receiving the plurality of data bits and a signal indicating that an error was detected in the plurality of data bits from the memory; and sending the second type of read command from the controller to the memory responsive to the signal (Figure 9, step 924 represents an error detected signal which the circuitry 300 to provide reading extended parity bits in steps 928-936).
Referring to claim 17, Oboukhov discloses further comprising sending the first type of read command and the second type of read command along with a same row address and column address (inherent the row/column address would be the same since both commands are related to the same read data).
Referring to claim 18, Oboukhov discloses wherein the second level is greater than the first level (Figure 9, the extended parity matrix, step 934 is greater than primary parity matrix, step 918).
Referring to claim 19, Oboukhov discloses performing single error correction as the first level of error correction; and performing single error correction double error detection, double error correction, or triple error correction as the second level of error correction (the designed primary parity matrix and extended parity matrix are equivalent to the claimed error correction levels).
Allowable Subject Matter
Claims 3, 6, 14, and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Justin Knapp whose telephone number is (571)270-3008. The examiner can normally be reached 8:00 am - 4:30 pm (ET).
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Justin R. Knapp
Primary Examiner
Art Unit 2112
/JUSTIN R KNAPP/Primary Examiner, Art Unit 2112