Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is in response to the application filed on 02/27/2024.
Claims 1-19 are pending.
Claim Rejections – 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-19 are rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject matter.
Claim 1, this claim is within at least one of the four categories of patent eligible subject matter as it is directing to a method claim under Step 1.
1. A processor implemented method for source code verification, the method comprising:
receiving via one or more hardware processor, a source code further comprising a plurality of function properties to be verified;
slicing by using at least one sequence slicer among a plurality of sequence slicers executed via the one or more hardware processors, the source code into a plurality of slices, wherein the sequence slicer includes at least one of a slice analyzer and a shallow slicer;
extracting by a feature vector generator executed via the one or more hardware processors, a plurality of feature vectors from each slice among the plurality of slices based on a true boolean value, a false boolean value and a plurality of boolean features, wherein each of the plurality of feature vectors indicates syntax and semantics of the source code;
generating by a neural network executed via the one or more hardware processors, a plurality likelihood of success values by applying a plurality of verification techniques over each feature vector among the plurality of feature vectors, wherein an input node in the neural network represents each feature vector, and an output node represents a likelihood of success value generated of each verification technique corresponding to the input node;
predicting a verification strategy by the neural network executed via the one or more hardware processors, by sorting the plurality of likelihood of success values of each verification technique corresponding to each feature vector in decreasing order and applying the verification strategy over each slice to be verified; and
displaying via the one or more hardware processors, a verification result as one of a verification successful (S) when each slice is successfully verified by the verification strategy, a verification failure (F) when each slice is verified by the verification strategy and at least one of the plurality of function properties fails in each slice, and an unknown (U) when each slice is not verified for the verification strategy run out of time or memory.
Regarding claim 1, the limitations “slicing… the source code into a plurality of slices,” “extracting… a plurality of feature vectors from each slice among the plurality of slices based on a true boolean value, a false boolean value and a plurality of boolean features, wherein each of the plurality of feature vectors indicates syntax and semantics of the source code,” “generating…a plurality likelihood of success values by applying a plurality of verification techniques over each feature vector among the plurality of feature vectors, wherein an input node in the neural network represents each feature vector, and an output node represents a likelihood of success value generated of each verification technique corresponding to the input node,” and “predicting a verification strategy…by sorting the plurality of likelihood of success values of each verification technique corresponding to each feature vector in decreasing order and applying the verification strategy over each slice to be verified” as drafted, are functions that, under its broadest reasonable interpretation, recite the abstract idea of a mental process. For example, the claim recites limitations that could align with mental process, e.g., analyzing code syntax/semantics, predicting strategies via sorting likelihoods or organizing human activities for selecting verification technique or human performed code review. A person can mentally evaluate code features, assign success probabilities, and prioritize strategies. Therefore, these limitations encompass a human mind carrying out the function through observation, evaluation judgment and/or opinion, or even with the aid of pen and paper. Thus, these limitations recite and falls within the “Mental Processes” grouping of abstract ideas under Prong 1.
Under Prong 2, the additional elements “using at least one sequence slicer among a plurality of sequence slicers executed via the one or more hardware processors,” “wherein the sequence slicer includes at least one of a slice analyzer and a shallow slicer,” “by a feature vector generator executed via the one or more hardware processors,” “by a neural network executed via the one or more hardware processors,” and “by the neural network executed via the one or more hardware processors” are recited at a high-level of generality such that it amounts no more than mere instructions for executing/applying for predicting source code verification which merely using generic computing equipment to execute the software tools to perform the abstract idea. See MPEP 2106.05(f). For the additional elements “receiving via one or more hardware processor, a source code further comprising a plurality of function properties to be verified” “displaying via the one or more hardware processors, a verification result as one of a verification successful (S) when each slice is successfully verified by the verification strategy, a verification failure (F) when each slice is verified by the verification strategy and at least one of the plurality of function properties fails in each slice, and an unknown (U) when each slice is not verified for the verification strategy run out of time or memory” do nothing more than to add insignificant extra solution activity to the judicial exception of merely gathering/displaying data for verification. See MPEP § 2106.05(h).
Under Step 2B, the claims do not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements of “using at least one sequence slicer among a plurality of sequence slicers executed via the one or more hardware processors,” “wherein the sequence slicer includes at least one of a slice analyzer and a shallow slicer,” “by a feature vector generator executed via the one or more hardware processors,” “by a neural network executed via the one or more hardware processors,” and “by the neural network executed via the one or more hardware processors” amount to no more than mere instructions, or generic computer and/or computer components to carry out the exception, thus, cannot amount to an inventive concept. See MPEP 2105.06(f). For the additional elements “receiving via one or more hardware processor, a source code further comprising a plurality of function properties to be verified” “displaying via the one or more hardware processors, a verification result as one of a verification successful (S) when each slice is successfully verified by the verification strategy, a verification failure (F) when each slice is verified by the verification strategy and at least one of the plurality of function properties fails in each slice, and an unknown (U) when each slice is not verified for the verification strategy run out of time or memory” the courts have recognized storing and retrieving information in memory as a well‐understood, routine, and conventional functions in a merely generic manner (e.g., at a high level of generality) or an insignificant extra-solution activity, Berkheimer v. HP, Inc., 881 F.3d 1360, 1368, 125 USPQ2d 1649, 1654 (Fed. Cir. 2018)). See MPEP 2106.05(d). Accordingly, the claims are not patent eligible under 35 USC 101.
2. The processor implemented method as claimed in claim 1, wherein the plurality of boolean features comprises a goto label in the source code, a goto label in loop, an unstructured forward-backward edges in loop, if array modified in loop, a constant reset in loop, a linear acceleration in loop, a linear acceleration intensive loop, a self-recurrence in loop, a mutual-recurrence in loop, a too-many if else in the source code, a non-linear operation in loop, a non-linear operations intensive loop, a non-linear operations in assertion, a no-loop, a small-known bound loop, a known-max bound loop, an unknown-bound loop, an infinite-loop, a multiple loop, a nested loop, and a recursive source code.
The limitations for this claim further recite an additional mental process under prong 1.
3. The processor implemented method as claimed in claim 1, wherein the true boolean value is updated in each feature vector when the plurality of boolean features are present in each feature vector.
The limitations for this claim further recite an additional mental process under prong 1.
4. The processor implemented method as claimed in claim 1, wherein the false boolean value is updated in each feature vector when the plurality of boolean features are absent in each feature vector.
The limitations for this claim further recite an additional mental process under prong 1.
5. The processor implemented method as claimed in claim 1, wherein the neural network translates each feature vector into the plurality of likelihood of success values corresponding to the verification technique.
The limitations for this claim further recite an additional mental process under prong 1.
6. The processor implemented method as claimed in claim 1, wherein the verification strategy is predicted by sorting the plurality of likelihood of success values in decreasing order and applying the verification strategy to verify each slice among the plurality of slices.
The limitations for this claim further recite an additional mental process under prong 1.
Claim 7, this claim is within at least one of the four categories of patent eligible subject matter as it is directing to a system claim under Step 1.
7. A system for source code verification, comprising:
a memory storing instructions;
one or more communication interfaces; and
one or more hardware processors coupled to the memory via the one or more communication interfaces, wherein the one or more hardware processors are configured by the instructions to:
receive a source code further comprising a plurality of function properties to be verified;
slice by using at least one sequence slicer among a plurality of sequence slicers, the source code into a plurality of slices, wherein the sequence slicer includes at least one of a slice analyzer and a shallow slicer;
extract by a feature vector generator a plurality of feature vectors from each slice among the plurality of slices based on a true boolean value, a false boolean value and a plurality of boolean features, wherein each of the plurality of feature vectors indicates syntax and semantics of the source code;
generate by a neural network a plurality likelihood of success values by applying a plurality of verification techniques over each feature vector among the plurality of feature vectors, wherein an input node in the neural network represents each feature vector, and an output node represents a likelihood of success value generated of each verification technique corresponding to the input node;
predict a verification strategy by the neural network by sorting the plurality of likelihood of success values of each verification technique corresponding to each feature vector in decreasing order and applying the verification strategy over each slice to be verified; and
display a verification result as one of a verification successful (S) when each slice is successfully verified by the verification strategy, a verification failure (F) when each slice is verified by the verification strategy and at least one of the plurality of function properties fails in each slice, and an unknown (U) when each slice is not verified for the verification strategy run out of time or memory.
Regarding claim 7, the limitations “slice … the source code into a plurality of slices,” “extract … a plurality of feature vectors from each slice among the plurality of slices based on a true boolean value, a false boolean value and a plurality of boolean features, wherein each of the plurality of feature vectors indicates syntax and semantics of the source code,” “generate …a plurality likelihood of success values by applying a plurality of verification techniques over each feature vector among the plurality of feature vectors, wherein an input node in the neural network represents each feature vector, and an output node represents a likelihood of success value generated of each verification technique corresponding to the input node,” and “predict a verification strategy …by sorting the plurality of likelihood of success values of each verification technique corresponding to each feature vector in decreasing order and applying the verification strategy over each slice to be verified” as drafted, are functions that, under its broadest reasonable interpretation, recite the abstract idea of a mental process. For example, the claim recites limitations that could align with mental process, e.g., analyzing code syntax/semantics, predicting strategies via sorting likelihoods or organizing human activities for selecting verification technique or human performed code review. A person can mentally evaluate code features, assign success probabilities, and prioritize strategies. Therefore, these limitations encompass a human mind carrying out the function through observation, evaluation judgment and/or opinion, or even with the aid of pen and paper. Thus, these limitations recite and falls within the “Mental Processes” grouping of abstract ideas under Prong 1.
Under Prong 2, the additional elements “a memory storing instructions; one or more communication interfaces; and one or more hardware processors coupled to the memory via the one or more communication interfaces, wherein the one or more hardware processors are configured by the instructions to:,” “using at least one sequence slicer among a plurality of sequence slicers,” “wherein the sequence slicer includes at least one of a slice analyzer and a shallow slicer,” “by a feature vector generator,” and “by a neural network” are recited at a high-level of generality such that it amounts no more than mere instructions for executing/applying for predicting source code verification which merely using generic computing equipment to execute the software tools to perform the abstract idea. See MPEP 2106.05(f). For the additional elements “receive a source code further comprising a plurality of function properties to be verified” “display a verification result as one of a verification successful (S) when each slice is successfully verified by the verification strategy, a verification failure (F) when each slice is verified by the verification strategy and at least one of the plurality of function properties fails in each slice, and an unknown (U) when each slice is not verified for the verification strategy run out of time or memory” do nothing more than to add insignificant extra solution activity to the judicial exception of merely gathering/displaying data for verification. See MPEP § 2106.05(h).
Under Step 2B, the claims do not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements of “a memory storing instructions; one or more communication interfaces; and one or more hardware processors coupled to the memory via the one or more communication interfaces, wherein the one or more hardware processors are configured by the instructions to:,” “using at least one sequence slicer among a plurality of sequence slicers,” “wherein the sequence slicer includes at least one of a slice analyzer and a shallow slicer,” “by a feature vector generator,” and “by a neural network” amount to no more than mere instructions, or generic computer and/or computer components to carry out the exception, thus, cannot amount to an inventive concept. See MPEP 2105.06(f). For the additional elements “receive a source code further comprising a plurality of function properties to be verified” “display a verification result as one of a verification successful (S) when each slice is successfully verified by the verification strategy, a verification failure (F) when each slice is verified by the verification strategy and at least one of the plurality of function properties fails in each slice, and an unknown (U) when each slice is not verified for the verification strategy run out of time or memory” the courts have recognized storing and retrieving information in memory as a well‐understood, routine, and conventional functions in a merely generic manner (e.g., at a high level of generality) or an insignificant extra-solution activity, Berkheimer v. HP, Inc., 881 F.3d 1360, 1368, 125 USPQ2d 1649, 1654 (Fed. Cir. 2018)). See MPEP 2106.05(d). Accordingly, the claims are not patent eligible under 35 USC 101.
8. The system of claim 7, wherein the plurality of boolean features comprises a goto label in the source code, a goto label in loop, an unstructured forward-backward edges in loop, if array modified in loop, a constant reset in loop, a linear acceleration in loop, a linear acceleration intensive loop, a self-recurrence in loop, a mutual-recurrence in loop, a too-many if else in the source code, a non-linear operation in loop, a non-linear operations intensive loop, a non-linear operations in assertion, a no-loop, a small-known bound loop, a known-max bound loop, an unknown-bound loop, an infinite-loop, a multiple loop, a nested loop, and a recursive source code.
The limitations for this claim further recite an additional mental process under prong 1.
9. The system of claim 7, wherein the true boolean value is updated in each feature vector when the plurality of boolean features are present in each feature vector.
The limitations for this claim further recite an additional mental process under prong 1.
10. The system of claim 7, wherein the false boolean value is updated in each feature vector when the plurality of boolean features are absent in each feature vector.
11. The system of claim 7, wherein the neural network translates each feature vector into the plurality of likelihood of success values corresponding to the verification technique.
The limitations for this claim further recite an additional mental process under prong 1.
12. The system method of claim 7, wherein the verification strategy is predicted by sorting the plurality of likelihood of success values in decreasing order and applying the verification strategy to verify each slice among the plurality of slices.
The limitations for this claim further recite an additional mental process under prong 1.
Claim 13 this claim is within at least one of the four categories of patent eligible subject matter as it is directing to a medium claim under Step 1.
13. One or more non-transitory machine-readable information storage mediums comprising one or more instructions which when executed by one or more hardware processors cause:
receiving a source code further comprising a plurality of function properties to be verified;
slicing by using at least one sequence slicer among a plurality of sequence slicers, the source code into a plurality of slices, wherein the sequence slicer includes at least one of a slice analyzer and a shallow slicer;
extracting by a feature vector generator, a plurality of feature vectors from each slice among the plurality of slices based on a true boolean value, a false boolean value and a plurality of boolean features, wherein each of the plurality of feature vectors indicates syntax and semantics of the source code;
generating by a neural network, a plurality likelihood of success values by applying a plurality of verification techniques over each feature vector among the plurality of feature vectors, wherein an input node in the neural network represents each feature vector, and an output node represents a likelihood of success value generated of each verification technique corresponding to the input node;
predicting a verification strategy by the neural network, by sorting the plurality of likelihood of success values of each verification technique corresponding to each feature vector in decreasing order and applying the verification strategy over each slice to be verified; and
displaying a verification result as one of a verification successful (S) when each slice is successfully verified by the verification strategy, a verification failure (F) when each slice is verified by the verification strategy and at least one of the plurality of function properties fails in each slice, and an unknown (U) when each slice is not verified for the verification strategy run out of time or memory.
Regarding claim 13, the limitations “slicing… the source code into a plurality of slices,” “extracting … a plurality of feature vectors from each slice among the plurality of slices based on a true boolean value, a false boolean value and a plurality of boolean features, wherein each of the plurality of feature vectors indicates syntax and semantics of the source code,” “generating …a plurality likelihood of success values by applying a plurality of verification techniques over each feature vector among the plurality of feature vectors, wherein an input node in the neural network represents each feature vector, and an output node represents a likelihood of success value generated of each verification technique corresponding to the input node,” and “predicting a verification strategy …by sorting the plurality of likelihood of success values of each verification technique corresponding to each feature vector in decreasing order and applying the verification strategy over each slice to be verified” as drafted, are functions that, under its broadest reasonable interpretation, recite the abstract idea of a mental process. For example, the claim recites limitations that could align with mental process, e.g., analyzing code syntax/semantics, predicting strategies via sorting likelihoods or organizing human activities for selecting verification technique or human performed code review. A person can mentally evaluate code features, assign success probabilities, and prioritize strategies. Therefore, these limitations encompass a human mind carrying out the function through observation, evaluation judgment and/or opinion, or even with the aid of pen and paper. Thus, these limitations recite and falls within the “Mental Processes” grouping of abstract ideas under Prong 1.
Under Prong 2, the additional elements “One or more non-transitory machine-readable information storage mediums comprising one or more instructions which when executed by one or more hardware processors cause,” “using at least one sequence slicer among a plurality of sequence slicers,” “wherein the sequence slicer includes at least one of a slice analyzer and a shallow slicer,” “by a feature vector generator,” and “by a neural network” are recited at a high-level of generality such that it amounts no more than mere instructions for executing/applying for predicting source code verification which merely using generic computing equipment to execute the software tools to perform the abstract idea. See MPEP 2106.05(f). For the additional elements “receiving a source code further comprising a plurality of function properties to be verified” and “displaying a verification result as one of a verification successful (S) when each slice is successfully verified by the verification strategy, a verification failure (F) when each slice is verified by the verification strategy and at least one of the plurality of function properties fails in each slice, and an unknown (U) when each slice is not verified for the verification strategy run out of time or memory” do nothing more than to add insignificant extra solution activity to the judicial exception of merely gathering/displaying data for verification. See MPEP § 2106.05(h).
Under Step 2B, the claims do not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements of “One or more non-transitory machine-readable information storage mediums comprising one or more instructions which when executed by one or more hardware processors cause,” “using at least one sequence slicer among a plurality of sequence slicers” “wherein the sequence slicer includes at least one of a slice analyzer and a shallow slicer” “by a feature vector generator” and “by a neural network” amount to no more than mere instructions, or generic computer and/or computer components to carry out the exception, thus, cannot amount to an inventive concept. See MPEP 2105.06(f). For the additional elements “receiving a source code further comprising a plurality of function properties to be verified” and “displaying a verification result as one of a verification successful (S) when each slice is successfully verified by the verification strategy, a verification failure (F) when each slice is verified by the verification strategy and at least one of the plurality of function properties fails in each slice, and an unknown (U) when each slice is not verified for the verification strategy run out of time or memory” the courts have recognized storing and retrieving information in memory as a well‐understood, routine, and conventional functions in a merely generic manner (e.g., at a high level of generality) or an insignificant extra-solution activity, Berkheimer v. HP, Inc., 881 F.3d 1360, 1368, 125 USPQ2d 1649, 1654 (Fed. Cir. 2018)). See MPEP 2106.05(d). Accordingly, the claims are not patent eligible under 35 USC 101.
14. The one or more non-transitory machine-readable information storage mediums of claim 13, wherein the plurality of boolean features comprises a goto label in the source code, a goto label in loop, an unstructured forward-backward edges in loop, if array modified in loop, a constant reset in loop, a linear acceleration in loop, a linear acceleration intensive loop, a self-recurrence in loop, a mutual-recurrence in loop, a too-many if else in the source code, a non-linear operation in loop, a non-linear operations intensive loop, a non-linear operations in assertion, a no-loop, a small-known bound loop, a known-max bound loop, an unknown-bound loop, an infinite-loop, a multiple loop, a nested loop, and a recursive source code.
The limitations for this claim further recite an additional mental process under prong 1.
15. The one or more non-transitory machine-readable information storage mediums of claim 13, wherein the true boolean value is updated in each feature vector when the plurality of boolean features are present in each feature vector.
The limitations for this claim further recite an additional mental process under prong 1.
16. The one or more non-transitory machine-readable information storage mediums of claim 13, wherein the false boolean value is updated in each feature vector when the plurality of boolean features are absent in each feature vector.
The limitations for this claim further recite an additional mental process under prong 1.
17. The one or more non-transitory machine-readable information storage mediums of claim 13, wherein the neural network translates each feature vector into the plurality of likelihood of success values corresponding to the verification technique.
The limitations for this claim further recite an additional mental process under prong 1.
18. The one or more non-transitory machine-readable information storage mediums of claim 13, wherein the verification strategy is predicted by sorting the plurality of likelihood of success values in decreasing order and applying the verification strategy to verify each slice among the plurality of slices.
The limitations for this claim further recite an additional mental process under prong 1.
19. The one or more non-transitory machine-readable information storage mediums of claim 13, wherein the verification strategy is predicted by sorting the plurality of likelihood of success values in decreasing order and applying the verification strategy to verify each slice among the plurality of slices.
The limitations for this claim further recite an additional mental process under prong 1.
Reasons for Allowance
Please note the claims are only allowable if applicants overcome the 101 rejections above.
The following is an examiner’s statement of reasons for allowance:
The invention generally relates to source code verification, particularly, to method and system for source code verification using machine learning based strategy prediction. The cited prior art taken alone or in combination fail to teach the method/system includes in part the following steps
“…a plurality of feature vectors from each slice among the plurality of slices based on a true boolean value, a false boolean value and a plurality of boolean features, wherein each of the plurality of feature vectors indicates syntax and semantics of the source code; generating by a neural network executed via the one or more hardware processors, a plurality likelihood of success values by applying a plurality of verification techniques over each feature vector among the plurality of feature vectors, wherein an input node in the neural network represents each feature vector, and an output node represents a likelihood of success value generated of each verification technique corresponding to the input node; predicting a verification strategy by the neural network executed via the one or more hardware processors, by sorting the plurality of likelihood of success values of each verification technique corresponding to each feature vector in decreasing order and applying the verification strategy over each slice to be verified; and displaying via the one or more hardware processors, a verification result as one of a verification successful (S) when each slice is successfully verified by the verification strategy, a verification failure (F) when each slice is verified by the verification strategy and at least one of the plurality of function properties fails in each slice, and an unknown (U) when each slice is not verified for the verification strategy run out of time or memory” as recited in claim 1,
“…a plurality of feature vectors from each slice among the plurality of slices based on a true boolean value, a false boolean value and a plurality of boolean features, wherein each of the plurality of feature vectors indicates syntax and semantics of the source code; generate by a neural network a plurality likelihood of success values by applying a plurality of verification techniques over each feature vector among the plurality of feature vectors, wherein an input node in the neural network represents each feature vector, and an output node represents a likelihood of success value generated of each verification technique corresponding to the input node; predict a verification strategy by the neural network by sorting the plurality of likelihood of success values of each verification technique corresponding to each feature vector in decreasing order and applying the verification strategy over each slice to be verified; and display a verification result as one of a verification successful (S) when each slice is successfully verified by the verification strategy, a verification failure (F) when each slice is verified by the verification strategy and at least one of the plurality of function properties fails in each slice, and an unknown (U) when each slice is not verified for the verification strategy run out of time or memory” as recited in claim 7 and
“…a plurality of feature vectors from each slice among the plurality of slices based on a true boolean value, a false boolean value and a plurality of boolean features, wherein each of the plurality of feature vectors indicates syntax and semantics of the source code; generating by a neural network, a plurality likelihood of success values by applying a plurality of verification techniques over each feature vector among the plurality of feature vectors, wherein an input node in the neural network represents each feature vector, and an output node represents a likelihood of success value generated of each verification technique corresponding to the input node; predicting a verification strategy by the neural network, by sorting the plurality of likelihood of success values of each verification technique corresponding to each feature vector in decreasing order and applying the verification strategy over each slice to be verified; and displaying a verification result as one of a verification successful (S) when each slice is successfully verified by the verification strategy, a verification failure (F) when each slice is verified by the verification strategy and at least one of the plurality of function properties fails in each slice, and an unknown (U) when each slice is not verified for the verification strategy run out of time or memory” as recited in claim 13.
The above-quoted claim language is not taught or suggested by the Applied Art below (whether considered individually or in any combination).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Related cited arts:
Fang, Chunrong, et al. "Functional code clone detection with syntax and semantics fusion learning." Proceedings of the 29th ACM SIGSOFT international symposium on software testing and analysis. 2020.pp. 516-527.
Le, Triet HM, Hao Chen, and Muhammad Ali Babar. "Deep learning for source code modeling and generation: Models, applications, and challenges." ACM Computing Surveys (CSUR) 53.3 (2020): pp. 1-38.
Li, Guangjie, Hui Liu, and Ally S. Nyamawe. "A survey on renamings of software entities." ACM Computing Surveys (CSUR) 53.2 (2020): pp. 1-38.
US 12002055 discloses a system delivers access to remote resources and remote data across geographic regions through a parallel circuit that transfers data between components. The system includes a volatile memory and processors that read to and write to the volatile memory. A computer readable medium storing a program in a non-transitory media provides access to remote resources locally by processing requests received from different computer devices remote from the processors from a publicly accessible distributed network that is addressed by a single address. The system generates routing commands based on a content of a payload, a protocol used to deliver the data, and detections of data types. The system routes requests from different computer devices remote to the processors to intended devices based on the single device address. The different computers includes physical devices and endpoints that sever a plurality of entry points for accessing a cloud.
US 11520345 discloses in various examples, a path perception ensemble is used to produce a more accurate and reliable understanding of a driving surface and/or a path there through. For example, an analysis of a plurality of path perception inputs provides testability and reliability for accurate and redundant lane mapping and/or path planning in real-time or near real-time. By incorporating a plurality of separate path perception computations, a means of metricizing path perception correctness, quality, and reliability is provided by analyzing whether and how much the individual path perception signals agree or disagree. By implementing this approach—where individual path perception inputs fail in almost independent ways—a system failure is less statistically likely. In addition, with diversity and redundancy in path perception, comfortable lane keeping on high curvature roads, under severe road conditions, and/or at complex intersections, as well as autonomous negotiation of turns at intersections, may be enabled.
US 20220248148 discloses a method and hearing device (100) for emulating cochlear processing of auditory stimuli are disclosed, in which a multilayer convolutional encoder-decoder neural network (10) sequentially compresses and then decompresses a time-domain input comprising a plurality of samples. At least one nonlinear unit for applying a nonlinear transformation is mimicking a level-dependent cochlear filter tuning associated with cochlear mechanics and outer hair cells. Other described modules cover inner-hair-cell and auditory-nerve fiber processing. A plurality of shortcut connections (15) is directly forwarding inputs between convolutional layers of the encoder (11) and the decoder (12). An output layer (14) is generating, for each input to the neural network, N output sequences of cochlear response parameters corresponding to N emulated cochlear filters associated with N different center frequencies to span a cochlear tonotopic place-frequency map. A transducer (105) of the hearing device converts output sequences generated by the neural network (10) into auditory-stimulus dependent audible time-varying pressure signals, or basilar-membrane vibrations, inner-hair-cell potentials, auditory-nerve firing patterns or population coding thereof for auditory or augmented hearing applications.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Satish Rampuria whose telephone number is 571-272-3732. The examiner can normally be reached on Monday-Friday from 8:30 AM to 5:00 PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chat Do, can be reached at telephone number 571-272-3721. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Satish Rampuria/Primary Examiner, Art Unit 2193
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