Prosecution Insights
Last updated: April 19, 2026
Application No. 18/588,510

FORCE DISTRIBUTION SENSOR

Non-Final OA §112
Filed
Feb 27, 2024
Examiner
RAEVIS, ROBERT R
Art Unit
2855
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Japan Display Inc.
OA Round
1 (Non-Final)
83%
Grant Probability
Favorable
1-2
OA Rounds
2y 9m
To Grant
99%
With Interview

Examiner Intelligence

Grants 83% — above average
83%
Career Allow Rate
1543 granted / 1857 resolved
+15.1% vs TC avg
Strong +16% interview lift
Without
With
+15.6%
Interview Lift
resolved cases with interview
Typical timeline
2y 9m
Avg Prosecution
73 currently pending
Career history
1930
Total Applications
across all art units

Statute-Specific Performance

§101
1.7%
-38.3% vs TC avg
§103
41.2%
+1.2% vs TC avg
§102
5.9%
-34.1% vs TC avg
§112
37.2%
-2.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1857 resolved cases

Office Action

§112
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . 35 USC 112(B) REJECTION Claims 1-13 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. As to claims 1,3,4,6,7,8,9,10, the phrase “array substrate” is confusing, as it’s not clear how the adjective “array” further limits the substrate. What structurally distinguishes an “array substrate” from a mere substrate? What array-like structure/feature is attributed and an “array” substrate? As to claims 1,9,10, the phrase “array electrodes” is confusing, as it not clear how each electrode is an array oriented. How does the adjective “array” further define an electrode? Isn’t an electrode by itself an electrode? As to claim 3, the recessed part 7 is of an embodiment (Figure 9) that does not include the second region 80 of sheet 40 (of embodiment Figure 2) where the sheet 40 is bonded to the installation surface 6 of claim 1. In effect, Applicant is mixing features of 2 different embodiments (Figure 1 & Figure 9). As to claim 4, the spacer 8 is of an embodiments (Figure 10) that does not include the second region 80 (of embodiment Figure 2) where the sheet 40 is bonded to the installation surface 6 of claim 1. In effect, Applicant is mixing features of 2 different embodiments (Figure 1 & Figure 10). As to claim 10, it’s not clear what “integrates” (line 2 from last) means in the context of the claim (and even application). The component 140 part 142 appears to clamp (per Para 81, Pub) the sensor sheet 130 to the installation surface 6; yet Para 60 (Pub) suggest that integrate means that two separate elements (i.e. “sheets”) are then “one sheet” (Para 60). As such, it is not clear what structure is actually integrated in claim 10. Claim 10’s calling for “an outside region” being integrated is confusing because the outside region is merely one component (i.e. sensor sheet 130), so what is the “outside region” (which relates to the sheet) as a whole integrated with? The difficulty is that the term integrate seems to have a different meanings: (1) one for the layer 131 and material 132 being integrated to result in “one sheet” (Para 60), and the other (2) for claim 10’s “outside region” (line 5 from last, claim 10) being integrated to … what? What is the “outside region” (claim 10) connected to as a whole (if anything) to provide for an integrated element? Is the ”outside region” integrated to the installation surface 6? Maybe, the detachable component actually integrates the “sensor base material” (line 12) and “sensor layer” (line 14), but that is not what claim 10 calls for. (Note: The single term integrate need have one definition for the entire disclosure, and that additional confusion may result if same term is provided with different definitions in the same application) PRIOR ART NOT APPLIED The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Rosenberg et al CN 105934733 teach (Figure 33) a touch sensor array (TSA) of force sensors, and makes reference to a protective upper layer (per Applicant’s claim 1), but otherwise lacks specifics on what the covers are connected to (per Applicant’s claim 1), and any detachable fixation component (for the sensors per Applicant’s claims 9,10). Filiz et al AU 2015100011 teach (Figure 2B) pressure sensitive components 212,222 on a stack 230, in array configuration. There is a cover 106 (Figure 1). However, the reference otherwise lacks specifics on what the cover is connected to (per Applicant’s claim 1), and any detachable fixation component the sensor components per Applicant’s claims 9,10). Huang CN 115144106 teaches (Figure 1) a force sensor that employs a flexible protective film 1; electrode layer 2, flexible micro structure/microporous sensing substrate 3, second electrode layer 5. The protective film 1 does not overlap (per claim 1), and the sensor layer does not overlap electrode layer (per claims 9,10). Liu CN 11156238 teach (Figure 1) pressure sensitive layer 104 between electrodes 102,106, and flexible substrates 101,107. CONCLUSION Any inquiry concerning this communication or earlier communications from the examiner should be directed to ROBERT R RAEVIS whose telephone number is (571)272-2204. The examiner can normally be reached on Mon to Friday from 8am to 4pm. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kristina DeHerrera, can be reached at telephone number 303-297-4237. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from Patent Center. Status information for published applications may be obtained from Patent Center. Status information for unpublished applications is available through Patent Center to authorized users only. Should you have questions about access to the USPTO patent electronic filing system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). Examiner interviews are available via a variety of formats. See MPEP § 713.01. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) Form at https://www.uspto.gov/InterviewPractice. /ROBERT R RAEVIS/ Primary Examiner, Art Unit 2855
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Prosecution Timeline

Feb 27, 2024
Application Filed
Mar 05, 2026
Non-Final Rejection — §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
83%
Grant Probability
99%
With Interview (+15.6%)
2y 9m
Median Time to Grant
Low
PTA Risk
Based on 1857 resolved cases by this examiner. Grant probability derived from career allow rate.

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