DETAILED ACTION
Claims 1-15 are pending in the case. Claims 1 and 10 are independent claims.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgement is made of Applicant’s claim for foreign priority of Korean application KR10-2024-0027213 filed on February 26, 2024. It is noted, however, that applicant has not filed a certified copy of the KR10-2024-0027213 application as required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on February 27, 2024 is in compliance with the provisions of 37 CFR 1.97 and 1.98. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character(s) not mentioned in the description:
FIGS. 3 and 4: Reference character #150.
FIGS. 6-8: Reference character #150.
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they do not include the following reference sign(s) mentioned in the description:
Computer system 10 is mentioned in reference to FIGS. 3 and 4, but not depicted in the drawing.
The drawings are further objected for failing to comply with 37 CFR 1.84(a)(1) and 37 CFR 1.84(I), which requires the drawings be in black, and that all drawings be made by a process which will give them satisfactory reproduction characteristics. Every line, number, and letter must be durable, clean, solid black (except for color drawings), sufficiently dense and dark, and uniformly thick and well-defined. The weight of all lines and letters must be heavy enough to permit adequate reproduction. This requirement applies to all lines however fine, to shading, and to lines representing cut surfaces in sectional views. Zooming in to the figures shows pixelation, which is a sign that these drawings weren't drawn in black.
Corrected drawing sheets in compliance with 37 CFR 1.121(d), or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The abstract of the disclosure is objected to because the abstract is longer than 150 words in length. A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b).
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
The disclosure is objected to because of the following informalities:
[0039]: In line 3, did the Applicant intend to add “not” before “limited”?
[0050]: In line 7, move “may be consecutive” to directly after “16 to 256 burst beats”.
[0062]: In lines 5 and 6, change “base address (sram_inst_addr)” to “base address (sram_inst_base)”.
[0063]: In lines 2 and 3, change “base address (sram_inst_addr)” to “base address (sram_inst_base)”.
Appropriate correction is required.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Such limitations are:
Claim 8, lines 1-2: “a process for fetching the next instruction from the on-chip memory to the instruction cache”.
Prong A: “a process” is a substitute for “means” that is a generic placeholder.
Prong B: “a process for” is the generic placeholder “a process” modified by functional language “for”.
Prong C: “a process for” is not modified by sufficient structure, material, or acts for performing the claimed function.
Claim 8, lines 2-4: “a process for fetching data required for execution of the instructions from main memory to the on-chip memory”.
Prong A: “a process” is a substitute for “means” that is a generic placeholder.
Prong B: “a process for” is the generic placeholder “a process” modified by functional language “for”.
Prong C: “a process for” is not modified by sufficient structure, material, or acts for performing the claimed function.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
The act/algorithm for the claim limitation of Claim 8, lines 2-4, mentioned above can be found in the following:
Claim 8, lines 2-4: “a process for fetching data required for execution of the instructions from main memory to the on-chip memory” – The act/algorithm is mentioned in paragraph [0058] of the disclosure stating “the processor 100 may transmit a DMA instruction (or request) including information necessary for fetching an instruction block, such as the size and address of an instruction block to be fetched and an address of a destination (the SRAM 160), to the DMA controller. The DMA controller may fetch an instruction block corresponding to the DMA instruction from the memory 200 to the SRAM 160.”
Examiner interprets the act of “a process for fetching data required for execution of the instructions from main memory to the on-chip memory” as a processor sending a DMA instruction/request to a DMA controller, and the controller fetching an instruction block of the claimed data required for execution of the instructions from memory 200 to SRAM 160.
For the above claim limitation recited in Claim 8, lines 1-2, a sufficient act/algorithm has not been disclosed in the specification.
Claim 8, lines 1-2: “a process for fetching the next instruction from the on-chip memory to the instruction cache” – The disclosure fails to describe the acts/algorithms for performing the “process for fetching…from the on-chip memory to the instruction cache” in the computer system. Paragraphs [0053-0057] of the disclosure discuss utilizing a scheduling algorithm for predicting data flow of the artificial intelligence model and fetching the instruction block from the SRAM 160 corresponding to an execution flow predicted based on a data flow of the artificial intelligence model, depicted in Figure 5. However, this fails to be more specific regarding the finite sequence of steps of the scheduling algorithm (See MPEP 2181(II)(B)) or the execution flow prediction used for “a process for fetching the next instruction from the on-chip memory to the instruction cache”.
Therefore, Examiner is taking the broadest reasonable interpretation (BRI) and 112(a) and 112(b) rejections are made below.
Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application also includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are:
Claim 3, lines 3-4: “an address adjuster adjusting the first address to the second address”
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
For the above claim limitation recited in Claim 3, sufficient structure has not been disclosed in the specification. For Claim 3, lines 3-4: “an address adjuster adjusting the first address to the second address” – The disclosure fails to describe structure for the “address adjuster” of the processor. The disclosure fails to be more specific regarding what the physical hardware contents are that cause “an address adjuster” to adjust the first address to the second address.
Therefore, Examiner is taking the broadest reasonable interpretation (BRI) and 112(a) and 112(b) rejections are made below.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 112(a)
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 3-4 and 8 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. As described above in the “Claim Interpretation” section, the disclosure does not provide adequate structure to perform the claimed functions performed by the “address adjuster” recited in Claim 3 and the “process for fetching the next instruction from the on-chip memory to the instruction cache” of Claim 8. The specification does not demonstrate that applicant has made an invention that achieves the claimed functions because the invention is not described with sufficient detail such that one of ordinary skill in the art can reasonably conclude that the inventor had possession of the claimed invention.
Examiner suggests rewording Claim 8 to remove the generic placeholder and modified language, “a process for”, such as: “wherein the processor performs fetching the next instruction from the on-chip memory to the instruction cache and fetching data required for execution of the instructions from the main memory to the on-chip memory in parallel”.
Dependent Claim 4 is also rejected under 112(a) due to inheriting the deficiencies of claim 3.
Claim Rejections - 35 USC § 112(b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2-14 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 2, line 4 recites “the adjusted second address”. It is unclear what the “adjusted” second address is referring to. In lines 1-3, a first address is adjusted to a second address. However, there is no mention of a second address being adjusted. For the purpose of examination, Examiner interprets “the adjusted second address” as “the second address”.
Dependent Claims 3-7 are also rejected under 112(b) due to inheriting the deficiencies of claim 2.
Claims 3-4 and 8: Claim limitation “an address adjuster adjusting the first address to the second address” in Claim 3, lines 3-4 and “a process for fetching the next instruction from the on-chip memory to the instruction cache” in Claim 8, lines 1-2 invoke 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. However, as described in the “Claim Interpretation” section above, the written description fails to disclose the corresponding structure, material, or acts for performing the entire claimed function of the “address adjuster” and the “process for fetching the next instruction from the on-chip memory to the instruction cache” and to clearly link the structure, material, or acts to the function.
Therefore, Claims 3 and 8 are indefinite and is rejected under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph.
Dependent Claim 4 is also rejected under 112(b) due to inheriting the deficiencies of claim 3.
Applicant may:
(a) Amend the claim so that the claim limitation will no longer be interpreted as a limitation under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph;
(b) Amend the written description of the specification such that it expressly recites what structure, material, or acts perform the entire claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(c) Amend the written description of the specification such that it clearly links the structure, material, or acts disclosed therein to the function recited in the claim, without introducing any new matter (35 U.S.C. 132(a)).
If applicant is of the opinion that the written description of the specification already implicitly or inherently discloses the corresponding structure, material, or acts and clearly links them to the function so that one of ordinary skill in the art would recognize what structure, material, or acts perform the claimed function, applicant should clarify the record by either:
(a) Amending the written description of the specification such that it expressly recites the corresponding structure, material, or acts for performing the claimed function and clearly links or associates the structure, material, or acts to the claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(b) Stating on the record what the corresponding structure, material, or acts, which are implicitly or inherently set forth in the written description of the specification, perform the claimed function. For more information, see 37 CFR 1.75(d) and MPEP §§ 608.01(o) and 2181.
Claim 5, lines 1-2 recite “the second address for the next instruction”. However, in claim 2, lines 2-3 mention only “a second address”. It is unclear how the second address is tied to the next instruction. For the purpose of examination, Examiner interprets “the second address for the next instruction” as “the second address”.
Dependent Claim 6 is also rejected under 112(b) due to inheriting the deficiencies of claim 5.
Claim 8, line 3 recites “the instructions from the main memory”. However, it is unclear if the instructions are referring to the instructions of claim 1, line 5, “a main memory…loading instructions”, or the “at least some of the instructions…loaded into the main memory” recited in claim 1, lines 8-9. For the purpose of examination, Examiner interprets “the instructions from the main memory” as “the at least some of the instructions from the main memory”.
Claim 11, lines 5-6 recite “the adjusted second address”. It is unclear what the “adjusted” second address is referring to. In lines 3-4, a first address is adjusted to a second address. However, there is no mention of a second address being adjusted. For the purpose of examination, Examiner interprets “the adjusted second address” as “the second address”.
Dependent Claims 12-14 are also rejected under 112(b) due to inheriting the deficiencies of claim 11.
Claim 13, line 3 recites “the second address for the next instruction”. However, in claim 11, line 4 mentions only “a second address”. It is unclear how the second address is tied to the next instruction. For the purpose of examination, Examiner interprets “the second address for the next instruction” as “the second address”.
Dependent Claim 14 is also rejected under 112(b) due to inheriting the deficiencies of claim 13.
Claim 14, line 3 recites “the second address for the next instruction”. However, in claim 11, line 4 mentions only “a second address”. It is unclear how the second address is tied to the next instruction. For the purpose of examination, Examiner interprets “the second address for the next instruction” as “the second address”.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 8, 9, 10 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Hebbar et al (US20140244932A1, herein Hebbar) in view of Kim (US20220138586A1).
Regarding Claim 1, Hebbar teaches a computer system (FIG. 2: semiconductor device 200)
a processor (FIG. 2: CPU 205) comprising an instruction cache (FIG. 2: L1 Cache 218 comprises of L1-I Cache (instruction cache) 220) and an on-chip memory coupled to the instruction cache (FIG. 2: L2 Cache 215); and
a main memory (FIG. 2: Main Memory 210) connected to the processor through a bus (FIG. 2: double sided arrow between Main Memory and CPU) and loading instructions and data (FIG. 2 and [0028]: a CPU 205 is configured to access instructions or data that are stored in the main memory 210; The processor cores 212 may include a bus unit (BU) 214 for managing communication over bridges or buses in the processing system 200), wherein the processor is configured to:
fetch an instruction block including at least some of the instructions a program ([0029]: level 2 (L2) cache 215 for storing copies of instructions or data that are stored in the main memory 210);
fetch at least some of the instructions included in the fetched instruction block from the on-chip memory to the instruction cache and execute the fetched instructions ([0030]: Relative to the L2 cache 215, the L1 cache 218 may be implemented using faster memory elements so that information stored in the lines of the L1 cache 218 can be retrieved quickly by the corresponding processor core 212. The L1 cache 218 may also be deployed logically or physically closer to the processor core 212 (relative to the main memory 210 and the L2 cache 215) so that information may be exchanged between the processor core 212 and the L1 cache 218 more rapidly or with less latency);
check, when a next instruction of a currently executed instruction does not exist in the instruction cache, whether the next instruction exists in the on-chip memory ([0033]: a core 212 first checks its corresponding L1 caches 218, 220, 225 when it needs to retrieve or access an instruction or data. If the request to the L1 caches 218, 220, 225 misses, then the request may be directed to the L2 cache 215, which can be formed of a relatively slower memory element than the L1 caches 218, 220, 225.); and
fetch the next instruction from the on-chip memory to the instruction cache based on a check result ([0042]: If a request for an instruction misses (check result) in the L1 instruction cache, the requested instruction cache line may be fetched from the L2 cache and an instruction cache line may be evicted from the L1 instruction cache to the L2 cache in accordance with a replacement policy to make room for the fetched instruction cache line.).
However, Hebbar does not teach the computing system executing an artificial intelligence model.
Kim teaches a computing system executing an artificial intelligence model ([0008]: artificial neural network (ANN) memory system with a neural processing unit (NPU) optimized for processing an artificial neural network (ANN) model).
It would have been obvious for one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the computing system of Hebbar to include executing an artificial intelligence model. One of ordinary skill would have done this for the benefit of realizing the variety of applications and uses of an artificial intelligence model within the system. Additionally, running an artificial intelligence model in a system that also prioritizes reducing latency between information exchanges between the CPU and memory would allow for the models to be executed more rapidly.
Regarding Claim 8, the combination of Hebbar and Kim teaches the computer system of claim 1, wherein the processor performs a process for fetching the next instruction from the on-chip memory to the instruction cache and a process for fetching data required for execution of *at least some of the instructions (*interpretation based on 112(b) issue) from the main memory to the on-chip memory (See claim 1 rejection).
However, the combination does not explicitly teach the processor performing the processes of fetching in parallel.
Kim teaches a processor performs a process for *fetching instructions from on-chip memory to instruction cache (*BRI based on 112(f) interpretation is “initiating fetching…”) and a process for fetching data for executing *at least some of the instructions (*interpretation based on 112(b) issue) from main memory to on-chip memory in parallel (FIG. 18 and [0683] teach the DRAM, also referred to as main memory, supplies data to the buffer memory (on-chip memory), and the buffer memory streams the data to the NPU, which is comprised of internal memory (cache); [0694-0695]: Even if the DMA controller does not receive a command from the NPU while the PE array of the NPU is performing an operation for inference (in other words: process which initiated a fetch of instructions from on-chip to cache), data may be independently read from the main memory and stored in the buffer memory based on the ANN data locality information (in other words: process for fetching instructions from main memory to on-chip memory); In other words: data can be can be read from main memory to buffer memory while the NPU is performing an operation (using instructions streamed/fetched from buffer memory to internal memory)).
It would have been obvious for one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the combination of Hebbar and Kim to include the processor performing the processes of fetching instructions from on-chip memory to instruction cache and fetching data for executing instructions from main memory to on-chip memory in parallel. One of ordinary skill would have done this for the benefit of efficiently fetching data from both external and internal memory locations. This can also result in a smaller amount of cache misses, since there will be data simultaneously being fetched from main memory to on-chip memory, as well as instructions fetched from on-chip memory to instruction cache. Additionally, performing these processes in parallel can substantially eliminate or reduce the latency of data provided to the processor.
Regarding Claim 9, the combination of Hebbar and Kim teaches the computer system of claim 1.
However, the combination of Hebbar and Kim thus far does not explicitly teach wherein the processor transmits a direct memory access (DMA) request for fetching the instruction block including at least some of the instructions of the artificial intelligence model loaded into the on-chip memory to a DMA controller.
Kim teaches wherein the processor transmits a direct memory access (DMA) request for fetching the instruction block including at least some of the instructions of the artificial intelligence model loaded into the on-chip memory to a DMA controller (FIG. 18 and [0695]: The DMA controller reads the data to be requested by the NPU (processor) based on the ANN data locality information from the main memory before the request from the NPU, and stores it in the buffer memory (on-chip memory). The DMA controller immediately provides the corresponding data stored in the buffer memory when the NPU actually requests the corresponding data).
It would have been obvious for one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the combination of Hebbar and Kim to include wherein the processor transmits a direct memory access (DMA) request for fetching the instruction block including at least some of the instructions of the artificial intelligence model loaded into the on-chip memory to a DMA controller. One of ordinary skill would have done this for the benefit of having a faster data transfer from the external memory to the on-chip memory, reducing the time needed for data processing and storage.
Regarding Claim 10, the combination of Hebbar and Kim teaches a method of minimizing memory traffic delay (Hebbar: FIG. 7) comprising, similar limitations to those recited in claim 1 and is therefore rejected on the same premises.
Regarding Claim 15, the claim recites a method with corresponding limitations to the apparatus of Claim 8, and is therefore rejected on the same premises.
Claims 2-6 and 11-14 are rejected under 35 U.S.C. 103 as being unpatentable over Hebbar et al (US20140244932A1, herein Hebbar) in view of Kim (US20220138586A1), in further view of Vondran (US20020091892A1).
Regarding Claim 2, the combination of Hebbar and Kim teaches the computer system of claim 1, the fetched instruction block and the on-chip memory.
However, the combination does not explicitly teach wherein the processor adjusts a first address related to an instruction included in the fetched instruction block to a second address in the on-chip memory, and provides the adjusted second address to a program counter.
Vondran teaches wherein the processor adjusts a first address related to an instruction included in a fetched instruction block (See FIG. 3 where main memory 310 has a block of instructions with corresponding memory addresses 315 (in other words: first address)) to a second address in an on-chip memory (See FIG. 3 where instruction cache 330 (in other words: on-chip memory) has lines of instructions with corresponding instruction tag entries 335 (in other words: second address)), and provides the *second address (*interpretation based on 112(b) issue) to a program counter (See FIG. 3 where program counter 350 contains the address of the instruction cache address).
It would have been obvious for one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the combination of Hebbar and Kim to include wherein the processor adjusts a first address related to an instruction included in the fetched instruction block to a second address in the on-chip memory, and provides the adjusted second address to a program counter. One of ordinary skill would have done this for the benefit of indicating where in the on-chip memory the next instruction to be executed can be accessed. The processor having access to the next instruction to be executed on-chip eliminates the need to fetch the instruction from main memory, reducing delays in accessing and executing the instruction.
Regarding Claim 3, the combination of Hebbar, Kim and Vondran teaches the computer system of claim 2, wherein the first address is an address included in the main memory.
However, the combination thus far does not explicitly teach the processor further comprises an address adjuster adjusting the first address to the second address.
Vondran teaches the processor further comprises an address adjuster adjusting the first address to the second address (FIG. 4: Memory Address Register 450 with associated increment 455 and branch logic 460).
It would have been obvious for one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the combination of Hebbar, Kim and Vondran to include the processor further comprises an address adjuster adjusting the first address to the second address. One of ordinary skill would have done this for the benefit of being able to indicate where in the on-chip memory the next instruction can be accessed for execution, allowing for efficient performance of instruction execution with minimal delays.
Regarding Claim 4, the combination of Hebbar, Kim and Vondran teaches the computer system of claim 3.
However, the combination thus far does not explicitly teach wherein the address adjuster adjusts the first address to the second address based on a base register storing a base address of the on-chip memory.
Vondran teaches wherein the address adjuster adjusts the first address to the second address based on a base register storing a base address of the on-chip memory ([0035]: the PC (program counter, in other words: base register) is incremented by a fixed amount n (in other words: base address). This amount corresponds to the size of a single entry in the cache so that, when incremented by n, the PC points to the next instruction).
It would have been obvious for one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the combination of Hebbar, Kim and Vondran to include wherein the address adjuster adjusts the first address to the second address based on a base register storing a base address of the on-chip memory. One of ordinary skill would have done this for the benefit of determining if the instruction required next for execution exists in the on-chip memory.
Regarding Claim 5, the combination of Hebbar, Kim and Vondran thus far teaches the computer system of claim 2.
Hebbar further teaches wherein the processor, when the *second address (*interpretation based to 112(b) issue) is included in an address range of the instruction block fetched to the on-chip memory, fetches the next instruction stored in the second address from the on-chip memory to the instruction cache ([0042]: If a request for an instruction misses (check result) in the L1 instruction cache, the requested instruction cache line may be fetched from the L2 cache and an instruction cache line may be evicted from the L1 instruction cache to the L2 cache in accordance with a replacement policy to make room for the fetched instruction cache line.).
Regarding Claim 6, the combination of Hebbar, Kim and Vondran teaches the computer system of claim 5.
Hebbar further teaches wherein the processor, when the second address is not included in the address range of the instruction block fetched to the on-chip memory, fetches a new instruction block including the next instruction from the main memory to the on-chip memory, and fetches the next instruction fetched to the on-chip memory to the instruction cache ([0033]: The main memory 210 may be the object of a request in response to cache misses from both the L1 caches 218, 220, 225 and the inclusive L2 cache 215.; [0029]: The L2 cache 215 shown in FIG. 2 is 4-way associative to the main memory 210 so that each line in the main memory 210 can potentially be copied to and from four cache lines (which are conventionally referred to as “ways”) in the L2 cache 215).
Regarding Claims 11, 12, 13 and 14, the claims recite a method with corresponding limitations to the apparatus of Claims 2, 3-4, 5, and 6, respectively, and are therefore rejected on the same premises.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Hebbar et al (US20140244932A1, herein Hebbar) in view of Kim (US20220138586A1), in further view of Vondran (US20020091892A1), in further view of Levitan et al (US6651162B1, herein Levitan).
Regarding Claim 7, the combination of Hebbar, Kim and Vondran teaches the computer system of claim 2, wherein the processor adjusts a first address (See Claim 2 rejection).
However, the combination thus far does not explicitly teach where the first address is corresponding to a target address of a branch instruction.
Levitan teaches the first address is corresponding to a target address of a branch instruction (FIG. 2 and Col. 4, lines 41-46: Branch target address caches (BTAC) 58 is an internal memory which stores the target addresses to a branch of instructions. Thus, if the current address references a branch instruction, the address to the predicted next instruction can be quickly accessed.).
It would have been obvious for one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the combination of Hebbar, Kim and Vondran to include the first address is corresponding to a target address of a branch instruction. One of ordinary skill would have done this for the benefit of providing an on-chip memory address location for the target of the branch instruction. Doing so would reduce the chances of a resulting cache miss.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Black et al (US8032711B2) teaches a system and method for prefetching data from external memory to on-chip memory. Ramrakhyani et al (US20190102310A1) teaches a system comprising of tiered memory for accessing and storing data. Rychlik (US8935517B2) teaches a branch target address cache within a processor that also comprises of instruction cache and external memory. Hinton (US5423014A) teaches instruction-fetch logic that checks if data can be fetched from main memory in parallel with fetching data from on-chip memory.
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/S.V./Examiner, Art Unit 2183
/David J. Huisman/Primary Examiner, Art Unit 2183