NON-FINAL REJECTION, FIRST DETAILED ACTION
Status of Prosecution
The present application, 18/588,749 filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
The application was filed in the Office on February 27, 2024 and claims foreign priority to European Union application EP23162338.0 filed March 16, 2023.
Claims 1-18 are pending and are all rejected. Claims 1, 16, 17 and 18 are independent.
Status of Claims
Claim 16 is objected to.
Claims 1-12 and 14-18 are rejected under 35 U.S.C. § 103 as being unpatentable over non-patent literature Chen et al., (“Chen”), “Hybrid Quantum-Classical Graph Convolutional Network,” published in 2021 in view of Ramesh et al. (“Ramesh”), United States Patent Application Publication 2022/0292675 published on Sep. 15, 2022 in further view of over non-patent literature Saleem et al., (“Saleem”), “Divide and Conquer for Combinatorial Optimization and Distributed Quantum Computation,” published in 2022.
Claims 13 is rejected under 35 U.S.C. § 103 as being unpatentable over Chen in view of Ramesh in view of Saleem in further view of Le Van Gong et al. (“Le Van Gong”), United States Patent Application Publication 2023/0206108 published on June 29, 2023.
Objection
Claim 16 is objected to for what appears to be a typographical error. It recites “the qubit register” without antecedent basis. Correction is required.
Claim Rejection – 35 USC § 103
The following is a quotation of 35 U.S.C. § 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
A.
Claims 1-12 and 14-18 are rejected under 35 U.S.C. § 103 as being unpatentable over non-patent literature Chen et al., (“Chen”), “Hybrid Quantum-Classical Graph Convolutional Network,” published in 2021 in view of Ramesh et al. (“Ramesh”), United States Patent Application Publication 2022/0292675 published on Sep. 15, 2022 in further view of over non-patent literature Saleem et al., (“Saleem”), “Divide and Conquer for Combinatorial Optimization and Distributed Quantum Computation,” published in 2022.
As to Claim 1, Chen teaches: A hybrid quantum-classical computation system for classifying a grid of features provided as an input, the system comprising:
a convolutional block comprising a convolutional filter configured to receive the grid of features as an input and to output a plurality of output features for the grid of features based on a trainable configuration of the convolutional filter (Chen: Fig. 7, Sec. V, the architecture of the system includes graph convolution; Sec. III, the input of a NxN image that can be considered as a graph with N2 nodes; eq. 7, the graph convolution will output an array (i.e. grid) of features based on the convolutional filter);
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a classifying block configured to receive a flattened feature vector and to generate an output classification (Chen: Figs. 8-9, and related discussion in Sec. VI, variational quantum circuit architecture includes two VQC’s that are chained together. The first performs amplitude encoding and the second deals with variational encoding), wherein the classifying block comprises a plurality of independent variational quantum circuits, each comprising a plurality of quantum gates acting on qubits the plurality of quantum gates comprising variational quantum gates (Chen: Figs. 8, 9: IV. B, “In the second VQC block, we employ variational encoding, where the input values are used as the quantum rotation angles. In variational encoding, there is a predefined sequence of single-qubit rotation gates for each qubit.”) wherein the action of a variational quantum gate on the qubits of the qubit register is parametrized according to an associated variational parameter, and encoding gates for modifying a state of the qubits of the qubit register according to an input feature vector (Chen: Figs. 8-9, trainable parameters αi, βi, γi are optimized); and
wherein measured outputs of the plurality of independent variational quantum circuits are combined to determine a label for the grid of input features as the output classification (Chen: Sec. V, the output of the second VQC is processed by a single-layer classical neural network to output the logits for each class (i.e. a label for the grid of input features); Fig. 7, class output).
Chen may not explicitly teach: a flattening layer for transforming the filtered grid of output features received from the convolutional block into a flattened feature vector;
a classifying block configured to receive the flattened feature vector and to generate an output classification, wherein the classifying block comprises a plurality of independent variational quantum circuits, each comprising a plurality of quantum gates acting on qubits of a qubit register of the respective variational quantum circuit, the plurality of quantum gates comprising variational quantum gates, wherein the action of a variational quantum gate on the qubits of the qubit register is parametrized according to an associated variational parameter, and encoding gates for modifying a state of the qubits of the qubit register according to an input feature vector.
Chen does disclose a VQC that has a collection of qubit gates, which may be considered to be a qubit register (Chen: Figs. 8, 9). And while Chen does discuss flattening the input image, it does not have details as to how it is performed (Chen: Fig. 7, the image is flattened).
Ramesh teaches in general concepts related to a bi-directional quantum annealing approach to Markov random field networks for machine learning in image analysis (Ramesh: Abstract). Specifically, Ramesh teaches that feature extraction is committed by processing images using a convolutional neural network interleaved with pooling layers and a flattening layer (Ramesh: par. 0043, Fig. 2).
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It would have been obvious to a person having ordinary skill in the art at a time before the effective filing date of the application to have implemented the Chen disclosures and teachings by utilizing the quantum register and with the feature extraction via the convolutional block and flattening layer as taught and suggested by Ramesh. Such a person would have been motivated to do so with a reasonable expectation of success to for an optimized architecture for classifying and using known convolutional and flattening with quantum registers.
Chen and Ramesh may not explicitly teach: wherein the variational quantum circuits of the plurality of independent variational quantum circuits receive different subsets of features from the flattened feature vector as the input feature vector.
Saleem teaches in general concepts related to a divide and conquer algorithm for quantum optimization (QDCA) to map large combinatorial optimization problems onto distributed quantum architectures (Saleem: Abstract). Specifically, Saleem teaches that a quantum circuit may be cut into fragments that can then be executed independently and recombined via classical post processing (Saleem: Fig. 4).
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It would have been obvious to a person having ordinary skill in the art at a time before the effective filing date of the application to have modified the Chen-Ramesh disclosures and teachings by implementing the VQC’s instead of the serial nature of Chen but instead in parallel and to accept partitioned features as taught and suggested by Saleem. Such a person would have been motivated to do so with a reasonable expectation of success to take advantage of parallel processing for computing resource optimization.
As to Claim 2, Chen, Ramesh and Saleem teach the elements of claim 1.
Saleem further teaches: wherein output states of all qubits in the qubit register of one of the plurality of independent variational quantum circuits are independent from the actions of quantum gates of another one of the plurality of independent variational quantum circuits (Saleem: Sec. 7, “Rather than directly searching for the MIS of the full graph, one can first partition the graph into multiple subgraphs where these subproblems can be solved independently, and then recombine their results to produce a solution over the full graph.”).
As to Claim 3, Chen, Ramesh and Saleem teach the elements of claim 1.
Chen, Ramesh and Saleem as combined further teaches: wherein the variational parameters of one of the plurality of independent variational quantum circuits are different from the variational parameters of another one of the plurality of independent variational quantum circuits (Examiner notes that Chen teaches the trainable parameters are trained in different VQC blocks (though serially); Saleem as combined teaches the use of parallel VQC’s instead).
As to Claim 4, Chen, Ramesh and Saleem teach the elements of claim 1.
Chen further teaches: wherein each of the plurality of independent variational quantum circuits comprises multiple layers of quantum gates (Chen: Figs. 8, 9 show multiple layers of quantum gates).
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As to Claim 5, Chen, Ramesh and Saleem teach the elements of claim 4.
Chen further teaches: wherein each layer of the multiple layers of quantum gates comprises a variational quantum gate for each of the qubits of the qubit register (Examiner notes that the each of the gates have trainable parameters).
As to Claim 6, Chen, Ramesh and Saleem teach the elements of claim 1.
Chen further teaches: wherein the plurality of independent variational quantum circuits is implemented in quantum hardware(Chen: Fig. 7, quantum circuits).
As to Claim 7, Chen, Ramesh and Saleem teach the elements of claim 1.
Ramesh further teaches: wherein the convolutional block and/or the flattening layer is implemented in classical hardware, in particular using a trainable machine learning model (Ramesh: pars. 0027-28, classical computing devices may be used to implement some of the computations; par. 0040, classical and quantum devices may perform the process [200]; step [208] is the processing with convolution and flattening).
As to Claim 8, Chen, Ramesh and Saleem teach the elements of claim 1.
Chen further teaches: wherein the plurality of independent variational quantum circuits each comprise at least two qubits in their respective qubit registers (Chen: Figs. 8, 9 indicate entanglement in the quantum circuit diagram with the Controlled-NOT gate notations with multiple qubits).
As to Claim 9, Chen, Ramesh and Saleem teach the elements of claim 1.
Chen further teaches: wherein each of the plurality of independent variational quantum circuits comprises an entangling gate for entangling quantum states of at least two of the qubits of the respective qubit register (Chen: Figs. 8, 9 indicate entanglement in the quantum circuit diagram with the Controlled-NOT gate notations).
As to Claim 10, Chen, Ramesh and Saleem teach the elements of claim 1.
Saleem further teaches: wherein the quantum states of qubits of different variational quantum circuits of the plurality of independent variational quantum circuits are not entangled prior to measurement (Saleem: Sec. 1, “At one extreme we may utilize no quantum communication between the subproblems, in this case the QDCA will prepare two independent quantum states corresponding to the two subgraphs.” Examiner asserts that there would not be any entanglement between the two different circuits in this instance).
As to Claim 11, Chen, Ramesh and Saleem teach the elements of claim 1.
Chen and Ramesh and Saleem as combined further teaches: wherein trainable parameters of the convolutional block, the flattening layer, and the classifying block are obtained based on a joint training process (Ramesh: Fig. 2, the training and validation with testing data takes place in concert).
As to Claim 12, Chen, Ramesh and Saleem teach the elements of claim 11.
Ramesh further teaches: wherein the joint training process is a process of a machine learning model implemented in classical hardware and the plurality of independent variational quantum circuits is implemented in quantum hardware (Ramesh: pars. 0027-28, classical computing devices may be used to implement some of the computations; par. 0040, classical and quantum devices may perform the process [200]; step [208] is the processing with convolution and flattening).
As to Claim 14, Chen, Ramesh and Saleem teach the elements of claim 1.
Saleem and Ramesh further teaches: wherein the measured outputs of the plurality of independent variational quantum circuits are combined using a trainable layer of artificial neurons implemented in classical hardware (Saleem: Sec. 7, the independent subproblems are recombined classically; Ramesh: par. 0002, the Boltzmann classical machines are neural networks).
As to Claim 15, Chen, Ramesh and Saleem teach the elements of claim 14.
Ramesh further teaches: wherein the trainable layer is a fully connected layer of artificial neurons implemented in classical hardware(Ramesh: par. 0002, the Boltzmann classical machines are neural networks).
As to Claim 16, Chen teaches: A method for determining a label for a grid of input features based on a hybrid quantum-classical computation algorithm, the method comprising:
receiving the grid of input features and generating a filtered grid of features based on the grid of input features and a convolutional filter, wherein the convolutional filter is configured to output a plurality of output features for the grid of input features based on a trainable configuration of the convolutional filter (Chen: Fig. 7, Sec. V, the architecture of the system includes graph convolution; Sec. III, the input of a NxN image that can be considered as a graph with N2 nodes; eq. 7, the graph convolution will output an array (i.e. grid) of features based on the convolutional filter);;
encoding each of vector subsets into qubits of a corresponding variational quantum circuit of a plurality of independent variational quantum circuits, each of the plurality of independent variational quantum circuits comprising an encoding gate configured to act on the quantum states of a qubit based on a feature of the corresponding subset of the plurality of the vector subsets, a variational quantum gate (Chen: Figs. 8-9, and related discussion in Sec. VI, variational quantum circuit architecture includes two VQC’s that are chained together. The first performs amplitude encoding and the second deals with variational encoding), wherein the action of a variational quantum gate on the qubits of the qubit register is parametrized according to an associated variational parameter(Chen: Figs. 8-9, trainable parameters αi, βi, γi are optimized), and an entangling gate for creating a superposition of the quantum states of two qubits of the corresponding circuit (Chen: Figs. 8, 9 indicate entanglement in the quantum circuit diagram with the Controlled-NOT gate notations); and
Chen and Ramesh may not explicitly teach: obtaining measured outputs based on measuring an output state of each of the plurality of independent variational quantum circuits and combining the measured outputs of the plurality of independent variational quantum circuits to determine a corresponding output label (Chen: Sec. V, the output of the second VQC is processed by a single-layer classical neural network to output the logits for each class (i.e. a label for the grid of input features); Fig. 7, class output).
Chen may not explicitly teach: flattening the filtered grid of output features into a flattened feature vector;
separating the flattened feature vector into a plurality of flattened feature vector subsets, and encoding each of the flattened feature vector subsets into qubits of a corresponding variational quantum circuit of a plurality of independent variational quantum circuits, each of the plurality of independent variational quantum circuits comprising an encoding gate configured to act on the quantum states of a qubit based on a feature of the corresponding subset of the plurality of flattened feature vector subsets, a variational quantum gate, wherein the action of a variational quantum gate on the qubits of the qubit register is parametrized according to an associated variational parameter.
Chen does disclose a VQC that has a collection of qubit gates, which may be considered to be a qubit register (Chen: Figs. 8, 9). And while Chen does discuss flattening the input image, it does not have details as to how it is performed (Chen: Fig. 7, the image is flattened).
Ramesh teaches in general concepts related to a bi-directional quantum annealing approach to Markov random field networks for machine learning in image analysis (Ramesh: Abstract). Specifically, Ramesh teaches that feature extraction is committed by processing images using a convolutional neural network interleaved with pooling layers and a flattening layer (Ramesh: par. 0043, Fig. 2).
It would have been obvious to a person having ordinary skill in the art at a time before the effective filing date of the application to have implemented the Chen disclosures and teachings by utilizing the quantum register and with the feature extraction via the convolutional block and flattening layer as taught and suggested by Ramesh. Such a person would have been motivated to do so with a reasonable expectation of success to for an optimized architecture for classifying and using known convolutional and flattening with quantum registers.
Chen and Ramesh may not explicitly teach: obtaining measured outputs based on measuring an output state of each of the plurality of independent variational quantum circuits and combining the measured outputs of the plurality of independent variational quantum circuits to determine a corresponding output label.
Saleem teaches in general concepts related to a divide and conquer algorithm for quantum optimization (QDCA) to map large combinatorial optimization problems onto distributed quantum architectures (Saleem: Abstract). Specifically, Saleem teaches that a quantum circuit may be cut into fragments that can then be executed independently and recombined via classical post processing (Saleem: Fig. 4).
It would have been obvious to a person having ordinary skill in the art at a time before the effective filing date of the application to have modified the Chen-Ramesh disclosures and teachings by implementing the VQC’s instead of the serial nature of Chen but instead in parallel and to accept partitioned features as taught and suggested by Saleem. Such a person would have been motivated to do so with a reasonable expectation of success to take advantage of parallel processing for computing resource optimization.
As to Claim 17, it is rejected for similar reasons as claims 1 and 16. Chen further teaches: determining a parameter update of the variational parameters and the trainable combination parameters based on a value of a loss function for the output label (Chen: Table II discusses training loss measurmenents; Sec. IV.C, training end-to end for each of those combination parameters, “With the knowledge of calculating the quantum function gradients, it becomes straightforward to employ a variety of optimization algorithms developed by the classical ML community [67] and to train the whole hybrid architecture in an end-to-end fashion.”).
As to Claim 18, it is rejected for similar reasons as claim 1. Ramesh further teaches a compute readable medium and a processor (Ramesh: par. 0071).
B.
Claims 13 is rejected under 35 U.S.C. § 103 as being unpatentable over non-patent literature Chen et al., (“Chen”), “Hybrid Quantum-Classical Graph Convolutional Network,” published in 2021 in view of Ramesh et al. (“Ramesh”), United States Patent Application Publication 2022/0292675 published on Sep. 15, 2022 in further view of over non-patent literature Saleem et al., (“Saleem”), “Divide and Conquer for Combinatorial Optimization and Distributed Quantum Computation,” published in 2022 in further Le Van Gong et al. (“Le Van Gong”), United States Patent Application Publication 2023/0206108 published on June 29, 2023.
As to Claim 13, Chen, Ramesh and Saleem teach the elements of claim 1.
Chen, Ramesh and Saleem may not explicitly teach: wherein each of the variational quantum circuits of the plurality of independent variational quantum circuits is configured to encode a number of inputs into the quantum states of the qubits of its qubit register, and the input feature vector comprises a number of features, which is a multiple of the number of inputs of the variational quantum circuits of the plurality of independent variational quantum circuits.
Le Van Gong teaches in general concepts related to dealing with quantum computers with limited number of input qubits while addressing a great number of trainable features (Le Van Gong: Abstract). Specifically, Le Van Gong teaches that the features that are to be computed is divided amongst the variational quantum circuits in a distributed manner by count (Le Van Gong: par. 0090, “The present disclosure overcomes this problem via a divide-and-conquer approach, where the large number of trainable features are divided into a list of feature groups, such that the number of the feature groups is less than or equal to the number of input qubits that can be handled by a quantum computer.”).
It would have been obvious to a person having ordinary skill in the art at a time before the effective filing date of the application to have modified the Chen-Ramesh-Saleem disclosures and teachings by dividing the number of features in the manner taught and suggested by Le Van Gong. Such a person would have been motivated to do so with a reasonable expectation of success to allow for the divide and conquer approach of Saleem for distributed and expanded capability of the hybrid system (Le Van Gong: par. 0090).
Conclusion
Prior art deemed relevant but not cited:
Resch, S., Gutierrez, A., Huh, J. S., Bharadwaj, S., Eckert, Y., Loh, G., ... & Tannu, S. (2021). Accelerating variational quantum algorithms using circuit concurrency. (discussing parallel processing for quantum circuits).
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/JAMES T TSAI/ Primary Examiner, Art Unit 2147
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