DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 8-9, 14, 16-17 and 19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Greenhill et al. (USPN 7,532,003).
With respect to claim 8, Greenhill et al. discloses, in Figs. 3-5,a method (method of operating Fig. 3 further details disclosed in Figs. 4-5) for controlling a load-variance rate (controlling the current consumption/load variance rate of 310 on Vdd) of at which one or more integrated circuits (Vdd is provided to/on the integrated chip of 310, see Col. 4 lines 15-24) vary a load on a voltage regulator (320 which is a DC/DC converter that maintains/regulates a desired voltage level Vdd, see Col. 4 lines 25-33), the method comprising:
sensing a die voltage on a semiconductor die of the one or more integrated circuits (340, 330 and voltage detector that provides the voltage detection of step 560 of Fig. 5, i.e., voltage readout circuitry connected to port 380, see Col. 5 lines 19-26, sense the voltage on the die. Note 310 is an integrated chip and chips have a semiconductor die);
resolving a difference between a setpoint voltage of the voltage regulator and the die voltage (in step 560 of Fig. 5 the difference between the current die voltage and the minimum setpoint is resolved); and
maintaining the load-variance rate at a highest available rate at which the die voltage stays within a predetermined interval of the setpoint voltage (the clock is speed is lowered if the load-variance rate causes the die voltage to be below the minimum voltage level, i.e., the “setpoint voltage”. If the voltage is above the setpoint voltage then the clock is operated at the desired maximum speed. The load variance is speed dependent), the maintaining comprising:
setting the load-variance rate to a first rate based on the difference falling within the predetermined interval of the setpoint voltage of the voltage regulator (If the voltage is above the setpoint voltage, i.e., within the predetermined interval above the minimum voltage, then the clock is operated at the desired maximum speed.; and
setting the load-variance rate to a second rate, lower than the first rate, based on the difference falling outside of the predetermined interval of the setpoint voltage of the voltage regulator (the clock is speed is lowered if the load-variance rate causes the die voltage to be below the minimum voltage level, i.e., outside the “setpoint voltage”) .
With respect to claim 9, the method of claim 8, wherein the steps of sensing the die voltage, resolving the difference, setting the load-variance rate to the first rate, and setting the load-variance rate to the second rate are enacted repeatedly, in a closed-loop manner to maintain the load-variance rate at the highest available rate (the rates are set in the closed loop fashion according to the loop of 560 to 570 to 572 to 520 and then back to 560 via 530, 540 and 550).
With respect to claim 14, the method of claim 8, wherein setting the load-variance rate to the first rate and setting the load-variance rate to the second rate comprise changing a clock speed of a processor or computer-memory system (the speed of the clock of processor 310 is controlled to adjust the load variance rate).
With respect to claim 16, Greenhill et al. discloses, in Figs. 3-5, a system (Fig. 3 construction and operational details disclosed in Figs. 4 and 5) comprising:
a voltage regulator (320 which is a DC/DC converter that maintains/regulates a desired voltage level Vdd, see Col. 4 lines 25-33) configured to regulate a die voltage (Vdd) on a semiconductor die (Vdd is provided to/on the integrated chip of 310, see Col. 4 lines 15-24. An integrated chip has a die and thus Vdd is provided on a semiconductor die);
one or more integrated circuits arranged on the semiconductor die and configured to vary a load on the voltage regulator at a load-variance rate (the processor 310 is a load on 320/Vdd that has a load/current consumption according to the operating speed of the load/310); and
a load-variance manager operatively coupled to the one or more integrated circuits (340, 330 and voltage detector that provides the voltage detection of step 560 of Fig. 5, i.e., voltage readout circuitry connected to port 380, see Col. 5 lines 19-26), the load-variance manager configured to sense the die voltage (see step 560 of Fig. 5) and control the load-variance rate (clock speed which controls the load variance of the processor) in a closed-loop manner (loop of 560 see No of Fig. 5, 570 see Yes, 572 and 520 back to 560) based on the die voltage (based on if the die voltage is above a minimum level in 560) to maintain a highest available load-variance rate at which the die voltage stays within a predetermined interval of a setpoint voltage of the voltage regulator (the clock is speed is lowered if the load-variance rate causes the die voltage to be below the minimum voltage level, i.e., the “setpoint voltage”. If the voltage is above the setpoint voltage then the clock is operated at the desired maximum speed. The load variance is speed dependent. Thus, the circuit operates as claimed).
With respect to claim 17, the system of claim 16, wherein controlling the load-variance rate includes resolving a difference between the setpoint voltage and the die voltage and selecting the load-variance rate based on the difference (in step 560 the difference between the current die voltage and the minimum setpoint is resolved and the speed is selected to be lower in steps 570 and 572 based on the resolved difference).
With respect to claim 19, the system of claim 16, wherein controlling the load-variance rate includes selecting a clock frequency based on whether the die voltage exceeds the predetermined interval of the setpoint voltage (when the predetermined interval of the minimum voltage level is exceeded the clock frequency/speed is selected to be lowered in steps 570 and 572. Alternatively, when the voltage level exceeds in a positive direction, i.e., is above the minimum, the frequency/speed is selected to be maintained).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Greenhill et al. (USPN 7,532,003).
With respect to claim 20, Greenhill et al. discloses that 320 is external to 310. Thus, Greenhill et al. fails to disclose “wherein the voltage regulator is arranged on the die.”
Nevertheless it would have been obvious to place 320 internal to processor 310, since it has been held that forming one piece of an article which has formerly been formed in two pieces and put together involves only routine skill in the art, Howard v. Detroit Stove Works, 150 U.S. 164 (1893). One would have been motivated to do so to for the purpose of reducing the overall size of the circuit/system of Fig. 3.
Allowable Subject Matter
Claims 1-7 are allowed.
Claims 10-13, 15 and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Thomas J. Hiltunen whose telephone number is (571)272-5525. The examiner can normally be reached 9:00AM-5:30PM EST M-F.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Menatoallah Youssef can be reached at (571)270-3684. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/THOMAS J. HILTUNEN/Primary Examiner, Art Unit 2836
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