DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-7 and 16-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
With respect to claim 1, it cannot be determined if the recitation of “a die voltage on the semiconductor die” on line 10 refers to the same or ad different “die voltage” as the recitation of “a die voltage on a semiconductor die” as recited on line 2 of claim 1.
Claims 2-7 are rejected for the same reasons as claim 1.
With respect to claim 16, it cannot be determined if the recitation of “on a semiconductor die” on line 3 refers to the same or ad different “semiconductor die” as the recitation of “on a semiconductor die” as recited on line 2 of claim 16.
Claims 17-20 are rejected for the same reasons as claim 16.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 5-8, 10, 15-16 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (USPN 8,051,307) in view of Gendler et al. (USPN 9,612,613) and in further view of Ihs (USPN 10,139,888).
With respect to claim 1, Huang et al. discloses, in Figs. 2-6, a system (Fig. 3 construction and operational details disclosed in Figs. 2 and 4-6) comprising:
a voltage regulator (22) configured to regulate a voltage supplied to a CPU (Vcore to 31)
the voltage regulator having a setpoint voltage approaching a minimum allowable voltage at full load (see Fig. 4 at Imax, VID-Offset, i.e., the VID signal for Fig. 4 that is sets an optimum Vcore see Col. 3 line 66 to Col. 4 line 29, is set to the “Minimum Voltage”) and a maximum allowable voltage at minimal load (Maximum voltage for VID-Offset/Vcore is set at the minimum load current value, see Fig. 4);
an integrated circuit (CPU 31) connected to the regulator (via Vcore) and configured to vary a load on the voltage regulator at a load-variance rate (CPU causes load variation by its operating conductions under the control of the clock generator and 34, see Col. 4 line 62 to Col. 5 line 24); and
a load-variance manager operatively coupled to the integrated circuit (element that detects the loading current of 31 with 32-33), the load-variance manager configured to:
sense a loading current of the integrated circuit (element that detects loading current of 31);
select a clock frequency based on whether the die voltage exceeds a predetermined interval of the setpoint voltage (33 operates as recited under the control of OC1 and OC2, see also Figs. 5 and 6 which discloses the clock signal frequency changing with the loading current set points); and
set the load-variance rate to a highest available rate at which the die voltage stays within the predetermined interval (the load-variance rate, i.e., loading conditions, are set according to OC1 and OC2 such that the stays within the predetermined interval yet operates with the highest available rate, i.e., “performance”, according to load demand, see Col. 5 lines 7-34 and lines 49-63).
Huang et al. discloses sensing the current demand of a CPU/integrated circuit. However, Huang et al. fails to disclose “sense a die voltage on the semiconductor die” (see sensing loading (current) of Huang et al.).
However, it is old and well-known to generate a current demand sensing signal by sensing “a die voltage on” a “semiconductor” die. This is further evidenced in Fig. 1 of Gendler et al. which discloses a device (103 with 110) for measuring the current demand of a “processor” (e.g., CPU) that is part of a system-on-a-chip (see Col. 3 lines 17-20) which will have a die (i.e., die of the chip, see 102 providing voltage VCCU to the “Die”). Thus current measuring device of 110 senses a die voltage (at least one of VCCU, VCCG and/or the difference between VCCU and VCCG, i.e., VDS) on the semiconductor die (VCCU, VCCD and VDS are all part of/on the “Die”).
It would have been obvious to use the circuit of 103 and 110 of Fig. 1 of Gendler et al. to measure the loading (current) of Huang et al. for the purpose of having a simply constructed current sensing element capable of sensing a current of a CPU/processor element.
Huang et al. fails to explicitly disclose whether or not all of the elements of Fig. 3 are constructed on the same die/chip. Thus, Huang et al. fails to disclose that the regulated voltage (Vcore) is “a die voltage on a semiconductor die” and that the integrated circuit (CPU 31) is “arranged on the semiconductor die”.
However, it is old and well-known to construct all of the elements of a circuit including a CPU/processor and a voltage controller/regulator on the same system-on-chip and therefore on the same die/chip.
This is further evidenced in Fig. 1 of Ihs which discloses a circuit including the CPU/processor (111, see Col. 3 lines 22-25) and a voltage controller/regulator on the same system-on-chip and therefore on the same die/chip (see Col. 2 lines 34-44).
It would have been obvious to construct the voltage controller/regulator and processor/CPU of Huang et al. on the same system-on-chip, and thus the same die, as evidenced by Ihs. Furthermore, it has been held that forming one piece of an article which has formerly been formed in two pieces and put together involves only routine skill in the art, Howard v. Detroit Stove Works, 150 U.S. 164 (1893). One would have been motivated to do so for the purpose of constructing a compact device on the same chip and therefore reducing the amount of separate chips required to construct the circuit of Fig. 2 of Huang et al.
As combined above the sensed die voltage, regulated voltage and CPU are all on the same chip/die.
With respect to claim 5, the system of claim 1, wherein the system is a motherboard of a computer system (motherboard is merely intended use of the CPU system of Huang et al., wherein the CPU of Huang et al. is capable of being operative with/connected to a motherboard. Furthermore, Gendler et al. discloses the known use of a processor on a mother board), and wherein the semiconductor die supports a processor core of the computer system (Fig. 2 supports the processor core of the CPU of Huang et al.).
With respect to claim 6, the system of claim 1, wherein the integrated circuit is configured to change a clock speed of a processor or computer-memory system (via the clock speed control of 33).
With respect to claim 7, the system of claim 1, wherein the integrated circuit is configured to energize or de-energize a power-gated domain (power gating provide by 103 of Gendler, as modified above in Huang et al., which is part of the core/processor and is energized and de-energized according to the amount of current/voltage supplied by the voltage controller/regulator of Huang et al.).
With respect to claim 8, Yun et al. discloses, a method for controlling a load-variance rate (variance of the loading/current draw of 31 of Fig. 3) at which one or more integrated circuits (31) vary a load on a voltage regulator (load one Vcore of 22), the method comprising:
sensing a current of the one or more integrated circuits (the loading current of 31 is sensed/measured, see Figs 4-6);
setting the load-variance rate (e.g. normal rate of Fig. 6 at R2) to a first rate (e.g., Normal/R2) if the current sensed is within a predetermined interval of a setpoint current of the voltage regulator (e.g., between TH2 and TH1 of Fig. 6); and
setting the load-variance rate to a second rate (e.g., Down clock 5% of Fig. 6 at R3), lower than the first rate (lower than the normal frequency rate), if the die current sensed is outside of the predetermined interval of the setpoint current of the voltage regulator (outside TH2 between TH3 and TH2).
Huang et al. discloses sensing the current demand of a CPU/integrated circuit. Huang et al. discloses detection of a current (see sensing loading (current) of Huang et al.) and not a voltage and the setting of current setpoints (see R1-R4 of Fig. 6) and not voltage set points. Thus, Huang et al. fails to disclose “sensing a die voltage on the semiconductor die” and a predetermined “setpoint voltage”.
However, it is old and well-known to generate a current demand sensing signal by sensing “a die voltage on” a “semiconductor” die. This is further evidenced in Fig. 1 of Gendler et al. which discloses a device (103 with 110) for measuring the current demand of a “processor” (e.g., CPU) that is part of a system-on-a-chip (see Col. 3 lines 17-20) which will have a die (i.e., die of the chip, see 102 providing voltage VCCU to the “Die”). Thus current measuring device of 110 senses a die voltage (i.e., VDS associated with VCCD/VCCU) on the semiconductor die (VCCU, VCCD and VDS are all part of/on the “Die”). Furthermore, the current through a transistor (i.e., the drain current) is proportional to the voltage across a transistor (i.e., VDS). Thus, by measuring VDS, Gendler et al is measuring the current through the sense transistor (i.e., the loading current).
It would have been obvious to use the circuit of 103 and 110 of Fig. 1 of Gendler et al. to measure the loading (current) of Huang et al. for the purpose of having a simply constructed current sensing element capable of sensing a current of a CPU/processor element.
As combined above the setpoints are set according to the measurement of the current and Gendler et al. discloses the measurement of the die voltage VDS. The drains to source voltage (i.e., VDS) is proportional to the current through the transistor (drain current/load current). Thus, the current setpoints are proportional to the interpreted “die voltage” VDS and thus the current setpoints may be considered VDS setpoints since the values are proportional.
Huang et al. fails to explicitly disclose whether or not all of the elements of Fig. 3 are constructed on the same die/chip. Thus, Huang et al. fails to disclose that the regulated voltage (Vcore) is “a die voltage on a semiconductor die” and that the integrated circuit (CPU 31) is “arranged on the semiconductor die”.
However, it is old and well-known to construct all of the elements of a circuit including a CPU/processor and a voltage controller/regulator on the same system-on-chip and therefore on the same die/chip.
This is further evidenced in Fig. 1 of Ihs which discloses a circuit including the CPU/processor (111, see Col. 3 lines 22-25) and a voltage controller/regulator on the same system-on-chip and therefore on the same die/chip (see Col. 2 lines 34-44).
It would have been obvious to construct the voltage controller/regulator and processor/CPU of Huang et al. on the same system-on-chip, and thus the same die, as evidenced by Ihs. Furthermore, it has been held that forming one piece of an article which has formerly been formed in two pieces and put together involves only routine skill in the art, Howard v. Detroit Stove Works, 150 U.S. 164 (1893). One would have been motivated to do so for the purpose of constructing a compact device on the same chip and therefore reducing the amount of separate chips required to construct the circuit of Fig. 2 of Huang et al.
As combined above the sensed die voltage, regulated voltage and CPU are all on the same chip/die.
With respect to claim 10, the method of claim 8, further comprising positioning the setpoint voltage at a minimum allowable voltage at full load of the voltage regulator (see Fig. 4 at Imax, VID-Offset, i.e., the VID signal for Fig. 4 that is sets an optimum Vcore see Col. 3 line 66 to Col. 4 line 29, is set to the “Minimum Voltage”) and at a maximum allowable voltage at minimal load of the voltage regulator (Maximum voltage for VID-Offset/Vcore is set at the minimum load current value, see Fig. 4).
Claim 15 is rejected for similar reasons as claim 7.
Claims 16 and 18 are rejected for similar reasons as claims 8 and 10. The circuit of Fig. 3 of Huang et al. operates in a closed loop fashion due to the feedback of VCORE, the clock control of 33 and the loading operations 31 controlled by 34 based on the detected loading current of 31.
Claim(s) 8-9, 1-14, 16-17 and 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yun et al. (USPN 20050144492) in view of Ihs (USPN 10,139,888).
With respect to claim 8, Yun et al. discloses, a method for controlling a load-variance rate (method of operating Fig. 1 further details disclosed in Figs. 3, 5 and 6) at which one or more integrated circuits (112/113) vary a load (according to current consumption in the activated mode and frequency of operation of 112/113) on a voltage regulator (120 supplying power to 112 and 113), the method comprising:
sensing a voltage of the one or more integrated circuits (220 of Fig. 1 determines if the voltage VDDCPU from 120 is sufficiently increased to a desired level, see paragraph 0057);
setting the load-variance rate (current consumption rate of 112 according the frequency of FCLK, see Fig. 5, operation speed of the processor and thus load variance is dependent upon the frequency of FCLK, see paragraph 0059. Further note power/current consumption increases with an increase in switching frequency, see paragraph 0007-0008) to a first rate (high frequency rate of FCLK in normal mode) if the voltage sensed is within a predetermined interval of a setpoint voltage of the voltage regulator (if the sensed voltage is larger than or equal to 1.3 V in the normal operating state. See also Fig. 6 which discloses additional frequency rates according to the transition of VDDCPU. For instance, lower operation mode of (normal level-an idle level/2), see paragraph 0061); and
setting the load-variance rate to a second rate (lower frequency rate during the transition period), lower than the first rate (lower than the high frequency rate), if the die voltage sensed is outside of the predetermined interval of the setpoint voltage of the voltage regulator (under 1.3 V to 1.0 V).
Yun et al. fails to explicitly disclose whether or not all of the elements of Fig. 1 are constructed on the same die/chip. Thus, Yun et al. fails to disclose that the regulated voltage (VDDCPU) is “a die voltage on a semiconductor die” and that the integrated circuit (112) is “semiconductor die” that receives the die voltage.
However, it is old and well-known to construct all of the elements of a circuit including a CPU/processor and a voltage controller/regulator on the same system-on-chip and therefore on the same die/chip.
This is further evidenced in Fig. 1 of Ihs which discloses a circuit including the CPU/processor (111, see Col. 3 lines 22-25) and a voltage controller/regulator on the same system-on-chip and therefore on the same die/chip (see Col. 2 lines 34-44).
It would have been obvious to construct the voltage controller/regulator and processor/CPU of Yun et al. on the same system-on-chip, and thus the same die, as evidenced by Ihs. Furthermore, it has been held that forming one piece of an article which has formerly been formed in two pieces and put together involves only routine skill in the art, Howard v. Detroit Stove Works, 150 U.S. 164 (1893). One would have been motivated to do so for the purpose of constructing a compact device on the same chip and therefore reducing the amount of separate chips required to construct the circuit of Fig. 1 of Yun et al.
With respect to claim 9, the method of claim 8, wherein the steps of sensing the die voltage, setting the load-variance rate to the first rate, and setting the load-variance rate to the second rate are enacted repeatedly, in a closed-loop manner (the control of Fig. 2 operates in a closed loop fashion. Furthermore, the operation will be cyclical between each time the system of Fig. 2 changes from the idle mode to the normal mode, back from the normal mode to the idle and into an additional normal mode from the previous idle mode).
With respect to claim 11, the method of claim 8, wherein setting the load-variance rate to the first rate and setting the load-variance rate to the second rate include resolving a difference between the setpoint voltage and the die voltage and setting the load-variance rate in response to the difference (the setting of the rates controlled according to the difference between the setpoint voltage of 1.3V and “die” voltage when the die voltage is between 1.0V and 1.3V in the transition period. For example the frequency is lower when there is a difference between the set die voltage and the 1.3 V setpoint voltage during the transition period, see steps s505-s507 of Fig. 3, see also paragraphs 0059-0062).
With respect to claim 12, the method of claim 11, wherein setting the load-variance rate to the first rate and setting the load-variance rate to the second rate include digitizing the difference (the difference between the setpoint and the measured die voltage is digitized, since 110 is processor such as a microprocessor which uses digital signals, see para 0043. Furthermore, VDDCPU is analog and must be digitized in order for 220 of the microprocessor to process the voltage level. Moreover, the difference is measured, see (normal level-an idle level)/2 of paragraph 0061), computing a comparison of the difference relative to a predetermined fraction of the setpoint voltage (the circuit operates as claimed due to the dividing by 2 of paragraph 0061), and setting the load-variance rate in response to the comparison (the frequency of FCLK and the load-variance of the CPU is set by the comparison, see Fig. 6).
Assuming, arguendo, that Yun et al. fails to explicitly disclose that difference is digitized. It would have been obvious to do so, since the circuit of 110 includes analog-to-digital converters (ADCs) that are capable of providing digitization of the signals. One would have been motivated to digitize the above signals and difference for the purpose of allowing the processor to 110 to provide such functions internal to the processor and thus reducing the amount of circuitry required to perform the sensing operations.
With respect to claim 13, the method of claim 12, wherein setting the load-variance rate to the first rate and setting the load-variance rate to the second rate include receiving a plurality of pulse trains differing in frequency (pulses generated by 240, see also Fig. 2), selecting a clock frequency based on the comparison, and setting the rate in response to the clock frequency (the selected frequency of FCLK is set according to the comparison, see Fig. 6 and paragraphs 0061-0062).
With respect to claim 14, the method of claim 8, wherein setting the load-variance rate to the first rate and setting the load-variance rate to the second rate comprise changing a clock speed of a processor or computer-memory system (the clock speeds are changed, see FCLK of Figs. 5 and 6 and 240 of Figs. 1 and 2).
With respect to claim 16, Yun discloses, a system comprising:
a voltage regulator (120) configured to regulate a voltage (VDDCPU) provided to a semiconductor device (112);
one or more integrated circuits arranged as the semiconductor die (112) and configured to vary a load on the voltage regulator at a load-variance rate (load varied according to the current consumption rate of 112 according the frequency of FCLK, see Fig. 5, operation speed of the processor and thus load variance is dependent upon the frequency of FCLK, see paragraph 0059. Further note power/current consumption increases with an increase in switching frequency, see paragraph 0007-0008); and
a load-variance manager (220) operatively coupled to the one or more integrated circuits (112), the load-variance manager configured to sense the die voltage (see step S506 of Fig. 3 and paragraph 0057) and control the load-variance rate in a closed-loop manner based on the voltage (Fig. 2 operates in a closed-loop manner according to the voltage during the idle to normal mode transition, see step S506).
Yun et al. fails to explicitly disclose whether or not all of the elements of Fig. 1 are constructed on the same die/chip. Thus, Yun et al. fails to disclose that the regulated voltage (VDDCPU) is “a die voltage on a semiconductor die” and that the integrated circuit (112) is “semiconductor die” that receives the die voltage.
However, it is old and well-known to construct all of the elements of a circuit including a CPU/processor and a voltage controller/regulator on the same system-on-chip and therefore on the same die/chip.
This is further evidenced in Fig. 1 of Ihs which discloses a circuit including the CPU/processor (111, see Col. 3 lines 22-25) and a voltage controller/regulator on the same system-on-chip and therefore on the same die/chip (see Col. 2 lines 34-44).
It would have been obvious to construct the voltage controller/regulator and processor/CPU of Yun et al. on the same system-on-chip, and thus the same die, as evidenced by Ihs. Furthermore, it has been held that forming one piece of an article which has formerly been formed in two pieces and put together involves only routine skill in the art, Howard v. Detroit Stove Works, 150 U.S. 164 (1893). One would have been motivated to do so for the purpose of constructing a compact device on the same chip and therefore reducing the amount of separate chips required to construct the circuit of Fig. 1 of Yun et al.
With respect to claim 17, the system of claim 16, wherein controlling the load-variance rate includes setting the load-variance rate to a highest available rate at which the die voltage stays within a predetermined interval bracketing a setpoint voltage of the voltage regulator (the highest available for FCLK rate brackets the end of the setpoint).
With respect to claim 19, the system of claim 16, wherein controlling the load-variance rate includes selecting a clock frequency based on whether the die voltage exceeds a predetermined interval of the setpoint voltage (FCLK is controlled according to the predetermined level, i.e., greater than 1.3V, and/or normal level-an idle level)/2 of paragraph 0061, see Figs. 5 and 6).
With respect to claim 20, the system of claim 16, wherein the voltage regulator is arranged on the die (the above elements are on the same die).
Allowable Subject Matter
Claims 2-4 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Conclusion
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/THOMAS J. HILTUNEN/Primary Examiner, Art Unit 2849