DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I (i.e., Claims 1-14) in the reply filed on June 22nd, 2026, is acknowledged. Claims 15-20 are hereby withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on June 22nd, 2026.
Information Disclosure Statement
The information disclosure statements (IDS) filed on February 28th, 2024, March 1st, 2024, March 11th, 2025, and April 7th, 2025 are being considered by the examiner.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they do not include the following reference sign(s) mentioned in the description:
(a) [0296] of the Specification refers to Figs. 46A-46D and references “memory opening 49” which is not shown in Figs. 46A-46D;
(b) [0296] of the specification refers to Figs. 46A-46D and references “memory elements (e.g., portions of the memory film 50) and a vertical semiconductor channel 60” which is not shown in Figs. 46A-46D.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claim 7 is objected to because of the following informalities:
(a) line 3, “. . . within the second subset of the first electrically conductive layers by tubular portion of a respective backside blocking dielectric layer . . .” should read, “within the second subset of the first electrically conductive layers by a tubular portion of a respective backside blocking dielectric layer . . .”
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 5-6 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 5 recites the limitation "the second horizontal plane" in lines 2-3 of said claim. There is insufficient antecedent basis for this limitation in the claim, as a second horizontal plan was previously introduced in Claim 2, but Claim 5 depends only upon Claim 1. Examiner is seeking clarification on whether Claim 5 is to depend upon Claim 2 or whether “the second horizontal plane” as stated should be amended to “a second horizontal plane”. For the purposes of compact prosecution, Examiner shall interpret “the second horizontal plane” as “a second horizontal plane” to not modify claim dependencies.
Claim 6 is rejected due to its dependence upon a previously rejected claim (i.e., Claim 5).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
A) Determining the scope and contents of the prior art.
B) Ascertaining the differences between the prior art and the claims at issue.
C) Resolving the level of ordinary skill in the pertinent art.
D) Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kubo, et al. (US 20220328413 A1; hereinafter referred to as Kubo) and further in view of Lee (US 20190067182 A1; hereinafter referred to as Lee).
Regarding Claim 1, Kubo discloses a three-dimensional memory device ([Abstract]), comprising:
a first alternating stack (first alternating stack, [0127], Fig. 70) of first insulating layers (first insulating layers 132, [0120], Fig. 70) and first electrically conductive layers (electrically conductive layers 146, 246, [0201], Fig. 70);
a memory opening (memory opening 49, [0172]) vertically extending through the first alternating stack (Fig. 16A);
a memory opening fill structure located in the memory opening (memory opening fill structure 58, [0172], Fig. 16B, 17) and comprising a vertical stack of memory elements (memory elements, [0172]) and a vertical semiconductor channel (vertical semiconductor channel 60, [0171-0172], Fig. 16D);
a first layer contact via structure (contact via structure 86, [0212]) vertically extending through a first subset of the first electrically conductive layers and contacting a top surface of one of the first electrically conductive layers within a first horizontal plane (Fig. 69C-70); and
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a first dielectric support pillar structure located in proximity to the first layer contact via structure (support pillar structure 222, [0222], Fig. 69A)).
Kubo is silent on the first dielectric support pillar structure being finned and comprising a first tubular insulating liner vertically extending through each of the first subset of the first electrically conductive layers and through said one of the first electrically conductive layers, and a first finned dielectric material portion comprising a first dielectric pillar that vertically extends through each layer within the first alternating stack and further comprising first dielectric fins that are located below the first horizontal plane.
However, in analogous art, Lee discloses a three-dimensional memory device with a finned dielectric support pillar structure (contact plug 54 and spacers 53 in combination; [0118], Fig. 13B) located in proximity to the first layer contact via structure (isolation pattern 55, Fig 13B) comprising:
a first tubular insulating liner vertically extending through each of the first subset of the first electrically conductive layers and through said one of the first electrically conductive layers (coupling pattern 53A, [0113], Fig. 13B), and
a first finned dielectric material portion comprising a first dielectric pillar that vertically extends through each layer within the first alternating stack (contact plug 54, [0113], Fig. 13B) and further comprising first dielectric fins that are located below the first horizontal plane (loop patterns 53B, [0113, 0119], Fig. 13B).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to modify the dielectric support pillar structure as disclosed in Kubo with the finned dielectric support pillar structure as disclosed in Lee. One would be motivated to do so as having a finned dielectric support pillar structure can further increase the insulating between the conductive layers and the support pillar; thus, increasing device performance (Lee: [0042]).
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Regarding Claim 2, Kubo/Lee discloses the three-dimensional memory device of Claim 1, wherein the first tubular insulating liner has an annular bottom surface (Lee: Fig. 13A) located within a second horizontal plane that underlies the first horizontal plane (Lee: Fig. 13B).
Regarding Claim 3, Kubo/Lee discloses the three-dimensional memory device of Claim 2, wherein a topmost horizontal surface of the first dielectric fins is located within a third horizontal plane that underlies the second horizontal plane (Lee: Fig. 13B)
Regarding Claim 4, Kubo/Lee discloses the three-dimensional memory device of Claim 3, wherein:
a vertical spacing between the second horizontal plane and the third horizontal plane is not greater than a thickness of one of the first insulating layers located between said one of the first electrically conductive layers and another of the first electrically conductive layers that is most proximal to said one of the first electrically conductive layers and located underneath the second horizontal plane (Kubo: Fig. 69C); and
a vertical spacing between the first horizontal plane and the second horizontal plane is not less than a sum of a thickness of said one of the first electrically conductive layers and a thickness of a backside blocking dielectric layer (Kubo: backside blocking dielectric layer 44, [0198], Fig. 59) in contact with said one of the first electrically conductive layers (Kubo: Fig. 69C).
Regarding Claim 5, Kubo/Lee discloses the three-dimensional memory device of Claim 1, wherein the first dielectric fins are located at levels of a second subset of the first electrically conductive layers that underlie the second horizontal plane (Lee: Fig. 13B).
Regarding Claim 6, Kubo/Lee discloses the three-dimensional memory device of Claim 5, wherein the second subset of the first electrically conductive layers comprise each of the first electrically conductive layers within the first alternating stack which underlies said one of the first electrically conductive layers (Lee: Fig. 13B).
Regarding Claim 7, Kubo/Lee discloses the three-dimensional memory device of Claim 1, wherein each of the first dielectric fins is laterally spaced from a respective first electrically conductive layer within the second subset of the first electrically conductive layers by tubular portion of a respective backside blocking dielectric layer (Kubo: backside blocking dielectric layer 44, [0198], Fig. 59) that contacts a respective cylindrical surface segment of the memory opening fill structure (Kubo: [0198]).
Regarding Claim 8, Kubo/Lee discloses the three-dimensional memory device of Claim 1, wherein each of the first subset of the first electrically conductive layers is laterally spaced from the first tubular insulating liner by a respective backside blocking dielectric layer (Kubo: backside blocking dielectric layer 44, [0198], Fig. 59; the backside blocking dielectric layer surrounds all of the channel layers, including those that do not have fins on their level) that contacts a respective cylindrical surface segment of the memory opening fill structure (Kubo: [0198]).
Regarding Claim 9, Kubo/Lee discloses the three-dimensional memory device of Claim 1, wherein said one of the first electrically conductive layers is laterally spaced from the first tubular insulating liner by a backside blocking dielectric layer (backside blocking dielectric layer 44, [0198], Fig. 59; the backside blocking dielectric layer surrounds all of the channel layers, including the first electrically conductive layer) that contacts a cylindrical surface segment of the memory opening fill structure (Kubo: [0198]).
Regarding Claim 10, Kubo/Lee discloses the three-dimensional memory device of Claim 1, wherein the first dielectric pillar comprises a straight sidewall that vertically extends from an inner periphery of a topmost surface of the first dielectric fins at least to a topmost surface of the first alternating stack (Lee: Fig. 13B).
Claim(s) 11-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kubo, et al. (US 20220328413 A1; hereinafter referred to as Kubo) and further in view of Lee (US 20190067182 A1; hereinafter referred to as Lee) and further in view of Yamada, et al. (US 20220352093 A1; hereinafter referred to as Yamada).
Regarding Claim 11, Kubo/Lee discloses the three-dimensional memory device of Claim 1.
Kubo/Lee fails to disclose a memory device comprising a second type of support structure (i.e., a first finless dielectric support pillar).
However, in analogous art, Yamada discloses a three-dimensional memory device comprising both finned and finless support pillar structures (first-type support pillar structure [finless] 22 and second-type support pillar structure [finned] 20C, [0115]), wherein the finless support structure comprises:
an additional tubular insulating liner comprising a same material as the first tubular insulating liner and vertically extending through each of the first electrically conductive layers in the first alternating stack (dummy memory film 50’, [0237]; the dummy memory film is made of a same material as the dummy memory film of the second-type support structure, and is analogous to the tubular insulating liner of the instant application as they both serve the purpose of further electrically insulating the support structure from the channel layers of the device), and
an additional dielectric pillar comprising a same material as the first dielectric pillar, laterally surrounded by the additional tubular insulating liner, and having a straight sidewall that vertically extends through each layer within the first alternating stack (dummy vertical semiconductor channel 60’, [0237]; the dummy vertical semiconductor channel is made of the same material as the dummy vertical semiconductor channel of the second-type support structure, and is analogous to the dielectric pillar as they both serve the same purpose of electrically connecting the support structure to the rest of the device).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to modify the device structure as taught by Kubo/Lee by introducing a differently structure dielectric support pillar as taught in Yamada as it would have been obvious to try this combination of support pillar structures.
At the time of the instant application, there was expressed need to improve compactness and functionality of three-dimensional memory devices as stated by Yamada, and that there is a finite number of identified, predictable solutions to this recognized need (i.e., the support structures can be all finned (as disclosed in Lee), all finless (as disclosed in Kubo), or a combination (as disclosed by Yamada)). It is averred that one of ordinary skill in the art could have pursued the known potential solutions with a reasonable expectation of success (e.g., Yamada discloses that a first-type support pillar structure (finless) and a second-type support pillar structure (finned) in combination can be used to form a functioning three-dimensional memory device) and, therefore, would have a reasonable expectation of success with this predictable solution. See MPEP 2143(I)(E).
Regarding Claim 12, Kubo/Lee/Yamada discloses the three-dimensional memory device of Claim 11, further comprising:
a second alternating stack (Kubo: second alternating stack, [0151], Fig. 70) of second insulating layers (second insulating layers 232, [0152], Fig. 70) and second electrically conductive layers located over the first alternating stack (second electrically conductive layers 246, [0201], Fig. 70), wherein the memory opening, the memory opening fill structure, the first layer contact via structure, and the first finned dielectric support pillar structure vertically extend through each layer within the second alternating stack (Fig. 70); and
a second finned dielectric support pillar structure vertically extending through the second alternating stack and not extending into the first alternating stack (Kubo: dielectric support pillar 224, Fig. 70) and comprising:
a second tubular insulating liner vertically extending through each of a first subset of the second electrically conductive layers and through one of the second electrically conductive layers that underlies the first subset of the second electrically conductive layers (Lee: contact plug 54 and spacers 53 in combination; [0118], Fig. 13B; since dielectric support pillar 224 and 222 are of similar design, it would be obvious to use the same device as expressed in Lee), and
a second finned dielectric material portion comprising a second dielectric pillar that vertically extends through each layer within the second alternating stack (Lee: contact plug 54, [0113], Fig. 13B) and further comprising second dielectric fins that underlie said one of the second electrically conductive layers (Lee: loop patterns 53B, [0113, 0119], Fig. 13B).
Regarding Claim 13, Kubo/Lee/Yamada discloses the three-dimensional memory device of Claim 12, further comprising a second layer contact via structure located in proximity to the second finned dielectric support pillar structure and vertically extending through the first subset of the second electrically conductive layers and contacting a top surface of said one of the second electrically conductive layers (Kubo: contact via 86, Fig. 70).
Regarding Claim 14, Kubo/Lee/Yamada discloses the three-dimensional memory device of Claim 12, further comprising an etch-stop plate embedded within an inter-tier dielectric layer located between the first alternating stack and the second alternating stack (etch stop layer, [0137], Fig. 70; “The top surface of the inter-tier dielectric layer 180 may be used as an etch stop layer or a planarization stop layer”), wherein a bottom surface of the second finned dielectric support pillar structure contacts the etch-stop plate (Kubo: Fig. 70; the second dielectric support pillar is in contact with the top surface of the inter-tier dielectric layer 180 and would, therefore, be in contact with the etch-stop plate as defined).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
(a) Lien, et al. (US 20230016518 A1); discloses contact vias and support pillar structures being of a same design of having a liner and central pillar structure.
(b) Shimabukuro, et al. (US 20220375958 A1); discloses finned support pillar structures along with contact vias.
(c) Amano, et al. (WO 2023239442 A1); discloses a three-dimensional memory device with support pillars and contact vias.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Noah C. Robertson whose telephone number is (571) 317-0595. The examiner can normally be reached Monday-Friday 9:30 AM - 6:30 PM (Eastern Time Zone).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William B Partridge, can be reached at (571) 270-1402. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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/Noah C. Robertson/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
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