DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is in reply to an Amendment filed on June 24, 2026 regarding Application No. 18/589,183. Applicants amended claims 1-5, 7, 9-11, 13, 15, 17, and 19 and added new claim 20. Claims 1-20 are pending.
Priority
Acknowledgment is made of Applicants’ claim for foreign priority under 35 U.S.C. 119(a)-(d). A certified copy of the KR 10-2023-0027230 application filed in Korea on February 28, 2023 has been filed.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on March 28, 2026 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the Office.
Response to Arguments
Applicants’ amendments to claims 2-5, 7, 9-11, 13, 15, 17, and 19 and remarks (Remarks, p. 7) regarding claim objections are acknowledged. In view of the amendments, the objections are moot.
Applicants’ arguments filed on June 24, 2026 have been fully considered but they are not persuasive or are moot in view of new grounds of rejection.
With respect to the discussion below, the Office submits that Park as modified teaches and/or suggests all features of newly amended independent claim 1. For example, figures 7 and 10 and paragraphs [0052]-[0054], and [0094]-[0095] of Park teach: e.g., wherein the connection pattern corresponding to CT2, is a conductive layer, and wherein the connection pattern corresponding to CT2 is connected to the connection line BE1 through a first contact hole CT2 and connected to the at least one signal line STL or the gate line. Although Park does not teach: wherein the connection pattern is provided of a same material and on a same layer as the first electrode, and wherein the connection pattern is connected to the connection line through the first contact hole and connected to the at least one signal line or the gate line through a second contact hole, it would have been obvious to include the claimed features, such that Park as modified teaches: wherein the connection pattern is provided of a same material and on a same layer as the first electrode and is a conductive layer, and wherein the connection pattern is connected to the connection line through a first contact hole and connected to the at least one signal line or the gate line through a second contact hole, since it would have been within the general skill of one of ordinary skill in the art to select features on the basis of their suitability for the intended use to provide gate driving signals for image display.
In response to the argument regarding “additional distinguishing features”, “any of the references applied by the Office Action”, “these features in combination with other features recited in independent claim 1, as amended” and Park, Jo, Yuan, and Choi (Remarks, pp. 7-8), the Office respectfully submits that the argument is not commensurate with the rejections and all features of newly amended independent claim 1 are taught and/or suggested by Park and as discussed, as discussed above and in the rejections.
In response to the argument regarding Park, second contact hole CT2, and conductive layer (Remarks, p. 8), the Office respectfully disagrees and submits that the argument is not commensurate with the rejections and the relevant claimed feature is taught by Park, as discussed above and in the rejections.
In response to the argument regarding Park, second contact hole CT2, “connected to the first bridge line BE1... through a first contact hole and connected to the start line STL... or the gate line through a second contact hole”, connection pattern, and claimed first contact hole (pp. 8 and 9), the Office respectfully disagrees and/or submits that the argument is not commensurate with the rejections and the relevant claimed features are taught and/or suggested by Park and as discussed, as discussed above and in the rejections.
In response to the argument regarding cathode auxiliary electrode 300 and connected to the gate control line 290 and the first bridge line BE1 (Remarks, p. 9), the Office submits that the argument is not commensurate with the rejections and the relevant claimed features are taught and/or suggested by Park and as discussed, as discussed above and in the rejections.
In response to the argument regarding Park and “‘wherein the connection pattern is provided of a same material and on a same layer as the first electrode and is a conductive layer, and wherein the connection pattern is connected to the connection line through a first contact hole and connected to the at least one signal line or the gate line through a second contact hole’ as recited in independent claim 1, as amended” (Remarks, p. 9), the Office respectfully submits that the argument is not commensurate with the rejections and the recited features are taught and/or suggested by Park and as discussed, as discussed above and in the rejections.
In response to the argument regarding Jo, Yuan, and Choi and remedy (Remarks, p. 9), the Office respectfully submits that all features of newly amended independent claim 1 are taught and/or suggested by Park and as discussed, as discussed above and in the rejections. As such, there are no deficiencies, as argued, for which Jo, Yuan, and Choi are required to remedy.
In response to the arguments regarding Park, Jo, Yuan, and Choi, specific features, amended independent claim 1, and amended claim 1, dependent claims 2-20, and allowable (Remarks, pp. 9-10), the Office respectfully disagrees and/or submits that the arguments are not commensurate with the rejections and all features of newly amended independent claim 1 are taught and/or suggested by Park and as discussed, as discussed above and in the rejections. As such, newly amended independent claim 1 is not allowable. In addition, claims 2-20 are not allowable by virtue of their individual dependencies from newly amended independent claim 1, and as discussed in the rejections.
For the reasons discussed above and in the rejections, pending claims 1-20 are not allowable.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or non-obviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicants are advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-13 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. in KR 10-2019-0051513 A (hereinafter Park; an original copy and full machine translation thereof was provided with the April 1, 2026 Office action).
Regarding claim 1, Park teaches:
A display apparatus (see FIG. 3), comprising (Park: FIG. 3 and “[0028] [FIG.] 3… illustrat[es] a display device….”, see also FIGs. 4-5):
a substrate (100 in FIGs. 9-10) including a display area (AA in FIGs. 3-5) having a pixel (P in FIG. 3) and a non-display area (outside of AA) surrounding the display area (Park: FIGs. 3-5 and 9-10, “[0031] The display panel 10 includes… a lower substrate. The lower substrate is provided with a display area AA including data lines (D1 to Dm…), gate lines (G1 to Gn…) …. The pixel P may be connected to any one of the data lines D1 to Dm and to one of the gate lines G1 to Gn”, and “[0064] Referring to FIG. 9, a buffer layer 110 is formed on one surface of the lower substrate 100….”);
a driving transistor (210 in FIG. 9) provided at the pixel (Park: FIG. 9, “[0164]… [E]ach of the pixels includes a thin film transistor including a gate electrode, a source electrode, and a drain electrode; An anode auxiliary electrode connected to a source electrode or a drain electrode of the thin film transistor; And an anode electrode connected to the anode auxiliary electrode….”, and “[0066] [Referring to FIG. 9,] [t]he thin film transistor 210 includes an active layer 211, a gate electrode 212, a source electrode 213, and a drain electrode….”, see also FIG. 14, “[0077]… The anode auxiliary electrode 240 may be connected to the source electrode 213 [of the thin film transistor 210] through the sixth contact hole CT6 passing through the protective film 150 and the first planarization film 160….”, and “[0080]… The anode electrode 250 [of a light emitting diode] may be connected to the anode auxiliary electrode 240 through the seventh contact hole CT7 passing through the second planarization film 170….”);
a light emitting diode (250-270 in FIG. 9) provided at the pixel and including a first electrode (250), an emitting layer (260), and a second electrode (270) (Park: FIG. 9 and “[0063]… [T]he pixel P includes a light emitting diode including an anode electrode 250, a light emitting layer 260, and a cathode electrode 270.”, see also [0079]); and
a gate driving unit (11 in FIG. 3) provided in the non-display area (Park: FIG. 3 and “[0033] The first… gate driver[] 11… may be formed in a non-display region by a gate driver in panel (GIP) scheme….”, see also FIG. 5),
wherein the gate driving unit includes a line portion (CL1, CL2, and STL portion in FIG. 5) including at least one signal line (e.g., STL) and a stage portion (ST 1-ST n portion) including at least one stage (e.g., ST 1) (Park: FIG. 5 and “[0042]… [T]he first… gate driver[] 11… includes first through n-th stages ST1 through STn…. The start signal line STL may be connected to the first stage ST1. The two clock signal lines CL1 and CL2 may be alternately connected to the first through n-th stages ST1 through STn….”, see also FIG. 7),
wherein the at least one stage is connected to the at least one signal line or a gate line of the display area through a connection line (e.g., BE1 in FIG. 7) and a connection pattern (e.g., corresponding to CT2) (Park: FIG. 7 and “[0052] The start line STL may be connected to the first stage ST1 via a first connection line BE1. The first connection line BE1 may be connected to the start line STL through the second contact hole CT2.”, see also “[0053] The first clock line CL1 may be connected to some stages via the second connection line BE2…. And the second connection line BE2 may be connected to the first clock line CL1 through the second contact hole CT2.” and “[0054] And the second clock line CL2 may be connected to the remaining stages ST1 through STn through the third connection line BE3….And the third connection line BE3 may be connected to the second clock line CL2 through the second contact hole CT2.”),
wherein the connection pattern is a conductive layer (Park: FIG. 7 and [0052], see also FIG. 10, [0053]-[0054], “[0094] The gate control line 290, such as the first and second clock lines CL1, CL2 and start line STL, includes first and second gate control lines 291, 292.”, and “[0095]... The first gate control line 291 is connected to the first through third connection lines... through the second contact hole CT2 passing through the second interlayer insulating film 140 or the first and second interlayer insulating films 130 and 140. [ (281, 282, 283), respectively.”), and
wherein the connection pattern is connected to the connection line through a first contact hole (e.g., CT2 in FIG. 7) and connected to the at least one signal line or the gate line (Park: FIG. 7 and [0052], see also FIG. 10, [0053]-[0054], and [0094]-[0095]).
However, it is noted that Park does not teach:
the pixel is a subpixel, and
wherein the connection pattern is provided of a same material and on a same layer as the first electrode, and
wherein the connection pattern is connected to the connection line through the first contact hole and connected to the at least one signal line or the gate line through a second contact hole,
but which would have been obvious to include, such that Park as modified teaches: a substrate including a display area having a subpixel and a non-display area surrounding the display area; a driving transistor provided at the subpixel; a light emitting diode provided at the subpixel and including a first electrode, an emitting layer, and a second electrode; wherein the connection pattern is provided of a same material and on a same layer as the first electrode and is a conductive layer, and
wherein the connection pattern is connected to the connection line through a first contact hole and connected to the at least one signal line or the gate line through a second contact hole, since it would have been within the general skill of one of ordinary skill in the art to select features on the basis of their suitability for the intended use to provide illumination and gate driving signals for image display.
Regarding claim 2, Park as modified teaches:
The display apparatus of claim 1, wherein the connection line is disposed on a different layer from the at least one signal line and overlaps the at least one signal line (Park: FIGs. 7 and 10-11, “[0052] The start line STL may be connected to the first stage ST1 via a first connection line BE1. The first connection line BE1 may be connected to the start line STL through the second contact hole CT2.”, “[0092]… [F]irst to third connection lines 281, 282 and 283 [in FIGs. 10-11]….”, and “[0094] The gate control line 290, such as the first and second clock lines CL1, CL2 and start line STL, includes first and second gate control lines 291, 292.”, see also FIGs. 13 and 15-16 and “[0095] The first gate control line 291 [in FIGs. 10-11] may be formed on the second interlayer insulating film 140…. The first gate control line 291 is connected to the first through third connection lines 240 through the second contact hole CT2 passing through the second interlayer insulating film 140 or the first and second interlayer insulating films 130 and 140. [ (281, 282, 283), respectively.”).
Regarding claim 3, Park as modified teaches:
The display apparatus of claim 1, wherein the connection line is disposed between the at least one signal line and the connection pattern (Park: see FIG. 7).
Regarding claim 4, Park as modified teaches:
The display apparatus of claim 1.
However, it is noted that Park as modified does not teach:
further comprising an auxiliary pattern between the at least one signal line and the connection pattern, wherein the auxiliary pattern overlaps the at least one signal line and is spaced apart from the connection line,
but which would have been obvious to include, such that Park as modified teaches: further comprising an auxiliary pattern between the at least one signal line and the connection pattern, wherein the auxiliary pattern overlaps the at least one signal line and is spaced apart from the connection line, since it would have been within the general skill of one of ordinary skill in the art to select features on the basis of their suitability for the intended use to provide gate driver signals for image display.
Regarding claim 5, Park as modified teaches:
The display apparatus of claim 4.
However, it is noted that Park as modified does not teach:
wherein the auxiliary pattern is in contact with the at least one signal line, and the connection line is separated from the at least one signal line,
but which would have been obvious to include, such that Park as modified teaches: wherein the auxiliary pattern is in contact with the at least one signal line, and the connection line is separated from the at least one signal line, since it would have been within the general skill of one of ordinary skill in the art to select features on the basis of their suitability for the intended use to provide gate driver signals for image display.
Regarding claim 6, Park as modified teaches:
The display apparatus of claim 4.
However, it is noted that Park as modified does not teach:
wherein the auxiliary pattern is formed of a same material and on a same layer as the connection line,
but which would have been obvious to include, such that Park as modified teaches: wherein the auxiliary pattern is formed of a same material and on a same layer as the connection line, since it would have been within the general skill of one of ordinary skill in the art to select features on the basis of their suitability for the intended use to provide gate driver signals for image display.
Regarding claim 7, Park as modified teaches:
The display apparatus of claim 1, wherein the connection line (e.g., BE2 in FIG. 7) includes a first line (e.g., BE2 line from the left of STL to the left of ST2) and a second line (e.g., BE2 line from the leftmost of BE2 to the left of CL2) spaced apart from each other (Park: see FIG. 7), and
wherein the first line is connected to the at least one stage (e.g., ST2), and the second line is connected to the at least one signal line (e.g., CL1) (Park: see FIG. 7 and “[0053] The first clock line CL1 may be connected to some stages via the second connection line BE2…. And the second connection line BE2 may be connected to the first clock line CL1 through the second contact hole CT2.”, see also “[0042]… [T]he first… gate driver[] 11… includes first through n-th stages ST1 through STn…. The two clock signal lines CL1 and CL2 may be alternately connected to the first through n-th stages ST1 through STn….”).
Regarding claim 8, Park as modified teaches:
The display apparatus of claim 7, wherein the connection pattern (e.g., corresponding to CT2) overlaps and is in contact with the first line and the second line (Park: in contact with the first line via the second line and a line between the first and second lines, and overlaps and is in contact with the second line; FIGs. 7 and 10-11 and “[0053] The first clock line CL1 may be connected to some stages via the second connection line BE2…. And the second connection line BE2 may be connected to the first clock line CL1 through the second contact hole CT2.”, “[0092]… [F]irst to third connection lines 281, 282 and 283 [in FIGs. 10-11]….”, and “[0094] The gate control line 290, such as the first and second clock lines CL1, CL2 and start line STL, includes first and second gate control lines 291, 292.”, see also FIGs. 13 and 15-16 and “[0095] The first gate control line 291 [in FIGs. 10-11] may be formed on the second interlayer insulating film 140…. The first gate control line 291 is connected to the first through third connection lines 240 through the second contact hole CT2 passing through the second interlayer insulating film 140 or the first and second interlayer insulating films 130 and 140. [ (281, 282, 283), respectively.”; it would have been obvious to include: the connection pattern overlaps and is in contact with the first line, since it would have been within the general skill of one of ordinary skill in the art to select features on the basis of their suitability for the intended use to provide gate driving signals for image display”).
Regarding claim 9, Park as modified teaches:
The display apparatus of claim 1, further comprising a light shielding layer between the substrate and the driving transistor (Park: see FIG. 9 and “[0068]… Between the buffer layer 110 and the active layer 211, a light shielding layer… may be formed….”),
wherein the driving transistor includes a gate electrode (212), an active layer (211), a source electrode (213), and a drain electrode (Park: FIG. 9 and “[0066] The thin film transistor 210 includes an active layer 211, a gate electrode 212, a source electrode 213, and a drain electrode….”, see also FIG. 14 (gate electrode 212, active layer 211, source electrode 213, and drain electrode 214), [0117], and [0125]),
wherein the at least one signal line is formed of a same material and on a same layer as the gate electrode (it would have been obvious to include the claimed features since it would have been within the general skill of one of ordinary skill in the art to select features on the basis of their suitability for the intended use to provide a signal line), and
wherein the connection line is formed of a same material and on a same layer as the source electrode and the drain electrode (it would have been obvious to include the claimed features since it would have been within the general skill of one of ordinary skill in the art to select features on the basis of their suitability for the intended use to provide a connection line).
Regarding claim 10, Park as modified teaches:
The display apparatus of claim 1, further comprising a light shielding layer between the substrate and the driving transistor (Park: see FIG. 9 and “[0068]… Between the buffer layer 110 and the active layer 211, a light shielding layer… may be formed….”),
wherein the driving transistor includes a gate electrode (212), an active layer (211), a source electrode (213), and a drain electrode (Park: FIG. 9 and “[0066] The thin film transistor 210 includes an active layer 211, a gate electrode 212, a source electrode 213, and a drain electrode….”, see also FIG. 14 (gate electrode 212, active layer 211, source electrode 213, and drain electrode 214), [0117], and [0125]),
wherein the at least one signal line is formed of a same material and on a same layer as the light shielding layer (it would have been obvious to include the claimed features since it would have been within the general skill of one of ordinary skill in the art to select features on the basis of their suitability for the intended use to provide a signal line), and
wherein the connection line is formed of a same material and on a same layer as the gate electrode, the source electrode, and the drain electrode (it would have been obvious to include the claimed features since it would have been within the general skill of one of ordinary skill in the art to select features on the basis of their suitability for the intended use to provide a connection line).
Regarding claim 11, Park as modified teaches:
The display apparatus of claim 1, wherein the at least one stage includes at least one transistor (e.g., TU in FIG. 6) (Park: FIG. 6 and “[0044] The k-th stage STk includes… a pull-up transistor TU….”),
wherein the at least one transistor includes a gate, an active pattern (corresponding to the transistor), a source, and a drain (Park: see FIG. 6), and wherein
the active pattern is connected to the source through a first pattern and connected to the drain through a second pattern (it would have been obvious to include the claimed features since it would have been within the general skill of one of ordinary skill in the art to select features on the basis of their suitability for the intended use to provide a gate driver for image display).
Regarding claim 12, Park as modified teaches:
The display apparatus of claim 11, wherein the first pattern and the second pattern are formed of a same material and on a same layer as the first electrode (it would have been obvious to include the claimed features since it would have been within the general skill of one of ordinary skill in the art to select features on the basis of their suitability for the intended use to provide a gate driver for image display).
Regarding claim 13, Park as modified teaches:
The display apparatus of claim 1, wherein the at least one signal line transmits a scan clock, a carry clock, a gate high-level voltage, a start signal (STL signal), a reset signal, or a real time signal (Park: FIG. 5, “[0042]… The start signal line STL may be connected to the first stage ST1.….”, and “[0043]… [T]he first stage ST1 receives the start voltage of the start signal line STL….”).
Regarding claim 20, Park as modified teaches:
The display apparatus of claim 1, further comprising:
an overcoat layer (e.g., 130 and/or 140 in FIG. 10) between the connection line and the connection pattern (Park: FIG. 10 and “[0095]... The first gate control line 291 is connected to the first through third connection lines... through the second contact hole CT2 passing through the second interlayer insulating film 140 or the first and second interlayer insulating films 130 and 140. [ (281, 282, 283), respectively.”),
wherein the first contact hole and the second contact hole are provided in the overcoat layer (Park: wherein the first contact hole is provided as claimed; FIG. 10 and [0095]; it would have been obvious to include the claimed features since it would have been within the general skill of one of ordinary skill in the art to select features on the basis of their suitability for the intended use to provide gate driving signals for image display).
Claims 14-15 and 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Park in view of Jo et al. in US 2021/0202674 A1 (hereinafter Jo).
Regarding claim 14, Park as modified teaches:
The display apparatus of claim 1, wherein the subpixel includes:
the light emitting diode connected to the driving transistor (Park: FIG. 9, “[0077] An anode auxiliary electrode 240… may be formed on the first planarization layer 160. The anode auxiliary electrode 240 may be connected to the source electrode 213 [of the thin film transistor 210] through the sixth contact hole CT6 passing through the protective film 150 and the first planarization film 160….”, and “[0080] The anode electrode 250 [of a light emitting diode] may be formed on the second planarization layer 170. The anode electrode 250 may be connected to the anode auxiliary electrode 240 through the seventh contact hole CT7 passing through the second planarization film 170….”).
However, it is noted that Park as modified does not teach:
a switching transistor switched according to a scan signal and connected to a data signal;
a storage capacitor connected to the switching transistor;
the driving transistor switched according to a voltage of a capacitor electrode of the storage capacitor and connected to a high-level voltage;
a reference transistor switched according to a sensing signal and connected to the storage capacitor, the driving transistor and a reference signal, and
the light emitting diode connected to the storage capacitor, the reference transistor, and a low-level voltage.
Jo teaches:
a switching transistor (ST in FIG. 2) switched according to a scan signal (GL1i signal) and connected to a data signal (DLj) (Park: FIG. 2, “[0068] A first electrode (for example, a source electrode) of the switching transistor ST is electrically connected to the j-th data line DLj….”, and “[0069] The switching transistor ST is turned on when a gate signal at a gate-on level is applied through the i-th first gate line GL1i….”);
a storage capacitor (Cst) connected to the switching transistor (Park: FIG. 2, “[0068]… [A] second electrode (for example, a drain electrode) of the switching transistor ST is electrically connected to a first node N1….”, and “[0070] A first electrode of the storage capacitor Cst is electrically connected to the first node N1….”);
a driving transistor (DT) switched according to a voltage of a capacitor electrode of the storage capacitor and connected to a high-level voltage (ELVDD) (Park: FIG. 2 and “[0071] A first electrode (for example, a source electrode) of the driving transistor DT receives the high-potential driving voltage ELVDD…. A gate electrode of the driving transistor DT is electrically connected to the first node N1. The driving transistor DT is turned on when a voltage at a gate-on level is applied through the first node N1, and may control the amount of a driving current flowing to the light-emitting element LD depending on a voltage provided to the gate electrode, that is, a voltage stored in the storage capacitor Cst.”);
a reference transistor (SST) switched according to a sensing signal (GL2i signal) and connected to the storage capacitor, the driving transistor and a reference signal (SLj signal) (Park: FIG. 2, “[0070] A first electrode of the storage capacitor Cst is electrically connected to the first node N1, and a second electrode of the storage capacitor Cst receives a high-potential driving voltage ELVDD. The storage capacitor Cst may be charged with a voltage corresponding to the difference between a voltage applied to the first node N1 and the high-potential driving voltage ELVDD.”, “[0071] A first electrode (for example, a source electrode) of the driving transistor DT receives the high-potential driving voltage ELVDD, and a second electrode (for example, a drain electrode) of the driving transistor DT is electrically connected to a first electrode (for example, an anode electrode) of the light-emitting element LD….”, and “[0072] A first electrode (for example, a source electrode) of the sensing transistor SST is electrically connected to a j-th sensing line SLj, and a second electrode (for example, a drain electrode) of the sensing transistor SST is electrically connected to the first electrode (for example, the anode electrode) of the light-emitting element LD. A gate electrode of the sensing transistor SST is electrically connected to an i-th second gate line GL2i. The sensing transistor SST is turned on when a sensing signal at a gate-on level is applied through the i-th second gate line GL2i, and transmits a reference voltage applied through the j-th sensing line SLj, to the anode electrode of the light-emitting element LD.”), and
a light emitting diode (LD) connected to the storage capacitor, the reference transistor, and a low-level voltage (ELVSS) (Park: see FIG. 2, “[0060]… The driving voltage may include… a low-potential driving voltage ELVSS….”, “[0070] A first electrode of the storage capacitor Cst is electrically connected to the first node N1, and a second electrode of the storage capacitor Cst receives a high-potential driving voltage ELVDD. The storage capacitor Cst may be charged with a voltage corresponding to the difference between a voltage applied to the first node N1 and the high-potential driving voltage ELVDD.”, “[0071] A first electrode (for example, a source electrode) of the driving transistor DT receives the high-potential driving voltage ELVDD, and a second electrode (for example, a drain electrode) of the driving transistor DT is electrically connected to a first electrode (for example, an anode electrode) of the light-emitting element LD. A gate electrode of the driving transistor DT is electrically connected to the first node N1. The driving transistor DT is turned on when a voltage at a gate-on level is applied through the first node N1….”, “[0072]… [A] second electrode (for example, a drain electrode) of the sensing transistor SST is electrically connected to the first electrode (for example, the anode electrode) of the light-emitting element LD….”, and “[0073]… The light-emitting element LD may be an organic light-emitting diode (OLED) or an ultra-small inorganic light-emitting diode having a size in a micro to nanoscale range…. Hereinafter, aspects in which the light-emitting element LD is an organic light-emitting diode will be described.”).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to include: the features taught by Jo, such that Park as modified teaches: a switching transistor switched according to a scan signal and connected to a data signal (as taught by Jo); a storage capacitor connected to the switching transistor (as taught by Jo); the driving transistor switched according to a voltage of a capacitor electrode of the storage capacitor and connected to a high-level voltage (driving transistor of Park as modified combined with the driving transistor of Jo); a reference transistor switched according to a sensing signal and connected to the storage capacitor, the driving transistor and a reference signal (driving transistor of Park as modified combined with the reference transistor of Jo), and the light emitting diode connected to the storage capacitor, the driving transistor, the reference transistor, and a low-level voltage (light emitting diode and driving transistor of Park as modified combined with the light emitting diode of Jo), for image display.
Regarding claim 15, Park as modified by Jo teaches:
The display apparatus of claim 14, wherein at least one of the switching transistor, the driving transistor, or the reference transistor is an oxide semiconductor thin film transistor (Jo:“[0075]… [E]ach of the switching transistor ST, the driving transistor DT, and the sensing transistor SST may be implemented as… an oxide thin-film transistor….” and “[0121] The light-shielding layer LS is placed in such a manner as to be overlapped by a semiconductor pattern of the driving transistor DT, particularly, the second channel CH2 when viewed from above, and may thus protect the oxide semiconductor device from external light….”; see also Park: the driving transistor is an oxide semiconductor thin film transistor; FIG. 9, “[0066] The thin film transistor 210 includes an active layer 211, a gate electrode 212, a source electrode 213, and a drain electrode….”, and “[0068]… The active layer 211 may be formed of… an oxide-based semiconductor material….”).
Regarding claim 17, Park as modified teaches:
The display apparatus of claim 1, further comprising:
a light shielding layer provided at the subpixel (Park: see FIG. 9 and “[0068]… Between the buffer layer 110 and the active layer 211, a light shielding layer and an insulating layer may be formed….”).
However, it is noted that Park as modified does not teach:
a buffer layer between the light shielding layer and the driving transistor;
an overcoat layer between the driving transistor and the light emitting diode; and
a passivation layer between the driving transistor and the overcoat layer.
Jo teaches:
a buffer layer (BUF in FIG. 4) between a light shielding layer (LS) and a driving transistor (DT) (Jo: see FIG. 4, “[0121] The light-shielding layer LS is placed in such a manner as to be overlapped by a semiconductor pattern of the driving transistor DT ….”, and “[0126] A buffer layer BUF is placed on the substrate SUB so as to cover the light-shielding layer LS….”);
an overcoat layer (OC) between the driving transistor and a light emitting diode (LD) (Jo: see FIG. 4, “[0073]… The light-emitting element LD may be an organic light-emitting diode (OLED) or an ultra-small inorganic light-emitting diode having a size in a micro to nanoscale range, but the present disclosure is not limited thereto. Hereinafter, aspects in which the light-emitting element LD is an organic light-emitting diode will be described.”, and “[0138]… [A]n overcoat layer OC….”); and
a passivation layer (PAS) between the driving transistor and the overcoat layer (Jo: see FIG. 4 and “[0138] On the passivation layer PAS, an overcoat layer OC may be formed….”).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to include: the features taught by Jo, such that Park as modified teaches: a buffer layer between the light shielding layer and the driving transistor (light shielding layer and driving transistor of Park as modified combined with the buffer and light shielding layers and driving transistor of Jo); an overcoat layer between the driving transistor and the light emitting diode (driving transistor and light emitting diode of Park as modified combined with the overcoat layer, driving transistor, and light emitting diode of Jo); and a passivation layer between the driving transistor and the overcoat layer (driving transistor of Park as modified combined with the passivation and overcoat layers and driving transistor of Jo), to protect and provide a buffer between display elements.
Regarding claim 18, Park as modified by Jo teaches:
The display apparatus of claim 17, wherein the driving transistor includes:
an active layer (ACT in Jo) corresponding to the light shielding layer and disposed over the buffer layer (Jo: see FIG. 4, “[0088] The driving transistor DT may include a second gate electrode GE2, a second source electrode SE2, and a second drain electrode DE2.”, “[0089] The second gate electrode GE2 may be placed overlapping a second channel CH2 formed in the active layer ACT….”, and “[0121] The light-shielding layer LS is placed in such a manner as to be overlapped by a semiconductor pattern of the driving transistor DT, particularly, the second channel CH2 when viewed from above….”, see also “[0090] The second source electrode SE2 may be connected to a second source area SA2 formed on a first side of the second channel CH2 in the active layer ACT….” and “[0091] The second drain electrode DE2 may be connected to a second drain area DA2 formed on a second side of the second channel CH2 in the active layer ACT….”);
a gate insulating layer (GI) and a gate electrode (GE2) sequentially disposed over the active layer (Jo: see FIG. 4, “[0088] The driving transistor DT may include a second gate electrode GE2….”, “[0089] The second gate electrode GE2 may be placed overlapping a second channel CH2 formed in the active layer ACT….”, and “[0129]… [A] gate insulation layer GI….”);
a source electrode (SE2) connected to a first end region of the active layer and the light shielding layer (Jo: a source electrode connected to a first end region of the active layer; see FIG. 4, “[0088] The driving transistor DT may include… a second source electrode SE2….”, and “[0090] The second source electrode SE2 may be connected to a second source area SA2 formed on a first side of the second channel CH2 in the active layer ACT….”; it would have been obvious to include: a source electrode connected to the light shielding layer, since it would have been within the general skill of one of ordinary skill in the art to select features on the basis of their suitability for the intended use to provide image display); and
a drain electrode (DE2) connected to a second end region of the active layer (Jo: see FIG. 4, “[0088] The driving transistor DT may include… a second drain electrode DE2.”, and “[0091] The second drain electrode DE2 may be connected to a second drain area DA2 formed on a second side of the second channel CH2 in the active layer ACT….”).
The motivation to combine the references is to provide a driving transistor for image display.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Park in view of Jo, in further view of Yuan et al. in US 2020/0066210 A1 (hereinafter Yuan).
Regarding claim 16, Park as modified by Jo teaches:
The display apparatus of claim 14, wherein the gate driving unit includes a clock signal (e.g., CL2 in FIG. 5 in Park), a stage circuit block (e.g., ST 1 block) (Park: FIGs. 5-6, “[0042]… [T]he first… gate driver[] 11… includes first through n-th stages ST1 through STn…. The two clock signal lines CL1 and CL2 may be alternately connected to the first through n-th stages ST1 through STn….”, and “[0044] The k-th stage STk includes a pull-up node NQ, a pull-down node NQB, a pull-up transistor TU, a pulldown transistor TD….”),
wherein the stage circuit block generates and transmits the scan signal to the switching transistor through the gate line and generates and transmits the sensing signal to the reference transistor through the gate line (Park: FIGs. 5-6 and “[0043] The k-th stage… is the start voltage of the start signal line (STL) or the output signal of the previous stage and any one of the clock lines (CL1, CL2) And outputs the clock signal input to the kth gate line as a gate signal. For example, the first stage ST1 receives the start voltage of the start signal line STL and the second clock signal of the second clock line CL2, and outputs a first gate signal to the first gate line GL1 Output….”; Jo: FIG. 2, “[0069] The switching transistor ST is turned on when a gate signal at a gate-on level is applied through the i-th first gate line GL1i….”, and “[0072]… A gate electrode of the sensing transistor SST is electrically connected to an i-th second gate line GL2i. The sensing transistor SST is turned on when a sensing signal at a gate-on level is applied through the i-th second gate line GL2i….”; i.e., stage circuit block of Park generates and transmits the scan signal of Park and the sensing signal of Jo), and
wherein the line portion includes the clock signal, and the stage portion includes the stage circuit block (Park: see FIG. 5).
However, it is noted that Park as modified by Jo does not teach:
the clock signal is a clock signal block,
a high-level voltage block, and a low-level voltage block, and
wherein the line portion includes the clock signal block and the high-level voltage block.
Yuan teaches:
a clock signal block (102 in FIG. 4), a high-level voltage block (104), and a low-level voltage block (104) (Yuan: see FIG. 4, “[0039]… As shown in FIG. 4, the gate drive output stage circuit includes:”, “[0041] a second control sub-circuit 102, configured to transmit a first clock signal CLK1 of a first clock terminal…;”, and “[0043] a second output sub-circuit 104, configured to transmit a first power supply voltage signal VGH of a first power supply voltage terminal….”, see also FIG. 1).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to include: the features taught by Yuan, such that Park as modified teaches: wherein the gate driving unit includes a clock signal block, a high-level voltage block, a stage circuit block, and a low-level voltage block (gate driving unit, clock signal, and stage circuit block of Park as modified combined with the clock signal, high-level voltage, and low-level voltage blocks of Yuan), and wherein the line portion includes the clock signal block and the high-level voltage block, and the stage portion includes the stage circuit block (line and stage portions, clock signal, and stage circuit block of Park as modified combined with the clock signal and high-level voltage blocks of Yuan), to provide gate driving signals for image display.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Park in view of Choi et al. in US 2022/0302421 A1 (hereinafter Choi).
Regarding claim 19, Park as modified teaches:
The display apparatus of claim 1.
However, it is noted that Park as modified does not teach:
further comprising a first encapsulating layer and a second encapsulating layer sequentially disposed over the light emitting diode,
wherein the first encapsulating layer includes at least one of an inorganic insulating material or an organic insulating material, and
wherein the second encapsulating layer includes a metallic material or glass.
Choi teaches:
a first encapsulating layer (310 and 320 in FIG. 19) and a second encapsulating layer (330) sequentially disposed over a light emitting diode (OLED1) (Park: FIG. 19, “[0253]… [T]he encapsulation layer 300… may be… arranged on the first organic light-emitting diode OLED1.”, and “[0254]… [T]he encapsulation layer 300 may include a first inorganic layer 310, a second inorganic layer 330, and an organic layer 320 therebetween.”),
wherein the first encapsulating layer includes at least one of an inorganic insulating material or an organic insulating material (Park: FIG. 19, “[0255] The first… inorganic layer[] 310… include[s] at least one inorganic insulating material….”, and “[0256] The organic layer 320 may include a polymer-based material. The polymer-based material may include… polyethylene….”), and
wherein the second encapsulating layer includes a metallic material or glass (Park: FIG. 19 and “[0255] The… second inorganic layer[]… 330 may… include aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and/or silicon oxynitride.”).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to include: the features taught by Jo, such that Park as modified teaches: further comprising a first encapsulating layer and a second encapsulating layer sequentially disposed over the light emitting diode (light emitting diode of Park as modified combined with the first and second encapsulating layers and light emitting diode of Choi), wherein the first encapsulating layer includes at least one of an inorganic insulating material or an organic insulating material (as taught by Choi), and wherein the second encapsulating layer includes a metallic material or glass (as taught by Choi), to protect display elements.
Conclusion
Applicants’ amendments necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicants are reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to K. Kiyabu whose telephone number is (571) 270-7836. The examiner can normally be reached Monday to Thursday 9:00 A.M. - 5:00 P.M. ET.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Temesghen Ghebretinsae, can be reached at (571) 272-3017. The fax number for the organization where this application or proceeding is assigned is (571) 273-8300.
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/K. K./
Examiner, Art Unit 2626
/TEMESGHEN GHEBRETINSAE/Supervisory Patent Examiner, Art Unit 2626 8/31/26B
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