DETAILED ACTION
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
General Remarks
2. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection.
3. When responding to this office action, applicants are advised to provide the examiner with paragraph numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
4. Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable
interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Election/Restrictions
5. Applicant's election with traverse of Species I, Claims 1-10 and 19-21 in the reply filed on 7/14/2026 is acknowledged. The traversal is on the ground(s) that a serious search and/or examination burden has not been established between Species I and II.
This is not found persuasive because species I comprises mutually exclusive characteristics from species II, namely species I does not comprise a gate, channel or doped regions adjacent to the first/second isolation passivation layers (found in species II). Secondly, species II does not comprise first/second isolation passivation layers which are adjacent to the first and second electrodes. Therefore, due to having mutually exclusive and distinct characteristics, there is a search burden on the examiner.
The requirement is still deemed proper and is therefore made FINAL.
Claim Rejections - 35 USC § 102
6. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
7. Claims 1, 3-4, 7 and 21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chavan, Ashonita A. et al. (Pub No. US 20200373314 A1) (hereinafter, Chavan).
Chavan, Fig 9: Ferroelectric capacitor over substrate
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Re Claim 1, (Original) Chavan teaches a ferroelectric memory, comprising:
a substrate (12; Fig 9; ¶[0021]); and
a plurality of memory cells (Ferroelectric FET used in memory cells; ¶¶[0006-0007]), formed on the substrate, wherein each memory cell comprises a ferroelectric capacitor (Ferroelectric capacitor; 40e; Fig 9; ¶[0039]), wherein the ferroelectric capacitor comprises:
a first electrode (Conductor material; 42; Fig 9; ¶[0035]) and a second electrode (Conductive material; 26; Fig 9; ¶[0035]) that are stacked;
a ferroelectric layer (Ferroelectric insulator material; 14; Fig 9; ¶[0035]; Note: Per ¶[0028] the composite stack 16 renders insulator material 14 to be ferroelectric), formed between the first electrode and the second electrode, wherein the ferroelectric layer comprises a hafnium oxide-based material (Ferroelectric insulator material 14 may be Hafnium oxide; ¶[0025]);
a first isolation passivation layer (Lower composite stack; 16; Fig 9; ¶[0026]), formed between the first electrode and the ferroelectric layer; and
a second isolation passivation layer (Upper composite stack; 16; Fig 9; ¶[0026]), formed between the second electrode and the ferroelectric layer, wherein the first isolation passivation layer is configured to suppress diffusion of an oxygen element in the ferroelectric layer to the first electrode, and the second isolation passivation layer is configured to suppress diffusion of the oxygen element in the ferroelectric layer to the second electrode (Per ¶[0025] the passivation layers, i.e. composite stacks 16 are required to be of an oxide material, which inherently suppresses the diffusion of oxygen to the electrodes although Chavan remains silent on the inherent characteristic) (See MPEP § 2112 (III)).
Re Claim 3, (Original) Chavan teaches the ferroelectric memory according to claim 1, wherein at least one of the first isolation passivation layer (Lower composite stack; 16; Fig 9; ¶[0026]) or the second isolation passivation layer (Upper composite stack; 16; Fig 9; ¶[0026]) comprises at least one of metal oxide or a metal simple substance (Non-ferroelectric metal oxides; ¶[0026]).
Re Claim 4, (Original) Chavan teaches the ferroelectric memory according to claim 1, wherein at least one of the first isolation passivation layer (Lower composite stack; 16; Fig 9; ¶[0026]) or the second isolation passivation layer (Upper composite stack; 16; Fig 9; ¶[0026]) comprises at least one of titanium oxide, tungsten oxide, tantalum oxide, niobium oxide, aluminum oxide, magnesium oxide, cerium oxide, platinum, or palladium (May be titanium oxide; ¶[0026]).
Re Claim 7, (Original) Chavan teaches the ferroelectric memory according to claim 1, wherein the first electrode (Conductor material; 42; Fig 9; ¶[0035]), the first isolation passivation layer (Lower composite stack; 16; Fig 9; ¶[0026]), the ferroelectric layer (Ferroelectric insulator material; 14; Fig 9; ¶[0035]; Note: Per ¶[0028] the composite stack 16 renders insulator material 14 to be ferroelectric), the second isolation passivation layer (Upper composite stack; 16; Fig 9; ¶[0026]), and the second electrode (Conductive material; 26; Fig 9; ¶[0035]) are stacked in a direction perpendicular to the substrate (12; Fig 9; ¶[0021]).
Re Claim 21, (New) Chavan teaches a ferroelectric memory, comprising:
a substrate (12; Fig 9; ¶[0021]); and
a plurality of memory cells (Ferroelectric FET used in memory cells; ¶¶[0006-0007]), formed on the substrate, wherein each memory cell comprises:
a ferroelectric layer (Ferroelectric insulator material; 14; Fig 9; ¶[0035]; Note: Per ¶[0028] the composite stack 16 renders insulator material 14 to be ferroelectric), wherein the ferroelectric layer comprises a hafnium oxide-based material (Ferroelectric insulator material 14 may be Hafnium oxide; ¶[0025]);
a first isolation passivation layer (Lower composite stack; 16; Fig 9; ¶[0026]), disposed on a first side of the ferroelectric layer; and a second isolation passivation layer (Upper composite stack; 16; Fig 9; ¶[0026]), disposed on a second side of the ferroelectric layer that is opposite the first side, wherein the first isolation passivation layer is configured to suppress diffusion of an oxygen element. (Per ¶[0025] the passivation layers, i.e. composite stacks 16 are required to be of an oxide material, which inherently suppresses the diffusion of oxygen to the electrodes although Chavan remains silent on the inherent characteristic) (See MPEP § 2112 (III))
Claim Rejections - 35 USC § 103
8. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
9. Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Chavan, Ashonita A. et al. (Pub No. US 20200373314 A1) (hereinafter, Chavan), and further in view of Guo, Xinwei (Pub No. US 20210020222 A1) (hereinafter, Guo).
Re Claim 19, (Original) Chavan teaches an electronic device, comprising:
a ferroelectric memory comprising: a substrate (12; Fig 9; ¶[0021]); and
a plurality of memory cells (Ferroelectric FET used in memory cells; ¶¶[0006-0007]), formed on the substrate, wherein each memory cell comprises a ferroelectric capacitor (Ferroelectric capacitor; 40e; Fig 9; ¶[0039]), wherein the ferroelectric capacitor comprises:
a first electrode (Conductor material; 42; Fig 9; ¶[0035]) and a second electrode (Conductive material; 26; Fig 9; ¶[0035]) that are stacked;
a ferroelectric layer (Ferroelectric insulator material; 14; Fig 9; ¶[0035]; Note: Per ¶[0028] the composite stack 16 renders insulator material 14 to be ferroelectric), formed between the first electrode and the second electrode, wherein the ferroelectric layer comprises a hafnium oxide-based material (Ferroelectric insulator material 14 may be Hafnium oxide; ¶[0025]);
a first isolation passivation layer (Lower composite stack; 16; Fig 9; ¶[0026]), formed between the first electrode and the ferroelectric layer; and
a second isolation passivation layer (Upper composite stack; 16; Fig 9; ¶[0026]), formed between the second electrode and the ferroelectric layer, wherein the first isolation passivation layer is configured to suppress diffusion of an oxygen element in the ferroelectric layer to the first electrode, and the second isolation passivation layer is configured to suppress diffusion of the oxygen element in the ferroelectric layer to the second electrode (Per ¶[0025] the passivation layers, i.e. composite stacks 16 are required to be of an oxide material, which inherently suppresses the diffusion of oxygen to the electrodes although Chavan remains silent on the inherent characteristic) (See MPEP § 2112 (III)).
However, Chavan does not teach a processor; and
a ferroelectric memory using, wherein the processor is electrically connected to the ferroelectric memory.
In the same field of endeavor, Guo teaches a processor (Processor; 120; Fig 1; ¶[0123]); and
a ferroelectric memory (Ferroelectric memory cell, i.e. of a memory array; Fig 1; ¶[0123]) using, wherein the processor is electrically connected to the ferroelectric memory.
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have used a processor and a ferroelectric memory using, wherein the processor is electrically connected to the ferroelectric memory, as taught by Guo, for the semiconductor structure of Chavan. One would have been motivated to do this with a reasonable expectation of success because a processor, e.g. a central processing unit (CPU) is required to control portions of a system comprising memory cells within a memory device, such that commands may be executed by the memory device (Guo; ¶[0021-0023]).
Allowable Subject Matter
10. Claims 2, 5-6, 8-10 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 2, the closest prior art Chavan, Ashonita A. et al. (Pub No. US 20200373314 A1) (hereinafter, Chavan) either singularly or in combination fails to anticipate or render obvious
“The ferroelectric memory according to claim 1, wherein at least one of the first isolation passivation layer or the second isolation passivation layer comprises a metal material having chemical inertia;
chemical inertia of the first isolation passivation layer is greater than both chemical inertia of the ferroelectric layer and chemical inertia of the first electrode; and
chemical inertia of the second isolation passivation layer is greater than both the chemical inertia of the ferroelectric layer and chemical inertia of the second electrode,”
in combination with all other limitations in the claim(s) as claimed and defined by applicant.
Regarding claim 5, the closest prior art Chavan, Ashonita A. et al. (Pub No. US 20200373314 A1) (hereinafter, Chavan) either singularly or in combination fails to anticipate or render obvious
“The ferroelectric memory according to claim 1, wherein the first isolation passivation layer comprises at least one of an amorphous structure or an orthorhombic crystalline phase structure;
the second isolation passivation layer comprises at least one of the amorphous structure or the orthorhombic crystalline phase structure; and
the first isolation passivation layer is further configured to suppress impact of the first electrode on a crystalline orientation of the ferroelectric layer, the second isolation passivation layer is further configured to suppress impact of the second electrode on the crystalline orientation of the ferroelectric layer, and the first isolation passivation layer and the second isolation passivation layer enable the ferroelectric layer to present an orthorhombic crystalline phase,”
in combination with all other limitations in the claim(s) as claimed and defined by applicant.
Regarding claim 8, the closest prior art Chavan, Ashonita A. et al. (Pub No. US 20200373314 A1) (hereinafter, Chavan) in view of Zeng, Bin-jian et al. (Pub No. CN 113871395 A) (hereinafter, Zeng) either singularly or in combination fails to anticipate or render obvious
“The ferroelectric memory according to claim 1, wherein the first electrode, the first isolation passivation layer, the ferroelectric layer, the second isolation passivation layer, and the second electrode are stacked in a direction parallel to the substrate,”
in combination with all other limitations in the claim(s) as claimed and defined by applicant.
Regarding claim 9, the closest prior art Chavan, Ashonita A. et al. (Pub No. US 20200373314 A1) (hereinafter, Chavan) in view of Kakushima, Kuniyuki et al. (Pub No. US 20230012093 A1) (hereinafter, Kakushima) either singularly or in combination fails to anticipate or render obvious
“The ferroelectric memory according to claim 1, wherein each memory cell further comprises a first transistor, a second transistor, a control line, a write bit line, a read bit line, a source line, and a word line, wherein a control end of the first transistor is electrically connected to the control line, a first end of the first transistor is electrically connected to the first electrode, and a second end of the first transistor is electrically connected to the write bit line;
a control end of the second transistor is electrically connected to the first electrode, a first end of the second transistor is electrically connected to the source line, and a second end of the second transistor is electrically connected to the read bit line; and
the second electrode is electrically connected to the word line,”
in combination with all other limitations in the claim(s) as claimed and defined by applicant.
Regarding claim 10, the closest prior art Chavan, Ashonita A. et al. (Pub No. US 20200373314 A1) (hereinafter, Chavan) either singularly or in combination fails to anticipate or render obvious
“The ferroelectric memory according to claim 1, wherein at least one of a
thickness of the first isolation passivation layer or a thickness of the second isolation passivation layer in a stacking direction of the first electrode and the second electrode is 0.5 nm to 5 nm.
at least one of the first isolation passivation layer or the second isolation passivation layer comprises at least one of an amorphous structure or an orthorhombic crystalline phase structure at least one of the amorphous structure or the orthorhombic crystalline phase structure,”
in combination with all other limitations in the claim(s) as claimed and defined by applicant.
Regarding claim 20, the closest prior art Chavan, Ashonita A. et al. (Pub No. US 20200373314 A1) (hereinafter, Chavan) either singularly or in combination fails to anticipate or render obvious
“The ferroelectric memory according to claim 19, wherein at least one of the first isolation passivation layer or the second isolation passivation layer comprises a metal material having chemical inertia;
chemical inertia of the first isolation passivation layer is greater than both chemical inertia of the ferroelectric layer and chemical inertia of the first electrode; and
chemical inertia of the second isolation passivation layer is greater than both the chemical inertia of the ferroelectric layer and chemical inertia of the second electrode,”
in combination with all other limitations in the claim(s) as claimed and defined by applicant.
11. In the instant case, re claims 2 and 20, Chavan does not teach a first or second passivation layer of claim 1 comprising a metal material with chemical inertia. Further, chemical inertia is not an inherent characteristic of the metal materials disclosed by Chavan per [0026]. Therefore, Chavan cannot be combined with any other prior art elements to obtain a predictable result, i.e. a first or second passivation layer of claim 1 comprising of a metal material having chemical inertia.
Re claims 5 and 10, Chavan does not teach a first or second passivation layers of claim 1 comprising either an amorphous structure or orthorhombic crystalline phase structure. Therefore, Chavan cannot be combined with any other prior art elements to obtain a predictable result, i.e. a first or second passivation layer of claim 1 comprising of an amorphous structure or orthorhombic crystalline phase structure.
Re claim 8, Chavan does not teach "wherein the first electrode, the first isolation passivation layer, the ferroelectric layer, the second isolation passivation layer, and the second electrode are stacked in a direction parallel to the substrate." Further, Zeng does teach a ferroelectric layer and first/second isolation passivation layers stacked parallel to a substrate, however the electrodes are stacked in a direction perpendicular to the substrate. Therefore, Chavan in view of Zeng cannot replicate the said invention of claim 8.
Re claim 9, Kakushima is the closest prior art which discloses in Figure 25A two transistors within a memory cell which connect to bit lines which may perform read/write operations as shown in Figure 25B, however, for these specific memory cells, a control line and source line are missing. Kakushima discloses a source line in NOR-type memory cell, however, that is not applicable to the memory cell of Figure 25A. Therefore, the elements of Chavan in view of Kakushima cannot be combined to yield a predictable result.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
[1] Hu, Yushi (Pub No. US 20210091096 A1) discloses a ferroelectric memory device with reduced edge defects by covering the edge region exposed by the first and second electrode with a healing layer or block layer.
[2] Moon, Taehwan et al. (Pub No. US 12087840 B2) discloses a ferreoelectric semiconductor device and capacitor comprising of a ferroelectric layer over a substrate with doped regions, designed to have relatively less leakage current.
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/T.E.D./
Examiner
Art Unit 2817
/ELISEO RAMOS FELICIANO/Supervisory Patent Examiner, Art Unit 2817
