The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claims 1-20 are presented for examination in this application (18/589,289) filed on February 27, 2024.
The Examiner cites particular sections in the references as applied to the claims below for the convenience of the applicant(s). Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant(s) fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
Claims 1-20 are pending for consideration.
Drawings
The drawings submitted on February 27, 2024 have been considered and accepted.
Information Disclosure Statement
Acknowledgment is made of the information disclosure statements filed on 2/27/2024. U.S. patents and Foreign Patents have been considered.
Claim Rejections - 35 U.S.C. 112
7.The following is a quotation of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), first paragraph:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same and shall set forth the best mode contemplated by the inventor of carrying out his invention.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 7 and 9 are rejected under 35 U.S.C. 112 (b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as claims recite “enables the data…to be updated”, claims are rejected under 35 U.S.C 112(b) as it is unclear if enabling data to be updated will result in updating the data or just have the capability of being updated. Claim 7 further recites “indicates completion of writing….indicates a failure of writing”, where it is unclear if writing refers to writing the data to the third volatile memory, data to be written in the first nonvolatile memory, or else.
Claim 15 is rejected under 35 U.S.C. 112 (a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as claims recite “during a period when the controller is not accessing the first die or the second die” claim 15, claims are rejected under 35 U.S.C 112(a) as specification recites the controller 2 can access only some of the page buffers, is considered. In this case, the controller 2 cannot freely access the plurality of page buffers and cannot effectively utilize the plurality of page buffers. The second embodiment is characterized in that when the controller 2 can access only some of the page buffers of the die 5, the storage capacity of the buffer memory 11 of the controller 2 can be reduced, similar to the first embodiment (Paragraph 0074), “the controller 2 also writes the same data as that of the write target die 5a to the page buffer 43 of the non-write target die 5b. The controller 2 specifies which page buffer 43 of the non-write target die 5b the data should be stored in depending on which of L/M/U/T the data is to be written into. With this, the computing unit 42 of the non-write target die 5b transfers the data transferred from the controller 2 to the specific page buffer 43a to another page buffer 43b” (Paragraph 0080) as no further disclosure on any of such details provided in the specification and how the controller does not have access to the dies while the writing operation is completed.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
10. Claims 1-6, 8, 11-13 and 15-20 are rejected under 35 U.S.C. 103(a) as being unpatentable by Stoller et al. (US PGPUB 2021/0389949) (hereinafter Stoller), in view of Morishita et al. (US PGPUB 2015/0370713 hereinafter referred to as Morishita).
As per independent claim 1, Stoller discloses a memory system comprising: a first die; a second die; and a controller configured to control writing and reading of data to and from the first die and the second die [(Paragraphs 0038-0042 and 0066-0069; Figs. 1 and 4) where Stoller teaches where Memory device 100 also incorporates one or more memory die interfaces 125 between the processing circuitry 110 of the controller 105 and at least some portion of the memory dies 130-A-130N+1 within memory device 100. Memory die interface 125 may be part of controller 105 or may be implemented by separate circuitry. For example, in the example of a UFS device, one or more of the memory die interfaces 125 will be a suitable memory interface, for example an Open NAND Flash Interface (“ONFI”), such as that defined by the ONFI 4.0 Specification, or later versions or revisions thereof. Components of the memory device 100, such as controller 105, may include a random access memory (RAM) 120 for performing the operations of the memory device 100. The random access memory 120 may be separate from the controller 105 or, as shown, may be integrated in the controller 105 to correspond to the claimed limitation], wherein the first die includes a first nonvolatile memory and a first volatile memory, and the second die includes a second nonvolatile memory and a second volatile memory, and the controller includes a third volatile memory [(Paragraphs 0035, 0038-0042 and 0066-0069; Figs. 1 and 4) where Stoller teaches where Stoller teaches where FIG. 4 illustrates an example block diagram of a memory die 400 according to some examples of the present disclosure. Memory die 400 may be one example of memory die 130A-130N+1 of FIG. 1. Memory die 400 may include a memory array 402 having a plurality of memory cells 404, and one or more circuits or components to provide communication with, or perform one or more memory operations on, the memory array 402. The memory die 400 can include a row decoder 412, a column decoder 414, sense amplifiers 420, a page buffer 422, a selector 424, an input/output (I/O) circuit 426, and a dedicated memory controller, in the form of memory control unit 430, including processing circuitry, potentially including one or more processors; the controller 105, may include a random access memory (RAM) 120 for performing the operations of the memory device 100. The random access memory 120 may be separate from the controller 105 or, as shown, may be integrated in the controller 105 to correspond to the claimed limitation], and the controller, during writing of data into the first die, stores the data in the third volatile memory, writes the data, which is stored in the third volatile memory and is to be stored in the first die, to the first volatile memory of the first die and the second volatile memory of the second die in parallel [(Paragraphs 0038-0042 and 0066-0069; Figs. 1 and 4) where Stoller teaches where FIG. 4 illustrates an example block diagram of a memory die 400 according to some examples of the present disclosure. Memory die 400 may be one example of memory die 130A-130N+1 of FIG. 1. Memory die 400 may include a memory array 402 having a plurality of memory cells 404, and one or more circuits or components to provide communication with, or perform one or more memory operations on, the memory array 402. The memory die 400 can include a row decoder 412, a column decoder 414, sense amplifiers 420, a page buffer 422, a selector 424, an input/output (I/O) circuit 426, and a dedicated memory controller, in the form of memory control unit 430, including processing circuitry, potentially including one or more processors, as described earlier herein to correspond to the claimed limitation].
Stoller does not appear to explicitly disclose the controller, during writing of data into the first die, stores the data in the third volatile memory, writes the data, which is stored in the third volatile memory and is to be stored in the first die, to the first volatile memory of the first die and the second volatile memory of the second die in parallel.
However, Morishita discloses the controller includes a third volatile memory, and the controller, during writing of data into the first die, stores the data in the third volatile memory, writes the data, which is stored in the third volatile memory and is to be stored in the first die, to the first volatile memory of the first die and the second volatile memory of the second die in parallel [(Paragraphs 0137-0147; FIGs. 13 and 14) wherein Morishita discloses in a write two-stage transfer, the FE-I/F #0 adds a guarantee code to write data from the host computer 1 and stores the write data to which the guarantee code has been added in the BS area #0 (a BS area reserved from the buffer area #0 for the two-stage transfer) (13-1). When parity ungenerated dirty data is stored in the write side 42a of the cache area #0, the CPU #0 verifies the guarantee code (13-2). Moreover, in the event that the write side 42a and the write side 42b are newly allocated during a reception of a write request, when parity ungenerated dirty data is not stored, the verification of the guarantee code of (13-2) is omitted. When a bit error has not occurred, the CPU #0 copies write data from the BS area #0 to the write side 42a of the cache area #0 (13-3) and further copies the write data to the write side 42b of the cache area #1 (13-4). The CPU #1 verifies the guarantee code of the write data stored in the write side 42b (13-5). If a bit error has not occurred, the CPU #1 reports write request completion to the host computer 1 via the CPU #0 and the FE-I/F #0 (13-6). On the other hand, as shown in FIG. 14, in a write direct transfer, the FE-I/F #0 adds a guarantee code to write data from the host computer 1 and stores the write data to which a guarantee code has been added in the write side 42a of the cache area #0 (14-1). When parity ungenerated dirty data is stored in the write side 42a, the CPU #0 verifies the guarantee code (14-2). Moreover, in a similar manner to a write two-stage transfer, in the event that the write side 42a and the write side 42b are newly allocated during a reception of a write request, when parity ungenerated dirty data is not stored, wherein the two-stage transfer of write data and copying data in buffer areas and caches in parallel of Morishita to correspond to the claimed limitation].
Stoller and Morishita are analogous art because they are from the same field of endeavor of data storage management.
Before the effective filing date of the claimed inventions, it would have been obvious to one of ordinary skill in the art, having the teachings of Stoller and Morishita before him or her, to modify the method of Stoller to include the two-stage transfer of Morishita because it will enhance data access.
The motivation for doing so would be [“access to a storage apparatus during generation of the redundant data is reduced and processing efficiency of the storage system is improved” (Paragraph 0004 by Morishita)].
Therefore, it would have been obvious to combine Stoller and Morishita to obtain the invention as specified in the instant claim.
As per dependent claim 2, Morishita discloses wherein the first die writes the data written from the third volatile memory to the first volatile memory to the first nonvolatile memory [(Paragraphs 0138-0142; Figs. 1 and 13-14) where Morishita teaches where, in a write two-stage transfer, the FE-I/F #0 adds a guarantee code to write data from the host computer 1 and stores the write data to which the guarantee code has been added in the BS area #0 (a BS area reserved from the buffer area #0 for the two-stage transfer) (13-1). When parity ungenerated dirty data is stored in the write side 42a of the cache area #0, the CPU #0 verifies the guarantee code (13-2). Moreover, in the event that the write side 42a and the write side 42b are newly allocated during a reception of a write request, when parity ungenerated dirty data is not stored, the verification of the guarantee code of (13-2) is omitted. When a bit error has not occurred, the CPU #0 copies write data from the BS area #0 to the write side 42a of the cache area #0 (13-3) and further copies the write data to the write side 42b of the cache area #1 (13-4). The CPU #1 verifies the guarantee code of the write data stored in the write side 42b (13-5). If a bit error has not occurred, the CPU #1 reports write request completion to the host computer 1 via the CPU #0 and the FE-I/F #0 (13-6) to correspond to the claimed limitation].
As per dependent claim 3, Morishita discloses wherein during writing of multi-bit data to the first nonvolatile memory, the controller controls the first die to write the same multi-bit data into the first nonvolatile memory multiple times [(Paragraphs 0191-0193; Figs. 11 and 13-14) where Morishita teaches where, the CPU 230 determines whether the storing of the write data in the cache area 244 of the other controller has normally ended (step 1118). This determination is made based on a result of copy execution in step 1116, a data guarantee code verification result, or the like. When storing has ended normally (step 1118: Yes), processing proceeds to step 1125. When storing has not ended normally (step 1118: No), since a data transfer failure or the like due to a temporary failure or the like of hardware or the like is assumed, the CPU 230 retries copying of the write data between the controllers. First, the CPU 230 initializes the number of retries (step 1119), and in a manner comparable to step 1116, retries copying (by DMA or the like) of the write data from the write side of the host controller to the write side of the other controller (step 1120). Subsequently, in a manner comparable to step 1117, the CPU 230 verifies the guarantee code of the write data by the CPU 230 (step 1121). Next, the CPU 230 determines whether the retry has ended normally (step 1122). This determination is made based on a result of the retried copy execution, a data guarantee code verification result, or the like. When the retry has ended normally (step 1122: Yes), processing proceeds to step 1125. When the retry has not ended normally (step 1122: No), the CPU 230 adds the number of retries (step 1123) and determines whether the number of retries has exceeded a threshold (step 1124). When the number of retries has exceeded the threshold (step 1124: Yes), processing proceeds to step 1129. When the number of retries has not exceeded the threshold (step 1124: No), the CPU 230 proceeds to step 1120 to once again retry the copying to correspond to the claimed limitation].
As per dependent claim 4, Morishita discloses wherein during writing of the same multi-bit data to the first nonvolatile memory a second time or later, the controller reads the multi-bit data from the second volatile memory [(Paragraphs 0191-0193; Figs. 11 and 13-14) where Morishita teaches where, the CPU 230 determines whether the storing of the write data in the cache area 244 of the other controller has normally ended (step 1118). This determination is made based on a result of copy execution in step 1116, a data guarantee code verification result, or the like. When storing has ended normally (step 1118: Yes), processing proceeds to step 1125. When storing has not ended normally (step 1118: No), since a data transfer failure or the like due to a temporary failure or the like of hardware or the like is assumed, the CPU 230 retries copying of the write data between the controllers. First, the CPU 230 initializes the number of retries (step 1119), and in a manner comparable to step 1116, retries copying (by DMA or the like) of the write data from the write side of the host controller to the write side of the other controller (step 1120). Subsequently, in a manner comparable to step 1117, the CPU 230 verifies the guarantee code of the write data by the CPU 230 (step 1121). Next, the CPU 230 determines whether the retry has ended normally (step 1122). This determination is made based on a result of the retried copy execution, a data guarantee code verification result, or the like. When the retry has ended normally (step 1122: Yes), processing proceeds to step 1125. When the retry has not ended normally (step 1122: No), the CPU 230 adds the number of retries (step 1123) and determines whether the number of retries has exceeded a threshold (step 1124). When the number of retries has exceeded the threshold (step 1124: Yes), processing proceeds to step 1129. When the number of retries has not exceeded the threshold (step 1124: No), the CPU 230 proceeds to step 1120 to once again retry the copying to correspond to the claimed limitation] and writes the multi-bit data read from the second volatile memory to the third volatile memory[(Paragraphs 0140-0143; Figs. 11 and 13-14) where Morishita teaches where, the CPU #0 copies write data from the BS area #0 to the write side 42a of the cache area #0 (13-3) and further copies the write data to the write side 42b of the cache area #1 (13-4). The CPU #1 verifies the guarantee code of the write data stored in the write side 42b (13-5). If a bit error has not occurred, the CPU #1 reports write request completion to the host computer 1 via the CPU #0 and the FE-I/F #0 (13-6). On the other hand, as shown in FIG. 14, in a write direct transfer, the FE-I/F #0 adds a guarantee code to write data from the host computer 1 and stores the write data to which a guarantee code has been added in the write side 42a of the cache area #0 (14-1). When parity ungenerated dirty data is stored in the write side 42a, the CPU #0 verifies the guarantee code (14-2). Moreover, in a similar manner to a write two-stage transfer, in the event that the write side 42a and the write side 42b are newly allocated during a reception of a write request, when parity ungenerated dirty data is not stored, the verification of the guarantee code of (14-2) is omitted to correspond to the claimed limitation], and then writes the multi-bit data written to the third volatile memory to the first volatile memory [(Paragraphs 0132-0134; Figs. 11 and 13-14) where Morishita teaches where, two-stage transfers include a write two-stage transfer and a read two-stage transfer. The write two-stage transfer is a two-stage transfer in which write data from the host computer 1 is transferred to the cache area 244 (CS area) via the buffer area 242 (BS area). The read two-stage transfer is a two-stage transfer in which read data in the cache memory 244 is transferred to the host computer 1 via the buffer area 242 (BS area). Meanwhile, direct transfers include a write direct transfer and a read direct transfer. The write direct transfer is a direct transfer in which write data from the host computer 1 is transferred to the cache area 244 (CS area) without involving the buffer area 242 (BS area). The read direct transfer is a direct transfer in which read data in the cache area 244 (CS area) is transferred to the host computer 1 without involving the buffer area 242 (BS area) to correspond to the claimed limitation].
As per dependent claim 5, Morishita discloses wherein the same multi-bit data is stored in the second volatile memory until the multiple times of writing to the first nonvolatile memory have completed [(Paragraphs 0191-0193; Figs. 11 and 13-14) where Morishita teaches where, the CPU 230 determines whether the storing of the write data in the cache area 244 of the other controller has normally ended (step 1118). This determination is made based on a result of copy execution in step 1116, a data guarantee code verification result, or the like. When storing has ended normally (step 1118: Yes), processing proceeds to step 1125. When storing has not ended normally (step 1118: No), since a data transfer failure or the like due to a temporary failure or the like of hardware or the like is assumed, the CPU 230 retries copying of the write data between the controllers. First, the CPU 230 initializes the number of retries (step 1119), and in a manner comparable to step 1116, retries copying (by DMA or the like) of the write data from the write side of the host controller to the write side of the other controller (step 1120). Subsequently, in a manner comparable to step 1117, the CPU 230 verifies the guarantee code of the write data by the CPU 230 (step 1121). Next, the CPU 230 determines whether the retry has ended normally (step 1122). This determination is made based on a result of the retried copy execution, a data guarantee code verification result, or the like. When the retry has ended normally (step 1122: Yes), processing proceeds to step 1125. When the retry has not ended normally (step 1122: No), the CPU 230 adds the number of retries (step 1123) and determines whether the number of retries has exceeded a threshold (step 1124). When the number of retries has exceeded the threshold (step 1124: Yes), processing proceeds to step 1129. When the number of retries has not exceeded the threshold (step 1124: No), the CPU 230 proceeds to step 1120 to once again retry the copying to correspond to the claimed limitation].
As per dependent claim 6, Morishita discloses wherein the controller stores different data in the third volatile memory after writing the multi-bit data to be written into the first nonvolatile memory into the first volatile memory and the second volatile memory [(Paragraphs 0058, 0078 and 0083; Figs. 1 and 4) where Morishita teaches where memory 240 has a buffer area 242 (#0, #1) and a cache area 244 (#0, #1). The buffer area 242 is a storage area in which data inputted/outputted to/from the cache area 244 is temporarily stored. Data read from the buffer area 242 is to be deleted from the buffer area 242. On the other hand, the cache area 244 is a storage area in which data inputted/outputted to/from the PDEV (RG) is temporarily stored. Unlike the buffer area 242, even if data is read from the cache area 244, the read data is not necessarily deleted from the cache area 244. While the buffer area 242 and the cache area 244 may be distributed among different memories, in the present example, the buffer area 242 and the cache area 244 are consolidated in the memory 240. In the cache area 244, a read side 41 (41a) may be reserved as an area in which data read from a PDEV (RG) is written or a write side 42 (42a, 42b) may be reserved as an area in which data to be written in a PDEV (RG) is written. In the description of the present example, unless specifically noted, both a read side and a write side are areas (typically, CS areas) that exist in the cache area 244; memory 240 is constituted by a program area 241, a buffer area 242, a management table area 243, and a cache area 244. Moreover, while the memory 240 included in both controllers 22 may be a non-volatile memory or a volatile memory, the cache area that stores dirty data may be made non-volatile by a backup power supply or the like to correspond to the claimed limitation].
As per dependent claim 8, Morishita discloses wherein the first nonvolatile memory and the second nonvolatile memory have a plurality of memory areas each of which is a unit of writing and reading, and the first volatile memory, the second volatile memory, and the third volatile memory have storage capacities corresponding to one or more of the memory areas [(Paragraphs 0058, 0078 and 0083; Figs. 1 and 4) where Morishita teaches where memory 240 has a buffer area 242 (#0, #1) and a cache area 244 (#0, #1). The buffer area 242 is a storage area in which data inputted/outputted to/from the cache area 244 is temporarily stored. Data read from the buffer area 242 is to be deleted from the buffer area 242. On the other hand, the cache area 244 is a storage area in which data inputted/outputted to/from the PDEV (RG) is temporarily stored. Unlike the buffer area 242, even if data is read from the cache area 244, the read data is not necessarily deleted from the cache area 244. While the buffer area 242 and the cache area 244 may be distributed among different memories, in the present example, the buffer area 242 and the cache area 244 are consolidated in the memory 240. In the cache area 244, a read side 41 (41a) may be reserved as an area in which data read from a PDEV (RG) is written or a write side 42 (42a, 42b) may be reserved as an area in which data to be written in a PDEV (RG) is written. In the description of the present example, unless specifically noted, both a read side and a write side are areas (typically, CS areas) that exist in the cache area 244; memory 240 is constituted by a program area 241, a buffer area 242, a management table area 243, and a cache area 244. Moreover, while the memory 240 included in both controllers 22 may be a non-volatile memory or a volatile memory, the cache area that stores dirty data may be made non-volatile by a backup power supply or the like to correspond to the claimed limitation].
As per dependent claim 11, Morishita discloses wherein each of the first volatile memory, the second volatile memory, and the third volatile memory has a plurality of memory areas, and the controller writes data stored in the plurality of memory areas in the third volatile memory into the first volatile memory and the second volatile memory in parallel [(Paragraphs 0140-0143; Figs. 11 and 13-14) where Morishita teaches where, the CPU #0 copies write data from the BS area #0 to the write side 42a of the cache area #0 (13-3) and further copies the write data to the write side 42b of the cache area #1 (13-4). The CPU #1 verifies the guarantee code of the write data stored in the write side 42b (13-5). If a bit error has not occurred, the CPU #1 reports write request completion to the host computer 1 via the CPU #0 and the FE-I/F #0 (13-6). On the other hand, as shown in FIG. 14, in a write direct transfer, the FE-I/F #0 adds a guarantee code to write data from the host computer 1 and stores the write data to which a guarantee code has been added in the write side 42a of the cache area #0 (14-1). When parity ungenerated dirty data is stored in the write side 42a, the CPU #0 verifies the guarantee code (14-2). Moreover, in a similar manner to a write two-stage transfer, in the event that the write side 42a and the write side 42b are newly allocated during a reception of a write request, when parity ungenerated dirty data is not stored, the verification of the guarantee code of (14-2) is omitted to correspond to the claimed limitation].
As per dependent claim 12, Morishita discloses wherein in response to a data read instruction from a host device, the controller reads read target data from the first volatile memory or the second volatile memory when the read target data is stored in the first volatile memory or the second volatile memory [(Paragraphs 0132-0134; Figs. 11 and 13-14) where Morishita teaches where, two-stage transfers include a write two-stage transfer and a read two-stage transfer. The write two-stage transfer is a two-stage transfer in which write data from the host computer 1 is transferred to the cache area 244 (CS area) via the buffer area 242 (BS area). The read two-stage transfer is a two-stage transfer in which read data in the cache memory 244 is transferred to the host computer 1 via the buffer area 242 (BS area). Meanwhile, direct transfers include a write direct transfer and a read direct transfer. The write direct transfer is a direct transfer in which write data from the host computer 1 is transferred to the cache area 244 (CS area) without involving the buffer area 242 (BS area). The read direct transfer is a direct transfer in which read data in the cache area 244 (CS area) is transferred to the host computer 1 without involving the buffer area 242 (BS area) to correspond to the claimed limitation].
Stoller teaches controls the first die to read the read target data from the first nonvolatile memory or the second die to read the read target data from the second nonvolatile memory when the read target data is not stored in the first volatile memory or the second volatile memory [(Paragraphs 0040-0043; Figs. 1 and 4) where Stoller teaches where Controller 105 may handle one or more functions of the memory by interacting with the memory cells of the memory device that are part of one or more memory dies 130-A-130N+1. A schematic of an example implementation of a memory die 130 is shown in FIG. 4. The controller 105 may communicate with these memory dies through the memory die interface 125 across a memory die bus 127. In some examples, the memory dies may have their own device controllers, including processing circuitry and processors, to control operations on the respective memory die. Such device controllers may be formed on a common die with the device storage array or may be on a separate die from that containing the device storage array. Both configurations are embraced by the identified “memory die” (130A-N+1) described herein. Memory dies may be NAND dies, three-dimensional NAND dies, phase change memory dies, and the like to correspond to the claimed limitation].
As per dependent claim 13, Morishita discloses wherein in response to a data write instruction from a host device, the controller writes write target data into the third volatile memory and then writes the write target data stored in the third volatile memory into the first volatile memory and the second volatile memory in parallel [(Paragraphs 0137-0147; FIGs. 13 and 14) wherein Morishita discloses in a write two-stage transfer, the FE-I/F #0 adds a guarantee code to write data from the host computer 1 and stores the write data to which the guarantee code has been added in the BS area #0 (a BS area reserved from the buffer area #0 for the two-stage transfer) (13-1). When parity ungenerated dirty data is stored in the write side 42a of the cache area #0, the CPU #0 verifies the guarantee code (13-2). Moreover, in the event that the write side 42a and the write side 42b are newly allocated during a reception of a write request, when parity ungenerated dirty data is not stored, the verification of the guarantee code of (13-2) is omitted. When a bit error has not occurred, the CPU #0 copies write data from the BS area #0 to the write side 42a of the cache area #0 (13-3) and further copies the write data to the write side 42b of the cache area #1 (13-4). The CPU #1 verifies the guarantee code of the write data stored in the write side 42b (13-5). If a bit error has not occurred, the CPU #1 reports write request completion to the host computer 1 via the CPU #0 and the FE-I/F #0 (13-6). On the other hand, as shown in FIG. 14, in a write direct transfer, the FE-I/F #0 adds a guarantee code to write data from the host computer 1 and stores the write data to which a guarantee code has been added in the write side 42a of the cache area #0 (14-1). When parity ungenerated dirty data is stored in the write side 42a, the CPU #0 verifies the guarantee code (14-2). Moreover, in a similar manner to a write two-stage transfer, in the event that the write side 42a and the write side 42b are newly allocated during a reception of a write request, when parity ungenerated dirty data is not stored, wherein the two-stage transfer of write data and copying data in buffer areas and caches in parallel of Morishita to correspond to the claimed limitation].
As per dependent claim 15, Morishita discloses wherein the data stored in the first volatile memory or the second volatile memory is written from the first volatile memory into the first nonvolatile memory or from the second volatile memory into the second nonvolatile memory during a period when the controller is not accessing the first die or the second die [(Paragraphs 0137-0147; FIGs. 13 and 14) wherein Morishita discloses in a write two-stage transfer, the FE-I/F #0 adds a guarantee code to write data from the host computer 1 and stores the write data to which the guarantee code has been added in the BS area #0 (a BS area reserved from the buffer area #0 for the two-stage transfer) (13-1). When parity ungenerated dirty data is stored in the write side 42a of the cache area #0, the CPU #0 verifies the guarantee code (13-2). Moreover, in the event that the write side 42a and the write side 42b are newly allocated during a reception of a write request, when parity ungenerated dirty data is not stored, the verification of the guarantee code of (13-2) is omitted. When a bit error has not occurred, the CPU #0 copies write data from the BS area #0 to the write side 42a of the cache area #0 (13-3) and further copies the write data to the write side 42b of the cache area #1 (13-4). The CPU #1 verifies the guarantee code of the write data stored in the write side 42b (13-5). If a bit error has not occurred, the CPU #1 reports write request completion to the host computer 1 via the CPU #0 and the FE-I/F #0 (13-6). On the other hand, as shown in FIG. 14, in a write direct transfer, the FE-I/F #0 adds a guarantee code to write data from the host computer 1 and stores the write data to which a guarantee code has been added in the write side 42a of the cache area #0 (14-1). When parity ungenerated dirty data is stored in the write side 42a, the CPU #0 verifies the guarantee code (14-2). Moreover, in a similar manner to a write two-stage transfer, in the event that the write side 42a and the write side 42b are newly allocated during a reception of a write request, when parity ungenerated dirty data is not stored, wherein the two-stage transfer of write data and copying data in buffer areas and caches in parallel of Morishita to correspond to the claimed limitation].
As per dependent claim 16, Stoller discloses wherein the first die and the second die each include a sense amplifier and a row decoder [(Paragraphs 0038-0042 and 0066-0069; Figs. 1 and 4) where Stoller teaches where FIG. 4 illustrates an example block diagram of a memory die 400 according to some examples of the present disclosure. Memory die 400 may be one example of memory die 130A-130N+1 of FIG. 1. Memory die 400 may include a memory array 402 having a plurality of memory cells 404, and one or more circuits or components to provide communication with, or perform one or more memory operations on, the memory array 402. The memory die 400 can include a row decoder 412, a column decoder 414, sense amplifiers 420, a page buffer 422, a selector 424, an input/output (I/O) circuit 426, and a dedicated memory controller, in the form of memory control unit 430, including processing circuitry, potentially including one or more processors, as described earlier herein to correspond to the claimed limitation].
As per dependent claim 17, Stoller discloses wherein the first volatile memory, the second volatile memory, and the third volatile memory are static random access memories (SRAMs) [(Paragraphs 0020, 0033 and 0074; Figs. 1 and 4) where Stoller teaches where Page buffers are allocated portions of Static Random Access Memory (SRAM) of the memory die that temporarily store data for doing operations such as program, erase, and read operations on the memory cells (e.g., NAND cells) of the memory die. The flash memory arrays can include a number of blocks of memory cells organized into a number of physical pages. In many examples, the SSDs will also include DRAM or SRAM (or other forms of memory die or other memory structures); Memory control unit 430 may utilize Random Access Memory (RAM) such as SRAM 431 to assist in performing operations to control the memory operations of the memory die 400. For example, the SRAM 431 may store one or more instructions, working values, and other calculations. The memory control unit 430 may execute software instruction sets, such as microcode which may reside on fully or partially on SRAM 431, within the memory control unit 430 (e.g., in dedicated registers, ROM, Flash, or other dedicated memory), within one or more memory cells (such as memory cells 404), or the like. SRAM 431 may store one or more page buffers that are used by the memory control unit 430 to temporarily store data being read from, or written to the memory cells (such as memory cells 404) to correspond to the claimed limitation].
As per dependent claim 18, Stoller discloses wherein the first nonvolatile memory and the second nonvolatile memory are NAND flash memories [(Paragraphs 0017, 0020, 0025 and 0043; Figs. 1 and 4) where Stoller teaches where Page buffers are allocated portions of Static Random Access Memory (SRAM) of the memory die that temporarily store data for doing operations such as program, erase, and read operations on the memory cells (e.g., NAND cells) of the memory die. The flash memory arrays can include a number of blocks of memory cells organized into a number of physical pages. In many examples, the SSDs will also include DRAM or SRAM (or other forms of memory die or other memory structures); Memory dies may be NAND dies, three-dimensional NAND dies, phase change memory dies, and the like to correspond to the claimed limitation].
As per dependent claim 19, Stoller discloses wherein the memory system comprises a plurality of dies including the first die and the second die, the plurality of dies are stacked [(Paragraphs 0030 and 0061-0062; Figs. 1 and 3) where Stoller teaches where multiple vertical structures can be stacked upon one another to form stacked arrays of storage cell strings to correspond to the claimed limitation], and the controller accesses each of the plurality of dies at different timings [(Paragraphs 0034 and 0080; Figs. 1 and 3) where Stoller teaches where Controller 105 may handle one or more functions of the memory by interacting with the memory cells of the memory device that are part of one or more memory dies 130-A-130N+1. A schematic of an example implementation of a memory die 130 is shown in FIG. 4. The controller 105 may communicate with these memory dies through the memory die interface 125 across a memory die bus 127. In some examples, the memory dies may have their own device controllers, including processing circuitry and processors, to control operations on the respective memory die. Such device controllers may be formed on a common die with the device storage array or may be on a separate die from that containing the device storage array; Operations 514 and 516 are repeated for each die that needs to be updated. In some examples, the controller may wait for a response indicating that the memory die has begun or is about to begin the software instruction set update before proceeding to the next memory die. In some examples, the controller may wait for a response indicating that the memory die has completed the update before moving onto the next die. In other examples, the controller may not wait until the memory die has completed the update before moving onto the next die in order to allow each die to update concurrently with each other—thereby improving parallelism of the software instruction set update to correspond to the claimed limitation].
As for independent claim 20, the applicant is directed to the rejections to claim 1 set forth above, as they are rejected based on the same rationale.
Claim 9 is rejected under 35 U.S.C. 103(a) as being disclosed by Stoller in view of Morishita, as applied to claim 1, and further in view of Kato et al. (US PGPUB 2015/0339198 hereinafter referred to as Kato).
As per dependent claim 9, Stoller/Morishita discloses the memory system according to claim 8.
Stoller/Morishita does not appear to explicitly disclose wherein the controller enables the data stored in the third volatile memory to be updated after writing data to be written into a predetermined memory area of the first nonvolatile memory from the third volatile memory to the first volatile memory and the second volatile memory.
However, Kato discloses wherein the controller enables the data stored in the third volatile memory to be updated after writing data to be written into a predetermined memory area of the first nonvolatile memory from the third volatile memory to the first volatile memory and the second volatile memory [(Paragraphs 0010-0012 and 0027-0029; FIGs. 1-3) where the nonvolatile semiconductor memory, a backup section, a first generator, a second generator, a writer, and a restoration section. The backup section writes backup data to the nonvolatile semiconductor memory. The backup data corresponds to management data which associates identification data of data written to the nonvolatile semiconductor memory with a write position of the data. The first generator generates update data indicating an updating state when the management data is updated after the backup data is written to the nonvolatile semiconductor memory. The second generator generates update accumulated data including the update data and past update data which has been generated before the update data and written to the nonvolatile semiconductor memory. The writer writes the update accumulated data to the nonvolatile semiconductor memory. The restoration section restores the management data based on the backup data read from the nonvolatile semiconductor memory and the update accumulated data to correspond to the claimed limitation].
Stoller/Morishita and Kato are analogous art because they are from the same field of endeavor of data storage management.
Before the effective filing date of the claimed inventions, it would have been obvious to one of ordinary skill in the art, having the teachings of Stoller/Morishita and Kato before him or her, to modify the method of Stoller/Morishita to include the update of data after writing of Kato because it will enhance data access.
The motivation for doing so would be [“to prevent the nonvolatile semiconductor memory 2 from being exhausted due to highly-frequent repetition of the writing backup table 7 to the nonvolatile semiconductor memory 2, the memory controller 4 writes the backup table 7 to the nonvolatile semiconductor memory 2 on condition that a write event of the backup table 7 occurs” (Paragraph 0023 by Kato)].
Therefore, it would have been obvious to combine Stoller/Morishita and Kato to obtain the invention as specified in the instant claim.
Claim 14 is rejected under 35 U.S.C. 103(a) as being disclosed by Stoller in view of Morishita, as applied to claim 1, and further in view of Cassuto et al. (US PGPUB 2021/0349828 hereinafter referred to as Cassuto).
As per dependent claim 14, Stoller/Morishita discloses the memory system according to claim 8.
Stoller/Morishita does not appear to explicitly disclose wherein the controller evicts the write target data stored in the first volatile memory or the second volatile memory and whose access frequency does not meet a predetermined criterion from the first volatile memory to the first nonvolatile memory or from the second volatile memory to the second nonvolatile memory.
However, Cassuto discloses wherein the controller evicts the write target data stored in the first volatile memory or the second volatile memory and whose access frequency does not meet a predetermined criterion from the first volatile memory to the first nonvolatile memory or from the second volatile memory to the second nonvolatile memory [(Paragraphs 0053-0057; FIGs. 1-3) where the cache module 36 may determine that an access threshold, such as a write frequency and/or a read frequency, for a particular page that has modifications stored in the cache has fallen below a threshold access frequency. In such implementations, cache module 36 may then flush the modifications for less frequently read and/or less frequently written pages from the cache to make room for caching modifications for more frequently read and/or more frequently written pages. Caching data for more frequently read and/or more frequently written pages may provide a performance benefit in some implementations, since it may be quicker to access such data from the cache than from the non-volatile storage to correspond to the claimed limitation].
Stoller/Morishita and Cassuto are analogous art because they are from the same field of endeavor of data storage management.
Before the effective filing date of the claimed inventions, it would have been obvious to one of ordinary skill in the art, having the teachings of Stoller/Morishita and Cassuto before him or her, to modify the method of Stoller/Morishita to include the update of data after writing of Cassuto because it will enhance data access.
The motivation for doing so would be [“provide a more efficient way of modifying pages in a non-volatile storage can improve the use of processing and memory resources, and prolong the usable life of certain types of storage media”” (Paragraph 0002 by Cassuto)].
Therefore, it would have been obvious to combine Stoller/Morishita and Cassuto to obtain the invention as specified in the instant claim.
a(2) CLAIMS ALLOWED IN THE APPLICATION
Per the instant office action, claims 1-6, 8, 9 and 11-20 are rejected, claims 7 and 10 are objected to but would be allowable if rewritten in an independent form and address all 112 rejections.
The reasons for allowance of claim 7 is that the prior art of record, neither anticipates, nor renders obvious the recited combination as a whole; including the limitations of “wherein after writing the data stored in the third volatile memory, which is to be written into the first nonvolatile memory, to the first volatile memory and the second volatile memory, the controller enables the data stored in the third volatile memory to be updated before status information indicating whether or not writing of the data from the first volatile memory to the first nonvolatile memory has completed, indicates completion of writing, and even if the status information indicates a failure of writing”.
The reasons for allowance of claim 10 is that the prior art of record, neither anticipates, nor renders obvious the recited combination as a whole; including the limitations of “wherein after writing first data stored in the first volatile memory into the predetermined memory area of the first nonvolatile memory a first time, the first die performs an operation of writing other data stored in the first volatile memory after the first volatile memory is updated to store the other data, to a memory area other than a predetermined memory area of the first nonvolatile memory multiple times, and then after the first volatile memory is updated to store the first data, writes the first data stored in the first volatile memory again into the predetermined memory area of the first nonvolatile memory”.
Pertinent Prior art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Chang et al., US PGPUB 2013/0326125– teaches FLASH MEMORY APPARATUS AND DATA ACCESS METHOD FOR FLASH MEMORY WITH REDUCED DATA ACCESS TIME.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jared Ian Rutz whose telephone number is (571)272-5535. The examiner can normally be reached on Monday-Friday, 8:00 AM to 4:00 PM.
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/MOHAMED M GEBRIL/Primary Examiner, Art Unit 2135