Prosecution Insights
Last updated: April 19, 2026
Application No. 18/589,365

EARPIECES WITH CAPACITIVE TOUCH INTERFACES

Non-Final OA §102§103
Filed
Feb 27, 2024
Examiner
KIM, PAUL
Art Unit
2695
Tech Center
2600 — Communications
Assignee
BOSE CORPORATION
OA Round
1 (Non-Final)
73%
Grant Probability
Favorable
1-2
OA Rounds
3y 5m
To Grant
93%
With Interview

Examiner Intelligence

Grants 73% — above average
73%
Career Allow Rate
797 granted / 1089 resolved
+11.2% vs TC avg
Strong +20% interview lift
Without
With
+19.8%
Interview Lift
resolved cases with interview
Typical timeline
3y 5m
Avg Prosecution
25 currently pending
Career history
1114
Total Applications
across all art units

Statute-Specific Performance

§101
16.4%
-23.6% vs TC avg
§103
47.2%
+7.2% vs TC avg
§102
20.8%
-19.2% vs TC avg
§112
9.1%
-30.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1089 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-7, 9-10, and 13-15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Harjee et al. (US Pub. 20220417641). Regarding claim 1, Harjee discloses an earpiece (see fig. 1B, item 101) comprising: a primary capacitive sensor (see fig. 1A, item 130; paragraphs 49 and 89; “both the touch sensor 130 and the force sensor 131 may be capacitance sensors”); and a secondary capacitive sensor (see fig. 1A, item 131; paragraphs 49 and 89; ; “both the touch sensor 130 and the force sensor 131 may be capacitance sensors”) arranged substantially orthogonally to the primary capacitive sensor (see paragraph 45; “The sides where touch and force are detected may be opposite and substantially orthogonal with respect to each other”); and a controller configured to receive input from the primary capacitive sensor to control one or more functions of the earpiece (see fig. 1A, item 132; paragraph 49), wherein the controller is further configured to receive input from the secondary capacitive sensor to detect if there is an interfering contact with the earpiece, and, if so, reject input from the capacitive touch interface (see paragraphs 60-61 and 63). Regarding claim 2, Harjee discloses the earpiece of claim 1, as discussed above, wherein the earpiece comprises a housing (see fig. 1B), and wherein the primary capacitive sensor comprises one or more primary capacitive sensor electrodes disposed on an inner surface of the housing (see fig. 2B; item 130). Regarding claim 3, Harjee discloses the earpiece of claim 2, as discussed above, wherein the earpiece further comprises a printed circuit board disposed within the housing (see fig. 2B, item 108), and wherein the secondary capacitive sensor comprises one or more secondary capacitive sensor electrodes disposed on a surface of the printed circuit board (see fig. 2B; item 131). Regarding claim 4, Harjee discloses the earpiece of claim 3, as discussed above, wherein the printed circuit board comprises a top surface arranged substantially parallel to the one or more primary capacitive sensor electrodes; a second surface, opposite the first surface; and an edge surface that extends between the top and bottom surfaces, and wherein the one or more secondary capacitive sensor electrodes are disposed on the edge surface (see fig. 2B, items 108, 130 and 131). Regarding claim 5, Harjee discloses the earpiece of claim 4, as discussed above, further comprising one or more spring contacts mounted on the top surface of the printed circuit board, wherein the one or more spring contacts provide an electrical connection between the one or more primary capacitive sensor electrodes and the printed circuit board (see fig. 2B, item 109; paragraphs 73-75 and 77). Regarding claim 6, Harjee discloses the earpiece of claim 5, as discussed above, wherein the controller is mounted on the top surface or the bottom surface of the printed circuit board (see fig. 2B). Regarding claim 7, Harjee discloses the earpiece of claim 6, as discussed above, wherein the controller is electrically connected to the one or more spring contacts via one or more electrically conductive traces of the printed circuit board (see paragraphs 86 and 90). Regarding claim 9, Harjee discloses the earpiece of claim 2, as discussed above, wherein the housing comprises: a first housing portion that at least partially defines an acoustic module that houses an electro-acoustic transducer; a second housing portion that at least partially defines an electronics module that houses electronics for driving the electro-acoustic transducer, and a third housing portion, wherein the one or more primary capacitive sensor electrodes are disposed on the third housing portion (see fig. 1B, items 101, 102 and 103; paragraphs 42, 52 and 67-68). Regarding claim 10, Harjee discloses the earpiece of claim 9, as discussed above, wherein the secondary capacitive sensor comprises one or more secondary capacitive sensor electrodes disposed on a surface of the second housing portion (see fig. 2B, item 131). Regarding claim 13, Harjee discloses an earpiece, comprising: a housing (see fig. 1B) containing: an electro-acoustic transducer (see fig. 1B, item 102; paragraph 52); and electronics for controlling operation of the earpiece (see paragraph 49), the electronics comprising: a printed circuit board (see sig. 2A, item 108; paragraph 86), a primary capacitive sensor comprising one or more primary capacitive sensor electrodes (see paragraph 87; touch electrodes) disposed on an inner surface of the housing (see fig. 1A, item 130; paragraphs 49, 87 and 89; “both the touch sensor 130 and the force sensor 131 may be capacitance sensors”), a secondary capacitive sensor comprising one or more secondary capacitive sensor electrodes (see paragraph 88; force electrodes) disposed on a surface of the printed circuit board (see fig. 1A, item 131; paragraphs 49, 88 and 89; “both the touch sensor 130 and the force sensor 131 may be capacitance sensors”), and a controller configured to receive input from the primary capacitive sensor to control one or more functions of the earpiece (see fig. 1A, item 132; paragraph 49), wherein the controller is further configured to receive input from the secondary capacitive sensor to detect if there is an interfering contact with the earpiece, and, if so, reject input from the capacitive touch interface (see paragraphs 60-61 and 63). Regarding claim 14, Harjee discloses the earpiece of claim 13, as discussed above, wherein the housing defines an acoustic module which houses the electro-acoustic transducer, and an electronics module which houses the electronics (see fig. 1B, items 101 and 102; paragraphs 42 and 52). Regarding claim 15, Harjee discloses the earpiece of claim 13, as discussed above, further comprising one or more spring contacts mounted on a top surface of the printed circuit board, wherein the one or more spring contacts electrically connect the one or more primary capacitive sensor electrodes to the printed circuit board, wherein the one or more secondary capacitive sensor electrodes are disposed on an edge surface of the printed circuit board, the edge surface being arranged orthogonally to the top surface of the printed circuit board (see fig. 2B, items 108, 109, 130 and 131; paragraphs 45, 73-75 and 77). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 8, 11-12, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Harjee et al. Regarding claim 8, Harjee discloses the earpiece of claim 3, as discussed above. Harjee fails to explicitly disclose wherein the one or more secondary capacitive sensor electrodes are formed by plating the surface of the printed circuit board. However, examiner takes official notice wherein the one or more secondary capacitive sensor electrodes are formed by plating the surface of the printed circuit board would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains since it is a well known design procedure for the one or more secondary capacitive sensor electrodes to be formed by plating the surface of the printed circuit board. Regarding claim 11, Harjee discloses the earpiece of claim 10, as discussed above. Harjee fails to explicitly disclose wherein the one or more secondary capacitive sensor electrodes are formed on the surface of the second housing portion via laser direct structuring. However, examiner takes official notice wherein the one or more secondary capacitive sensor electrodes are formed on the surface of the second housing portion via laser direct structuring would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains since it is a well known design procedure for the one or more capacitive sensor electrodes to be formed on the surface of the second housing portion via laser direct structuring. Regarding claim 12, Harjee discloses the earpiece of claim 2, as discussed above. Harjee fails to explicitly disclose wherein the one or more primary capacitive sensor electrodes are formed on the inner surface of the housing via laser direct structuring. However, examiner takes official notice wherein the one or more primary capacitive sensor electrodes are formed on the inner surface of the housing via laser direct structuring would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains since it is a well known design procedure for the one or more capacitive sensor electrodes to be formed on the surface of the second housing portion via laser direct structuring. Regarding claim 16, Harjee discloses the earpiece of claim 15, as discussed above. Harjee fails to explicitly disclose wherein the one or more secondary capacitive sensor electrodes are formed by plating the edge surface of the printed circuit board. However, examiner takes official notice wherein the one or more secondary capacitive sensor electrodes are formed by plating the edge surface of the printed circuit board would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains since it is a well known design procedure for the one or more secondary capacitive sensor electrodes to be formed by plating the surface of the printed circuit board. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to PAUL KIM whose telephone number is (571)270-7697. The examiner can normally be reached 9 AM - 5 PM, PST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, VIVIAN CHIN can be reached at (571) 272-7848. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /PAUL KIM/Primary Examiner, Art Unit 2695
Read full office action

Prosecution Timeline

Feb 27, 2024
Application Filed
Mar 02, 2026
Non-Final Rejection — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
73%
Grant Probability
93%
With Interview (+19.8%)
3y 5m
Median Time to Grant
Low
PTA Risk
Based on 1089 resolved cases by this examiner. Grant probability derived from career allow rate.

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