Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Response to Amendment
3 The amendment filed on 12/17/2025 have been fully considered and are made of record.
a. Claims 1-2, 4, 6, 12 and 18 have been amended.
Response to Arguments
Applicant’s arguments filed on 12/17/2025have been considered but are moot because the new ground of rejection has been applied to amended limitations.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-18 are rejected under 35 U.S.C. 103 as being unpatentable over Kraz et al. (Pub NO, US 2003/0201778 A1; hereinafter Kraz) in view of Ramirez et al. (Pub NO. US 2015/0260759 A1; hereinafter Ramirez).
Regarding Claim 1, Kraz teaches a tamper detection circuit (detection circuit 9 in fig. 1 and Fig. below; See [0022]-[0026]) comprising:
a trace antenna (trace antenna 50/52/53 in fig. 1 and Fig. below; See [0024]);
an amplifier (amplifier 70 in Fig. 1 and Fig. below; See [0025]-[0026]) comprising an amplifier input terminal coupled to the trace antenna (input of 70 is coupled to antenna 50/52/53 in Fig. 1 and Fig. below); and
a comparator (comparator 78 in fig. 1 and Fig. below; See [0026]) comprising
a first comparator input terminal coupled to an output terminal of the amplifier (See non-inverting input of comparator 78 is coupled to output of amplifier 70 in Fig. 1 and Fig. below),
a second comparator input terminal coupled to a voltage reference source (See inverting input of comparator 78 is coupled to a voltage reference source 80 in Fig. 1 and Fig. below), and
a comparator output terminal configured to output a pulse signal based on voltage signals received at the first comparator input terminal and the voltage reference source (digital logic level is pulse; [034]).
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Kraz is silent about wherein the tamper detection circuit (i) is configured within a meter device and (ii) detects tampering of the meter device.
Ramirez teaches wherein the tamper detection circuit (i) is configured within a meter device (tamper detection circuit 18 is inside meter device 10 in fig. 1; See [0015]-[0021]) and (ii) detects tampering of the meter device (18 detects tampering of meter device 10 in Fig. 1; See [0015]-[0021]).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention was made to incorporate the tamper detection circuit of Kraz inside the meter device of Ramirez in order to detect tamper of the meter device (Ramirez; [0001]).
Regarding Claim 2, Kraz in view of Ramirez teaches the tamper detection circuit of claim 1. Kraz further teaches wherein the amplifier comprises an operational amplifier (See [0032]) configured to amplify trace voltage signals received from the trace antenna (voltage signal is amplified and traced from antenna; See [0032]).
Regarding Claim 3, Kraz in view of Ramirez teaches the tamper detection circuit of claim 1. Kraz further teaches wherein the comparator comprises an operational amplifier (it is inherent property of comparator having operational amplifier) configured to compare the voltage signals received at the first comparator input terminal to the voltage reference source (See [0034]).
Regarding Claim 4, Kraz teaches a meter device (device in Fig. 2 and Fig. below; See [0024]-[0028]) comprising:
a tamper detection circuit (ESD detection is tamper detection and circuit 9 in Fig. 2 and Fig. below; See [0024]-[0028]) comprising
a trace antenna (trace antenna 50/52/53 in Fig. 2 and Fig. below; See [0024]),
an amplifier (amplifier 70 in Fig. 2 and Fig. below; See [0025]), and
a comparator (comparator 78 in Fig. 2 and Fig. below; See [0026]),
wherein the tamper detection circuit (i) is configured to generate a pulse signal (See [0028]);
a memory device having executable instructions stored therein (See [0035]); and
a processor, in response to the executable instructions (See [0035]), configured to:
monitor the pulse signal from the tamper detection circuit (See [0035]);
determine a tampering event based on the pulse signal (See [0035]); and
generate an alarm condition based on the tampering event (visual indication LED is alarm; See [0035]).
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Kraz is silent about wherein the tamper detection circuit (ii) is configured within a meter device and (iii) detects tampering of the meter device.
Ramirez teaches wherein the tamper detection circuit (ii) is configured within a meter device (tamper detection circuit 18 is inside meter device 10 in fig. 1; See [0015]-[0021]) and (iii) detects tampering of the meter device (18 detects tampering of meter device 10 in Fig. 1; See [0015]-[0021]).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention was made to incorporate the tamper detection circuit of Kraz inside the meter device of Ramirez in order to detect tamper of the meter device (Ramirez; [0001]).
Regarding Claim 5, Kraz in view of Ramirez teaches the meter device of claim 4. Kraz further teaches wherein the amplifier comprises an amplifier input terminal coupled to the trace antenna (See non-inverting input of comparator 78 is coupled to trace antenna 50 in Fig. 1).
Regarding Claim 6, Kraz in view of Ramirez teaches the meter device of claim 4. Kraz further teaches wherein the comparator comprises
a first comparator input terminal coupled to an output terminal of the amplifier (See non-inverting input of comparator 78 is coupled to output of amplifier 70 in Fig. 1),
(ii) a second comparator input terminal coupled to a voltage reference source (See inverting input of comparator 78 is coupled to a voltage reference source 80 in Fig. 1), and
(iii) a comparator output terminal configured to output the pulse signal based on voltage signals received at the first comparator input terminal and the voltage reference source (digital logic level is pulse; [034]).
Regarding Claim 7, Kraz in view of Ramirez teaches the meter device of claim 4. Kraz further teaches wherein the processor, in response to the executable instructions, is further configured to analyze the pulse signal with respect to one or more criteria (analyze pulse based on comparator output and criterion is comparator compare with threshold; See [0034]-[0035]).
Regarding Claim 8, Kraz in view of Ramirez teaches the meter device of claim 7. Kraz further teaches wherein the one or more criteria comprises an interval between one or more pulses, a duration of the one or more pulses, or a frequency of the one or more pulses (See [0029], [0037]).
Regarding Claim 9, Kraz in view of Ramirez teaches the meter device of claim 8. Kraz further teaches wherein the processor, in response to the executable instructions, is further configured to distinguish a presence of one or more high voltage/frequency tamper events from one or more false detection events based on the one or more criteria (See [0029], [0041]-[0042]).
Regarding Claim 10, Kraz in view of Ramirez teaches the meter device of claim 4. Kraz further teaches wherein the tamper detection circuit is configured to generate the pulse signal based on a detection of environmental radiation by the tamper detection circuit (comparator 78 generates pulse based on antenna 50 and antenna detects radiation of environmental pulse in fig. 2; See [0030], [0039]).
Regarding Claim 11, Kraz in view of Ramirez teaches the meter device of claim 4. Kraz further teaches wherein the tampering event comprises a high voltage/frequency event (See [0037]).
Regarding Claim 12, Kraz teaches a method for detecting tampering of a meter device (method for device in Fig. 2 and Fig. below; See [0024]-[0028]), the method comprising:
monitoring a pulse signal from a tamper detection circuit (See [0035]),
wherein the tamper detection circuit (ESD detection is tamper detection and circuit 9 in Fig. 2 and Fig. below; See [0024]-[0028])
comprises a trace antenna (trace antenna 50/52/53 in Fig. 2 and Fig. below; See [0024]),
an amplifier (amplifier 70 in Fig. 2 and Fig. below; See [0025]), and
a comparator (comparator 78 in Fig. 2 and Fig. below; See [0026]),
determining a tampering event based on the pulse signal (See [0035]); and
generating an alarm condition based on the tampering event (visual indication LED is alarm; See [0035]).
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Kraz is silent about (ii) is configured within a meter device and (iii) detects tampering of the meter device.
Ramirez teaches wherein the tamper detection circuit (ii) is configured within a meter device (tamper detection circuit 18 is inside meter device 10 in fig. 1; See [0015]-[0021]) and (iii) detects tampering of the meter device (18 detects tampering of meter device 10 in Fig. 1; See [0015]-[0021]).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention was made to incorporate the tamper detection circuit of Kraz inside the meter device of Ramirez in order to detect tamper of the meter device (Ramirez; [0001]).
Regarding Claim 13, Kraz in view of Ramirez teaches the method of claim 12. Kraz further teaches wherein the pulse signal is generated based on a detection of environmental radiation by the tamper detection circuit (comparator 78 generates pulse based on antenna 50 and antenna detects radiation of environmental pulse in fig. 2; See [0030], [0039]).
Regarding Claim 14, Kraz in view of Ramirez teaches the method of claim 12. Kraz further teaches wherein the tampering event comprises a high voltage/frequency event (See [0037]).
Regarding Claim 15, Kraz in view of Ramirez teaches the method of claim 12. Kraz further teaches wherein determining the tampering event comprises monitoring the pulse signal based on one or more criteria comprising an interval between one or more pulses, a duration of the one or more pulses, or a frequency of the one or more pulses (See [0029], [0037]).
Regarding Claim 16, Kraz in view of Ramirez teaches the method of claim 12. Kraz further teaches wherein determining the tampering event comprises distinguishing a presence of one or more high voltage/frequency tamper events from one or more false detection events (See [0029], [0041]-[0042]).
Regarding Claim 17, Kraz in view of Ramirez teaches the method of claim 12. Kraz further teaches wherein generating the alarm condition further comprises:
identifying one or more characteristics associated with the tampering event (characteristics is continuous-wave signal; See [0033]); and
generating a data object comprising the one or more characteristics (steady DC voltage 110 is data object generated by continuous-wave signal; See [0033]).
Regarding Claim 18, Kraz in view of Ramirez teaches the method of claim 17. Kraz further teaches wherein the one or more characteristics comprise a device identifier of the meter device, a type of tampering, or a date/time of the tampering event (real-time indication is date/time of event; See [0006]).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ZANNATUL FERDOUS whose telephone number is (571)270-0399. The examiner can normally be reached Monday through Friday 8am to 5pm (PST).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Rodak Lee can be reached at 571-270-5628. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ZANNATUL FERDOUS/Examiner, Art Unit 2858
/LEE E RODAK/ Supervisory Patent Examiner, Art Unit 2858