DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention group I, claims 1-15 in the reply filed on 06/04/2026 is acknowledged.
Accordingly, claims 16-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the feature “wherein the at least two gates are at least two non-adjacent gates contacting the backside gate connector” of claim 4; “wherein the at least two gates are a combination of adjacent and non-adjacent gates contacting the backside gate connector” of claim 5; and “the second source/drain contact contacting the backside gate connector” of claim 8 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 6-8, 10-13 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claims 6 and 7, claims 6 and 7 recites the limitation " the at least one source/drain". There is insufficient antecedent basis for this limitation in the claim.
For the purpose of this Action, the above limitation of claims 6-7 will be interpreted and examined as --the at least one source/drain contact--
Regarding claim 8, claim 8 recites the limitation "the second source/drain contact". There is insufficient antecedent basis for this limitation in the claim. In addition, it is unclear the second source/drain contact refers to which element because the drawing does not show any source/drain contact contacting the backside gate connector 129.
Regarding claim 10, claim 10 recites the limitation "the backside power rail". There is insufficient antecedent basis for this limitation in the claim.
Regarding claim 11, claim 11 recites “the at least one source/drain”. There is insufficient antecedent basis for this limitation in the claim.
Claims depending from the rejected claims noted above are rejected at least on the same basis as the claim(s) from which the dependent claims depend.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Narasimha et al. (US Pub. 20250210519) in view of Alptekin et al. (US Pub. 20240070365).
Regarding claim 1, Narasimha et al. discloses in Fig. 6D, paragraph [0065] a semiconductor structure comprising:
a backside gate connector [567] in a backside layer contacting a bottom surface of at least two gates [530]; and
a single gate contact [675] directly contacts a top surface of one of the at least two gates [530], wherein the single gate contact [675] connects the one of the at least two gates [530] to a layer of front side interconnect wiring [670] above the at least two gates [530].
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Narasimha et al. fails to explicitly disclose
the backside layer comprises a backside metal layer.
However, metal is a known contact material and therefore it would have been obvious to select metal based on its suitability for use as the backside contact in the device of Narasimha et al. Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945).
For further support, Alptekin et al. is cited.
Alptekin et al. discloses in Fig. 13, paragraph [0069]
the backside layer [228 and 226] comprises a backside metal layer.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Alptekin et al. into the method of Narasimha et al. to include the backside layer comprises a backside metal layer. The ordinary artisan would have been motivated to modify Narasimha et al. in the above manner for the purpose of providing suitable material of the backside layer in which the gate contact is formed.
Regarding claims 2-3, Narasimha et al. discloses in Fig. 6D
wherein the at least two gates [530] are in a gate-all-around field-effect transistor.
wherein the at least two gates [530] are at least two adjacent gates contacting the backside gate connector [567].
Regarding claim 14, Narasimha et al. discloses in Fig. 6D, paragraph [0065] a semiconductor structure comprising:
a backside gate connector [567] contacting a bottom surface of at least two gates [530] in more than one semiconductor device, wherein the backside gate connector [567] is below and between the at least two gates [530] in the more than one semiconductor device; and
a gate contact [675] directly contacting a top surface of one of the at least two gates [530], wherein the gate contact [675] connects the one of the at least two gates to a layer of front side interconnect wiring [670] above the at least two gates.
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Narasimha et al. fails to explicitly disclose
wherein the backside gate connector is composed of a contact metal.
However, metal is a known contact material and therefore it would have been obvious to select metal based on its suitability for use as the backside gate connector in the device of Narasimha et al. Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945).
For further support, Alptekin et al. is cited.
Alptekin et al. discloses in Fig. 13, paragraph [0069]
the backside gate connector [228 and 226] is composed of a contact metal.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Alptekin et al. into the method of Narasimha et al. to include wherein the backside gate connector is composed of a contact metal. The ordinary artisan would have been motivated to modify Narasimha et al. in the above manner for the purpose of providing suitable material of the backside layer in which the gate contact is formed.
Regarding claim 15, Narasimha et al. discloses wherein the more than one semiconductor device are each selected from the group consisting of gate-all-around field-effect transistors (GAA FETs), finFETs, stacked FETs, complementary FETs (CFETs), complementary metal-oxide semiconductor (CMOS) devices, and planar FETs [GAA FETs].
Claims 1-2, 4, 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Yun et al. (US Pub. 20240395900) in view of Narasimha et al. (US Pub. 20250210519).
Regarding claim 1, Yun et al. discloses in Fig. 2, a semiconductor structure comprising:
a backside gate connector [BG1 and BG2 and backside metal line connected to BG1 and BG2] in a backside metal layer contacting a bottom surface of at least two gates [G2 and G5][paragraph [0040]].
Yun et al. fails to disclose
a single gate contact directly contacts a top surface of one of the at least two gates, wherein the single gate contact connects the one of the at least two gates to a layer of front side interconnect wiring above the at least two gates.
Narasimha et al. discloses in Fig. 6D
a single gate contact [675] directly contacts a top surface of one of the at least two gates [530], wherein the single gate contact [675] connects the one of the at least two gates [530] to a layer of front side interconnect wiring [670] above the at least two gates [530].
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It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Narasimha et al. into the method of Yun et al. to include a single gate contact directly contacts a top surface of one of the at least two gates, wherein the single gate contact connects the one of the at least two gates to a layer of front side interconnect wiring above the at least two gates. The ordinary artisan would have been motivated to modify Yun et al. in the above manner for the purpose of electrically coupled the one of the at least two gates with a frontside power/signal line to provide the turn-on and turn-off signals to the one of the at least two gates [paragraph [0066] of Narasimha et al.].
Regarding claims 2, 4, Yun et al. discloses in Fig. 2
wherein the at least two gates [G2 and G5] are in a gate-all-around field-effect transistor;
wherein the at least two gates [G2 and G5] are at least two non-adjacent gates contacting the backside gate connector [BG1 and BG2 and backside metal line connected to BG1 and BG2].
Regarding claim 14, Yun et al. discloses in Fig. 2, a semiconductor structure comprising:
a backside gate connector [BG1 and BG2 and backside metal line connected to BG1 and BG2] contacting a bottom surface of at least two gates [G2 and G5] in more than one semiconductor device, wherein the backside gate connector [BG1 and BG2 and backside metal line connected to BG1 and BG2] is composed of a contact metal and is below and between the at least two gates [530] in the more than one semiconductor device [paragraph [0009], [0338], [0040]].
Yun et al. fails to disclose
a gate contact directly contacting a top surface of one of the at least two gates, wherein the gate contact connects the one of the at least two gates to a layer of front side interconnect wiring above the at least two gates.
Narasimha et al. discloses in Fig. 6D
a gate contact [675] directly contacting a top surface of one of the at least two gates [530], wherein the gate contact [675] connects the one of the at least two gates [530] to a layer of front side interconnect wiring [670] above the at least two gates [530].
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It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Narasimha et al. into the method of Yun et al. to include a gate contact directly contacting a top surface of one of the at least two gates, wherein the gate contact connects the one of the at least two gates to a layer of front side interconnect wiring above the at least two gates. The ordinary artisan would have been motivated to modify Yun et al. in the above manner for the purpose of electrically coupled the one of the at least two gates with a frontside power/signal line to provide the turn-on and turn-off signals to the one of the at least two gates [paragraph [0066] of Narasimha et al.].
Regarding claim 15, Yun et al. discloses in Fig. 2 wherein the more than one semiconductor device are each selected from the group consisting of gate-all-around field-effect transistors (GAA FETs), finFETs, stacked FETs, complementary FETs (CFETs), complementary metal-oxide semiconductor (CMOS) devices, and planar FETs [GAA FETs].
Claims 3 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over Yun et al. (US Pub. 20240395900) in view of Narasimha et al. (US Pub. 20250210519) as applied to claim 1 above and further in view of Alptekin et al. (US Pub. 20240070365).
Regarding claims 3 and 5, Yun et al. fails to disclose
wherein the at least two gates are at least two adjacent gates contacting the backside gate connector;
wherein the at least two gates are a combination of adjacent and non-adjacent gates contacting the backside gate connector.
Narasimha et al. discloses in Fig. 6D
wherein the at least two gates [530] are at least two adjacent gates contacting the backside gate connector [567].
Alptekin et al. discloses in Fig. 13
wherein the at least two gates are at least two adjacent gates contacting the backside gate connector [228 and 226];
wherein the at least two gates are a combination of adjacent [left gate and middle gate] and non-adjacent gates [left gate and right gate] contacting the backside gate connector [228 and 226].
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Narasimha et al. and Alptekin et al. into the method of Yun et al. to include wherein the at least two gates are at least two adjacent gates contacting the backside gate connector; wherein the at least two gates are a combination of adjacent and non-adjacent gates contacting the backside gate connector. The ordinary artisan would have been motivated to modify Yun et al. in the above manner for the purpose of providing suitable position of the at least two gates connected to the backside gate connector so that a common gate input signal can be delivered to adjacent and non-adjacent gates.
Claims 6-7 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Yun et al. (US Pub. 20240395900) in view of Narasimha et al. (US Pub. 20250210519) as applied to claim 1 above and further in view of Chang et al. (US Pub. 20250203837).
Regarding claims 6-7, Yun et al. discloses in Fig. 2
at least one source/drain contact [CA4] residing between the at least two gates [G2 and G5];
the backside gate connector [BG1 and BG2 and backside metal line connected to BG1 and BG2] resides under the at least two gates [G2 and G5] and the at least one source/drain contact [CA4].
Yun et al. fails to disclose
wherein the at least one source/drain contact is connected to the front side interconnect wiring above the at least one source/drain contact.
Chang et al. discloses in Fig. 2, paragraph [0021]-[0022]
wherein the at least one source/drain contact [MD] is connected to the front side interconnect wiring [M0] above the at least one source/drain contact [MD].
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Chang et al. into the method of Yun et al. to include wherein the at least one source/drain contact is connected to the front side interconnect wiring above the at least one source/drain contact. The ordinary artisan would have been motivated to modify Yun et al. in the above manner for the purpose of forming a frontside multilayer interconnect structure (FMLI) so that the various devices and/or components can operate as specified by design requirements [paragraph [0020]-[0022] of Chang et al.]. Further, it would have been obvious to try one of the known methods with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Regarding claim 9, Yun et al. discloses in Fig. 2, paragraph [0039]
wherein the backside gate connector [BG1 and BG2 and backside metal line connected to BG1 and BG2] resides with sidewalls surrounded by one or more dielectric materials [106].
Yun et al. fails to disclose
the backside gate connector resides on a backside interlayer dielectric.
Chang et al. discloses in Fig. 2, paragraph [0023]
the backside gate connector [BV0] resides on a backside interlayer dielectric [66’] with sidewalls surrounded by one or more dielectric materials [60].
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Chang et al. into the method of Yun et al. to include the backside gate connector resides on a backside interlayer dielectric. The ordinary artisan would have been motivated to modify Yun et al. in the above manner for the purpose of forming a backside multilayer interconnect structure (FMLI) so that the various devices and/or components can operate as specified by design requirements [paragraph [0020]-[0021], [0023] of Chang et al.].
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The cited art discloses similar materials, devices and methods.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SOPHIA T NGUYEN whose telephone number is (571)272-1686. The examiner can normally be reached 9:00am -5:00 pm, Monday-Friday.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, BRITT D HANLEY can be reached at (571)270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SOPHIA T NGUYEN/Primary Examiner, Art Unit 2893
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