CTNF 18/589,819 CTNF 98266 Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 102 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15 AIA Claim (s) 1, 3, 6-11, 13 and 16-20 are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by Chang (US 20210398907 A1) . Regarding Claim 1, Chang teaches a package (500, see Fig. 5(a)) comprising: a first substrate (401); a first integrated device (534) coupled to the first substrate (shown Fig. 5(a)); a second substrate (511); a second integrated device (528c) coupled to the second substrate; and an encapsulation layer (513) coupled to the first substrate and the second substrate (see also [0044], [0047] and Fig. 7(a) which teaches the encapsulant including a “molding compound and filler” and filling every space between interposer 404 and first substrate 401)), wherein the encapsulation layer, the first integrated device and the second integrated device are located between the first substrate and the second substrate (shown Fig. 5(a)). Regarding Claim 3, Chang teaches the package of claim 1, wherein the first integrated device is coupled to the second integrated device through a plurality of solder interconnects (see [0053] and Fig. 5(a) wherein the first integrated device is electrically coupled to the first substrate and the interposers 403 and 404 and further electrically coupled to the second substrate and second integrated device, wherein a plurality of pads, electrical connectors and solder bumps are implemented). Regarding Claim 6, Chang teaches the package of claim 3, wherein an electrical path between the first integrated device and the second integrated device comprises the plurality of solder interconnects between the first integrated device and the second integrated device. Regarding Claim 7, Chang teaches the package of claim 1, further comprising a plurality of solder interconnects, wherein the first substrate is configured to be electrically coupled to the second substrate through the plurality of solder interconnects (see [0053] and Fig. 5(a) wherein the first integrated device is electrically coupled to the first substrate and the interposers 403 and 404 and further electrically coupled to the second substrate and second integrated device, wherein a plurality of pads, electrical connectors and solder bumps are implemented). Regarding Claim 8, Chang teaches the package of claim 1, wherein the first substrate comprises a first surface (401b) and a second surface (401a), wherein the second substrate comprises a first surface (511b) and a second surface (511a), wherein the first integrated device is coupled to the second surface of the first substrate (shown Fig. 5(a)), and wherein the second integrated device is coupled to the first surface of the first substrate (electrically coupled to external connections on surface 401b, see also [0038] and Figs. 4, 5(a) wherein the interposers 403 and 404 establish an electrical connection). Regarding Claim 9, Chang teaches the package of claim 8, further comprising a third integrated device (528a) coupled to the second surface of the second substrate (shown Fig. 5(a)). Regarding Claim 10, Chang teaches the package of claim 9, further comprising a second encapsulation layer (upper portion of 513) coupled to the second surface of the second substrate (shown Fig. 5(a)), wherein the second encapsulation layer at least partially encapsulates the third integrated device (shown Fig. 5(a)). Regarding Claim 11, Chang teaches a method for fabricating a package (see Fig. 5(a)), comprising: providing a first substrate (401); coupling a first integrated device (534) to the first substrate; providing a second substrate (511); coupling a second integrated device (528c) to the second substrate; and forming an encapsulation layer (513) coupled to the first substrate and the second substrate (see also [0044], [0047] and Fig. 7(a) which teaches the encapsulant including a “molding compound and filler” and filling every space between interposer 404 and first substrate 401)), wherein the encapsulation layer, the first integrated device and the second integrated device are located between the first substrate and the second substrate (shown Fig. 5(a)). Regarding Claim 13, Chang teaches the method of claim 11, wherein the first integrated device is coupled to the second integrated device through a plurality of solder interconnects (see [0053] and Fig. 5(a) wherein the first integrated device is electrically coupled to the first substrate and the interposers 403 and 404 and further electrically coupled to the second substrate and second integrated device, wherein a plurality of pads, electrical connectors and solder bumps are implemented). Regarding Claim 16, Chang teaches the method of claim 13, wherein an electrical path between the first integrated device and the second integrated device comprises the plurality of solder interconnects between the first integrated device and the second integrated device. Regarding Claim 17, Chang teaches the method of claim 11, further coupling a plurality of solder interconnects, wherein the first substrate is configured to be electrically coupled to the second substrate through the plurality of solder interconnects (see [0053] and Fig. 5(a) wherein the first integrated device is electrically coupled to the first substrate and the interposers 403 and 404 and further electrically coupled to the second substrate and second integrated device, wherein a plurality of pads, electrical connectors and solder bumps are implemented). Regarding Claim 18, Chang teaches the method of claim 11, wherein the first substrate comprises a first surface (401b) and a second surface (401a), wherein the second substrate comprises a first surface (511b) and a second surface (511a), wherein the first integrated device is coupled to the second surface of the first substrate (shown Fig. 5(a)), and wherein the second integrated device is coupled to the first surface of the first substrate (electrically coupled to external connections on surface 401b, see also [0038] and Figs. 4, 5(a) wherein the interposers 403 and 404 establish an electrical connection). Regarding Claim 19, Chang teaches the method of claim 18, further comprising coupling a third integrated device (528a) coupled to the second surface of the second substrate (shown Fig. 5(a)). Regarding Claim 20, Chang teaches the method of claim 19, further comprising forming a second encapsulation layer (upper portion of 513) coupled to the second surface of the second substrate (shown Fig. 5(a)), wherein the second encapsulation layer at least partially encapsulates the third integrated device (shown Fig. 5(a)) . 07-15 AIA Claim (s) 1-3 and 6-8 and 11-13 and 16-18 are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by Sankman (US 20200357721 A1) . Regarding Claims 1 and 11, Sankman teaches a method of forming a package (see Fig. 1) comprising: providing a first substrate (106); coupling a first integrated device (104a) to the first substrate; providing a second substrate (116); coupling a second integrated device (114a) to the second substrate; and forming an encapsulation layer (see [0032] describing an encapsulant between the first substrate and second substrate) that is coupled to the first substrate and the second substrate (see [0032]), wherein the encapsulation layer, the first integrated device and the second integrated device are located between the first substrate and the second substrate (as described in [0032]). The package of claim 1 is taught as a result of the method of claim 11. Regarding Claims 2 and 12 , Sankman teaches the package of claim 1 and method of claim 11 respectively, further comprising an adhesive (107 and 117, see also [0030]) coupled to the first integrated device and the second integrated device and wherein the adhesive is located between the first integrated device and the second integrated device (shown Sankman: Fig. 1). Regarding Claims 3 and 13 , Sankman teaches the package of claim 1 and method of claim 11, wherein the first integrated device is coupled to the second integrated device through a plurality of solder interconnects (108, 118, 122 and 130, see also [0022]). Regarding Claims 6 and 16 , Sankman teaches the package of claim 3 and method of claim 13, wherein an electrical path (see [0022] and [0024] wherein dies 104 and 114 communicate through circuit board 140, which therefore establishes an electrical path) between the first integrated device and the second integrated device comprises the plurality of solder interconnects between the first integrated device and the second integrated device. Regarding Claims 7 and 17 , Sankman teaches the package of claim 1 and method of claim 11, further comprising a plurality of solder interconnects, wherein the first substrate is configured to be electrically coupled to the second substrate through the plurality of solder interconnects (see [0022] and [0024] wherein dies 104 and 114 communicate through circuit board 140, which therefore establishes an electrical coupling). Regarding Claims 8 and 18 , Sankman teaches the package of claim 1 and method of claim 11, wherein the first substrate comprises a first surface (bottom surface) and a second surface (upper surface), wherein the second substrate comprises a first surface (bottom surface) and a second surface (upper surface), wherein the first integrated device is coupled to the second surface of the first substrate (coupled through interconnects 108), and wherein the second integrated device is coupled to the first surface of the first substrate (electrically coupled through interconnects 108, 118, 122 and 130, see also [0022] and [0024] wherein dies 104 and 114 communicate through circuit board 140, which therefore establishes an electrical coupling to the first surface of the first substrate) . Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-23-aia AIA The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. 07-21-aia AIA Claim (s) ) 4-5 and 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Chang (US 20210398907 A1) in further view of Pietambaram (US 20230197697 A1) . Regarding Claims 4-5 and 14-15, Chang teaches the package of claim 3 and method of claim 13, but does not explicitly teach wherein the first integrated device or second integrated device comprises a plurality of through substrate vias. Pietambaram teaches a package (see Figs. 1A and 5D) comprising a first integrated device (114-2) and a second integrated device ( 114-3) electrically coupled to each other, wherein the first integrated device is a double-sided die comprising through silicon vias (TSVs) to form connections on both surfaces (see [0030]). It would be obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to modify the first integrated device and second integrated device of Chang to further comprise through substrate vias as suggested by Pietambaram as this would enable connections to be formed on either surface of the die, “reduce routing congestion” and “improve utilization of the dies by enabling a die in a non-adjacent layer to be connected to a package substrate” (see [0030]) . Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure : Tsai (US 20230105359 A1) teaches a package comprising a first substrate (208), a second substrate (238), a ring-shaped device (100) comprising a via (108), coupled to the second substrate (shown Fig. 18), an integrated device (224) coupled to the first substrate (shown Fig. 18) and an encapsulant (232) covering the ring-shaped device and integrated device between the first and second substrate and further comprising a plurality of die on an upper surface of the second substrate (see layer 304) which may further comprise an encapsulant (see [0054]). Any inquiry concerning this communication or earlier communications from the examiner should be directed to CASEY PAUL BOATMAN whose telephone number is (703)756-4778. The examiner can normally be reached M-F 7:30 AM - 5:30 PM ET. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached at (571)270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /C.P.B./ Examiner, Art Unit 2893 /Britt Hanley/ Supervisory Patent Examiner, Art Unit 2893 Application/Control Number: 18/589,819 Page 2 Art Unit: 2893 Application/Control Number: 18/589,819 Page 3 Art Unit: 2893 Application/Control Number: 18/589,819 Page 4 Art Unit: 2893 Application/Control Number: 18/589,819 Page 5 Art Unit: 2893 Application/Control Number: 18/589,819 Page 6 Art Unit: 2893 Application/Control Number: 18/589,819 Page 7 Art Unit: 2893 Application/Control Number: 18/589,819 Page 8 Art Unit: 2893 Application/Control Number: 18/589,819 Page 9 Art Unit: 2893 Application/Control Number: 18/589,819 Page 10 Art Unit: 2893 Application/Control Number: 18/589,819 Page 11 Art Unit: 2893
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