Prosecution Insights
Last updated: October 04, 2026
Application No. 18/589,885

OPTOELECTRONIC SEMICONDUCTOR CHIP

Non-Final OA §103
Filed
Feb 28, 2024
Priority
Mar 15, 2018 — DE 102018106001.7 +5 more
Examiner
YEUNG LOPEZ, FEIFEI
Art Unit
2899
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Osram GmbH
OA Round
2 (Non-Final)
81%
Grant Probability
Favorable
2-3
OA Rounds
0m
Est. Remaining
79%
With Interview

Examiner Intelligence

Grants 81% — above average
81%
Career Allowance Rate
884 granted / 1088 resolved
+13.3% vs TC avg
Minimal -3% lift
Without
With
+-2.7%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
34 currently pending
Career history
1123
Total Applications
across all art units

Statute-Specific Performance

§101
0.4%
-39.6% vs TC avg
§103
55.2%
+15.2% vs TC avg
§102
24.1%
-15.9% vs TC avg
§112
17.3%
-22.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1088 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim(s) 1-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shioji (PG Pub 2017/0331009 A1) and Kim et al (2016/0351754 A1). Regarding claim 1, Shioji teaches an optoelectronic semiconductor chip comprising: a semiconductor layer sequence (2, fig. 1B) having an active zone (22, paragraph [0028]) for generating radiation with a wavelength of maximum intensity L (inherent); and a mirror (4, paragraph [0038]) for the radiation on a rear side opposite a light extraction side (paragraph [0067]), several intermediate layers (Bragg reflector 4, paragraphs [0038]; dielectric layers, paragraph [0113]) in a direction away from the semiconductor layer sequence, the intermediate layers have alternately high and low refractive indices (paragraph [0113]) for the radiation and are each made of a material transparent to the radiation (since 4 is a Bragg reflector, the layers forming it have to be transparent to the radiation to be reflected), the intermediate layers are followed in the direction away from the semiconductor layer sequence by at least one metal layer (6, paragraphs [0080][0060]); and the metal layer extends through the intermediate layers towards the semiconductor layer sequence (fig. 1B). Shioji does not teach a cover layer. In the same field of endeavor, Kim teaches a cover layer (160, fig. 1), the cover layer is formed with a material transparent to the radiation (implied in the teaching that the radiation has to pass through 41 to reach reflector 43 to be reflected) and has an optical thickness of at least 0.5 L inclusive (400 nm thick, paragraph [0070], for light with wavelength of 554 nm, paragraphs [0077]), the cover layer is followed by intermediate layers (170), for the benefit of improving reflectivity (paragraphs [0004][0054] and fig. 4). Thus, it would have been obvious to the skilled in the art before the effective filing date of the invention to include a cover layer, the cover layer was formed with a material transparent to the radiation and has an optical thickness of at least 0.5 L inclusive, for the benefit of improving reflectivity. Shioji in view of Kim teaches “the metal layer extends through the cover layer towards the semiconductor layer sequence” to provide electrical bias to the semiconductor sequence. Regarding claim 2, Shioji teaches the optoelectronic semiconductor chip according to claim 1, wherein the metal layer is configured to apply a current to the semiconductor layer sequence (fig. 1B). Regarding claim 3, Shioji teaches the optoelectronic semiconductor chip according to claim 1, wherein the metal layer (6 is on “p-side contact” 32, paragraphs [0036][0037], fig. 1B) is configured to apply a current to a p-doped side of the semiconductor sequence. Regarding claim 4, Shioji teaches the optoelectronic semiconductor chip according to claim 1, wherein the metal mirror layer comprises or consists of silver (61, fig. 1B, paragraph [0080]) or a silver alloy. Regarding claim 5, Shioji teaches the optoelectronic semiconductor chip according to claim 1, wherein the metal mirror layer comprises or consists of gold (62, fig. 1B, paragraph [0060]) or aluminum or a gold alloy or an aluminum alloy. Regarding claim 6, Shioji teaches the optoelectronic semiconductor chip according to claim 1, wherein between the cover layer and the semiconductor layer sequence a contact layer (32, fig. 1B) is arranged, wherein the metal mirror layer is directly contacting the contact layer. Regarding claim 7, Shioji teaches the optoelectronic semiconductor chip according to claim 6, wherein the contact layer comprises or consists of a transparent conductive oxide (paragraphs [0036][0037]). Regarding claim 8, Shioji teaches the optoelectronic semiconductor chip according to claim 6, wherein the contact layer comprises or consists of indium tin oxide (paragraphs [0036][0037]), indium zinc oxide or zinc oxide. Regarding claim 9, Shioji does not teach the optoelectronic semiconductor chip according to claim 6, wherein the intermediate layers, the cover layer and/or the contact layer are structured by means of a dry etch process. However, “structured by means of a dry etch process” is a manufacturing step in a device claim and does not carry patentable weight because it does not impart structural features distinct from those shown in the cited art. “[E]ven though product-by process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by process claim is the same as or obvious from a process of the prior art, the claim is unpatentable even though the prior product was made by a different process.” In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985). Regarding claim 10, Shioji teaches the optoelectronic semiconductor chip according to claim 6, wherein the contact layer is arranged directly at a p-doped side of the semiconductor layer sequence (“p-side contact” 32, paragraphs [0036][0037], fig. 1B). Regarding claim 11, Shioji teaches the optoelectronic semiconductor chip according to claim 1, wherein the metal layer directly contacts (6 contacts 32, fig. 1B) the semiconductor layer sequence (32 is part of the semiconductor sequence). Since the claims do not exclude any material in the semiconductor layer sequence, thus, layer 32 can be read as part of the semiconductor sequence. Regarding claim 12, Kim teaches the optoelectronic semiconductor chip according to claim 1, wherein the cover layer has a thickness of at most 5 L (1.5λ/n, paragraph [0060]). Regarding claim 13, Shioji teaches the optoelectronic semiconductor chip according to claim 1, wherein the metal layer is configured as a reflection layer for radiation generated in the active zone (paragraphs [0003][0026]). Regarding claim 14, Shioji teaches the optoelectronic semiconductor chip according to claim 1, wherein a thickness of at least one of the intermediate layers is unequal to L/4 (paragraph [0113]). Regarding claim 15, Kim teaches the optoelectronic semiconductor chip according to claim 1, wherein the cover layer has an optical thickness between 1.1 L and 1.6 L (1.5L when n is 1 in 1.5λ/n, paragraphs [0059][0060]), inclusive. Regarding claim 16, Kim teaches the optoelectronic semiconductor chip according to claim 1, wherein the cover layer is of SiO2 (paragraph [0059]) and/or the intermediate layers are alternately of Nb2O5 and SiO2. Regarding claim 17, Shioji in view of Kim (see claim 1) teaches an optoelectronic semiconductor chip comprising: a semiconductor layer sequence having an active zone for generating radiation with a wavelength of maximum intensity L; and a mirror for the radiation on a rear side opposite a light extraction side, wherein the mirror comprises at least one cover layer, the cover layer is formed with a material transparent to the radiation and has an optical thickness of at least 0.5 L inclusive, the cover layer is followed by several intermediate layers in a direction away from the semiconductor layer sequence, the intermediate layers have alternately high and low refractive indices for the radiation and are each made of a material transparent to the radiation, the intermediate layers are followed in the direction away from the semiconductor layer sequence by at least one metal layer as a reflection layer, the semiconductor chip comprises at least one through-connection extending (6 in via hole, fig. 1B of Shioji) from the metal layer (6 on top of 4 of Shioji) to the semiconductor layer sequence, the through-connection electrically connects the metal layer and the semiconductor layer sequence, and the through-connection and the metal layer are formed in one piece (fig. 1B of Shioji). Regarding claim 18, Shioji in view of Kim (see claim 1) teaches an optoelectronic semiconductor chip comprising: a semiconductor layer sequence having an active zone for generating radiation with a wavelength of maximum intensity L; and a mirror for the radiation on a rear side opposite a light extraction side, wherein the mirror comprises at least one cover layer, the cover layer is formed with a material transparent to the radiation and has an optical thickness of at least 0.5 L inclusive, the cover layer is followed by several intermediate layers in a direction away from the semiconductor layer sequence, the intermediate layers have alternately high and low refractive indices for the radiation and are each made of a material transparent to the radiation, the intermediate layers are followed in the direction away from the semiconductor layer sequence by at least one metal layer as a reflection layer, between the semiconductor layer sequence and the cover layer a contact layer (32, fig. 1B of Shioji) is arranged at direct contact with the semiconductor layer sequence, the contact layer is made of a transparent conductive oxide (paragraphs [0036][0037]), the semiconductor chip comprises at least one through-connection (6 in holes of 4) extending from the metal layer to the contact layer, the through-connection electrically connects the metal layer and the contact layer (fig. 1B), and the through-connection and the metal layer are formed in one piece (fig. 1B). Regarding claim 20, Shioji teaches the optoelectronic semiconductor chip according to claim 18, further comprising an adhesion promoting layer (61, fig. 1B, paragraph [0046]) arranged between the metal layer and the intermediate layers, wherein the through-connection is free of (61 is not part of through-connection 62, fig. 1B) the adhesion promoting layer. Response to Arguments Applicant's arguments filed July 8, 2026 regarding rejection under Shioji and Kim (2016/0351754 A1) have been fully considered but they are not persuasive. Applicant argues that, page 11, second paragraph Kim '754 teaches that the "reflector RS includes first and second Bragg layers 150 and 170 and a separation layer 106. The semiconductor light-emitting device 100 further includes first and second electrodes 130 and 140, and a metal layer 190 disposed below the reflector RS." See Kim '754, paragraph [0044]. The first and second Bragg layers 150 and 170 of Kim '754 are arranged on an opposite side of the substrate 101 of Kim '754 and separated from the semiconductor layer 122 of Kim '754. See Id., paragraph [0044]. Applicant submits that this clearly reveals that the problem addressed by the second Bragg layer 170 of Kim '754 only occurs because the first and second Bragg layers 150 and 170 of Kim '754 directly adjoin the substrate 101. This is because Kim '754 teaches a device where the first and second Bragg layers 150 and 170 and the semiconductor layer 122 forming the light emitting structure 100 are arranged on opposite sides of the substrate 101. See Id., FIG. 1. In Shioji, in contrast, DBR 4 is not in contact with the substrate anyway because material of the semiconductor layers 21, 22, 23 is arranged between the DBR 4 and the substrate 1. See Shioji, paragraphs [0038] and [0039]. Threfore, Applicant submits that one of ordinary skill in the art would not be motivated to combine Shioji with Kim '754, as proposed by the Office, because there would be no reason to use the second Bragg layer 170 as an interface layer of Kim '754 in the device of Shioji since they different arrangements that serve different purposes. Therefore, Applicant submits that the Office's proposed combination of Shioji and Kim '754 is based on impermissible hindsight in knowledge of the present invention, rather than on the actual technical teaching of the cited references. In response, Kim teaches reflector RS increases light extraction efficiency of the device (paragraph [0005]). Kim teaches reflector RS to be on the substrate because light is to be extracted through the top surface of layer 126. Thus, in Shioji’s device, the skilled in the art would have recognized to form RS, and cover layer 160, in place of reflector 4 to increase light extraction. Applicant does not present arguments explaining why forming Kim’s RS in Shioji’s device would cause a problem and would not reflect light. Applicant’s arguments, see pages 7 to 10, filed July 8, 2026, with respect to Kim et al (WO 2017/069372 A1, hereafter WIPO Kim) reference have been fully considered and are persuasive. The rejection of under WIPO Kim has been withdrawn. Allowable Subject Matter Claim 19 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: Prior art does not teach “wherein the adhesion promoting layer and the contact layer are made of the same materials” (claim 19). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to FEIFEI YEUNG LOPEZ whose telephone number is (571)270-1882. The examiner can normally be reached M-F: 8am to 4pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at 571 270 7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /FEIFEI YEUNG LOPEZ/Primary Examiner, Art Unit 2899
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Prosecution Timeline

Feb 28, 2024
Application Filed
Apr 16, 2026
Non-Final Rejection mailed — §103
Jul 08, 2026
Response Filed
Sep 09, 2026
Non-Final Rejection mailed — §103 (current)

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Prosecution Projections

2-3
Expected OA Rounds
81%
Grant Probability
79%
With Interview (-2.7%)
2y 5m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 1088 resolved cases by this examiner. Grant probability derived from career allowance rate.

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