DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This office action is in response to the amendment filed on 06/30/2026. Claims 1, 3-16, and 18-21 are pending. Claims 1 and 18 are amended. Claim 17 is canceled. Claim 21 is new.
Response to Arguments
Applicant’s arguments, see Remarks pages 6-7, filed 06/30/2026, with respect to the rejection(s) of claim(s) 1 under 35 USC 102 have been fully considered and are persuasive. Specifically, the amendment to claim 1, which now requires using the occupancy of the decode queue to determine the availability of instructions, overcomes the previous rejection and the arguments to that effect were found persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Chishti US 2025/0004781 and Grochowski US 6,115,807.
Applicant’s arguments on page 7-8 of the Remarks with respect to claim 21 have been fully considered and are persuasive. Specifically, the argument that Chishti does not disclose the execution circuitry choosing between executing instructions with speculation and without speculation was found to be persuasive. However, this feature raises new matter issues and a 112(a) rejection is presented below.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 21 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 21 recites “execution circuitry configured to choose between executing each of the instructions with speculation and without speculation” in lines 4-5, and further mentions this feature in lines 6-7 and lines 9-10. While the specification discloses that the execution circuitry executes instructions using speculation, see page 3 lines 6-7, and the availability of the instructions could be measured based on the availability of instructions to the execution circuitry, see page 3 lines 21-23, the specification does not describe that the execution circuitry itself chooses between executing instructions with speculation and without speculation. The specification discloses that the throttle circuitry throttles the extent to which speculation occurs, see page 3 lines 3-5, which indicates that the throttle circuitry chooses whether the execution circuitry will execution instructions with speculation or without speculation (i.e., with throttling).
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 18 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 18 recites “the instructions” in line 5, line 10, and line 11. It is unclear whether these refer to the instructions introduced in line 3 or line 4. For purposes of examination, these will be interpreted as referring to the instructions introduced in line 4.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-4, 9-13, 16, and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Chishti US 2025/0004781 in view of Grochowski US 6,115,807.
Regarding claim 1, Chishti teaches:
1. A data processing apparatus comprising:
decode circuitry configured to decode instructions from a decode queue configured to queue the instructions awaiting decoding by the decode circuitry ([0036]: decoder circuitry decodes instructions from storage 103, which functions as a decode queue to store/queue instructions awaiting decoding by the decode circuitry);
execution circuitry (Fig. 1 execution circuitry 109) configured to execute the instructions using speculation ([0034] describes Adaptive Speculation (ASL) logic that limits the amount of speculation and [0036] describes that the ASL may throttle execution, which indicates that the execution circuitry executes instructions using speculation); and
throttle circuitry configured to throttle an extent to which the speculation is performed (Fig. 1 ASL 150 limits/throttles speculation, see also [0034]), wherein
the throttle circuitry is configured to control throttling speculation based on an availability of the instructions ([0060]-[0062]: the ASL may throttle based on the number of allocated uops, which is an availability of instructions allocated in the pipeline to be speculatively executed by the execution circuitry, see also Fig. 4 showing the allocation stage before the execute stage).
Chishti does not teach determining the availability of the instructions according to an occupancy of the decode queue by the instructions.
However, Grochowski teaches determining an availability of instructions determined according to an occupancy of a decode queue by the instructions (col 4 lines 30-40: the circular instruction queue receives instructions, decodes them, and determines how many of the decoded instructions may issue, which is the number of instructions that are output in the next cycle, which indicates that the determination of the number of instructions that may issue is based on the occupancy of the queue by those instructions)
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the decoder of Chishti with the instruction queue of Grochowski such that the combination would determine the number of instructions to issue/allocate (i.e., an availability of the instructions) based on their occupancy of the instruction/decode queue. One of ordinary skill in the art would have been motivated to make this modification to simplify operation of the decoder in implementations that may use an instruction rotator (Grochowski col 8 lines 12-21).
Claim 18 is directed to a non-transitory computer-readable medium corresponding to the data processing apparatus of claim 1 and is rejected for the same reasons as claim 1.
Regarding claim 3, Chishti in view of Grochowski teaches:
3. The data processing apparatus according to claim 1, wherein the throttle circuitry is configured to throttle the speculation more aggressively when the availability of the instructions is above an availability threshold as compared to when the availability of the instructions is below the availability threshold (Chishti [0043] and [0062]: speculation is throttled if wastage (which is based on the allocated uops/availability of instructions) is above a wastage/availability threshold, compared to the wasted/availability being below the wastage/availability threshold).
Regarding claim 4, Chishti in view of Grochowski teaches:
4. The data processing apparatus according to claim 1, wherein the throttle circuitry is configured to throttle the speculation by selection of a speculation throttling policy (Chishti [0066]-[0067]: the ASL selects a configuration/speculation throttle policy).
Regarding claim 9, Chishti in view of Grochowski teaches:
9. The data processing apparatus according to claim 1, wherein the throttle circuitry is configured to throttle the extent to which the speculation is performed by stalling a single point of a pipeline comprising the execution circuitry (Chishti [0077]: the throttling may be performed in any stage up to the execute stage using inactive cycles (i.e., stalling), any stage that the throttling/stalling is performed in is a single point of the pipeline).
Regarding claim 10, Chishti in view of Grochowski teaches:
10. The data processing apparatus according to claim 9,
wherein the single point is a rename stage of the pipeline (Chishti [0077]: the throttling may be performed in the renaming stage).
Regarding claim 11, Chishti in view of Grochowski teaches:
11. The data processing apparatus according to claim 9,
wherein the single point is a branch prediction stage of the pipeline (Chishti [0073]-[0074]: the throttling may be performed during the branch prediction stage).
Regarding claim 12, Chishti in view of Grochowski teaches:
12. The data processing apparatus according to claim 1, wherein
the throttle circuitry is configured to throttle the extent to which the speculation is performed by stalling multiple points of a pipeline comprising the execution circuitry (Chishti [0074]: the throttling may be performed on the branch prediction stage and the later stages, which are multiple points of the pipeline).
Regarding claim 13, Chishti in view of Grochowski teaches:
13. The data processing apparatus according to claim 12, wherein the multiple points are between a branch prediction stage of the pipeline and a rename stage of the pipeline, inclusive (Chishti [0074]: the multiple stages/points that are throttled include the stages from the branch prediction stage to the rename stage, see also Fig. 4 and [0077])
Regarding claim 16, Chishti in view of Grochowski teaches:
16. The data processing apparatus of claim 1, wherein
the execution circuitry comprises a 6x128 bit vector datapath (Chishti [0101]: the execution unit circuitry width may be 16-bit to 1,024 bit, which includes a 768-bit (i.e., 6x128 bit) vector datapath).
Regarding claim 19, Chishti in view of Grochowski teaches:
19. A system comprising:
the data processing apparatus of claim 1, implemented in at least one packaged chip (Fig. 1 and Fig. 5 show the ASL in a processor core, which indicates that the apparatus is implemented in a processor which is a packaged chip);
at least one system component ([0119]: any one of the parallel processors, memory hub, and I/O hub is a system component); and
a board, wherein the at least one packaged chip and the at least one system component are assembled on the board ([0119]: a multi-chip module may include components of the computing system, which indicates that the processor and at least one of the system components are assembled in the multi-chip/board).
Regarding claim 20, Chishti in view of Grochowski teaches:
20. A chip-containing product comprising the system of claim 19, wherein the system is assembled on a further board with at least one other product component ([0119]: the multi-chip module may be connected with another multi-chip module (i.e., a further board) and any component on the other multi-chip module is another product component).
Claims 5-8 are rejected under 35 U.S.C. 103 as being unpatentable over Chishti US 2025/0004781 in view of Grochowski US 6,115,807 and Priyadarshi US 2017/0249149.
Regarding claim 5, Chishti in view of Grochowski teaches:
5. The data processing apparatus according to claim 4, wherein
the speculation throttling policy causes throttling based on an estimated probability that a current in-flight control flow instruction in the instructions has been mispredicted based on a current prediction success rate of control flow instructions in the instructions (Chishti [0050] and [0056]-[0057]: the throttling is based on the prediction accuracy, which is an estimated probability that a current in-flight branch has been mispredicted based on a current prediction success rate).
Chishti in view of Grochowski does not teach throttling based on an estimated probability that a current in-flight control flow instruction in the instructions has been mispredicted based on a number of in-flight control flow instructions in the instructions
However, Priyadarshi teaches throttling based on an estimated probability that a current in-flight control flow instruction in the instructions has been mispredicted based on a number of in-flight control flow instructions in the instructions ([0003]: a large number of in-flight branches indicates a higher likelihood that some of the branches were mispredicted and fetching is throttled based on the number of in-flight branches being too large).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Chishti in view of Grochowski to estimate the probability that a branch instruction has been mispredicted (and to throttle based on this estimation) based on the number of in-flight control flow instructions as taught by Priyadarshi. One of ordinary skill in the art would have been motivated to make this modification to improve the accuracy of the estimated probability of a branch being mispredicted since estimating the probability based on more information (i.e., the number of in-flight branches in addition to the accuracy/prediction success rate) would be yield better estimations.
Regarding claim 6, Chishti in view of Grochowski and Priyadarshi teaches:
6. The data processing apparatus according to claim 5, wherein
the current prediction success rate of control flow instructions in the instructions is the current prediction success rate of low-confidence control flow instructions in the instructions (Chishti [0050] and [0056]-[0057]: the accuracy/prediction success rate is for low confidence branches when it is below the accuracy threshold).
Regarding claim 7, Chishti in view of Grochowski and Priyadarshi teaches:
7. The data processing apparatus according to claim 6, wherein
the low confidence control flow instructions comprise control flow instructions having and unsaturated confidence metric is unsaturated (Chishti [0057]: the low confidence branches are branches that have an accuracy/confidence metric of less than the accuracy threshold, which is an unsaturated accuracy/confidence metric since accuracy would be saturated at 100%) that are predicted dynamically (Chishti Fig. 5 shows a branch predictor 532 and [0087]-[0088] describes that the processor performs branch prediction and may have a low level of certainty in that the prediction is correct, which indicates that branches/control flow instructions, including the low confidence branches, are predicted dynamically) and are predicted (Chishti Fig. 5 shows a branch predictor 532 and [0087]-[0088] describes that the processor performs branch prediction and may have a low level of certainty in that the prediction is correct, which indicates that the branches are conditional branches/control flow instructions since branch prediction is performed for conditional branches).
Regarding claim 8, Chishti in view of Grochowski and Priyadarshi teaches:
8. The data processing apparatus according to claim 5, wherein
the speculation throttling policy causes throttling to increase when a likelihood that the current in-flight control flow instruction in the instructions has been mispredicted is above a misprediction threshold (Chishti [0056]-[0057] and [0059]: a low confidence bit is set to indicate a low confidence branch when the misprediction count (i.e., a likelihood that the branch has been mispredicted) is above a misprediction threshold, see [0052]-[0055] and speculative execution may be throttled on detecting the low confidence branch, see [0059]).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Chishti US 2025/0004781 in view of Grochowski US 6,115,807 and Glew US 2007/0083739.
Regarding claim 14, Chishti in view of Grochowski teaches:
14. The data processing apparatus according to claim 1,
Chishti in view of Grochowski does not teach:
wherein the throttle circuitry is configured to throttle the speculation additionally based on a type of predictor used for the speculation being performed.
However, Glew teaches a branch predictor system that uses different types of predictors that each provide a prediction and a confidence level, see [0026]-[0028] and Fig. 1.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Chishti in view of Grochowski to use the branch prediction system of Glew. In this combination, Chishti would throttle based on the confidence level provided by each predictor, which would be based on the type of predictor used (as the predictors are of different types). One of ordinary skill in the art would have been motivated to make this modification to improve predictor performance (since different types of predictors would provide more accurate branch predictions) while controlling potential wasted power from wrong-path instructions from low-confidence predictors.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Chishti US 2025/0004781 in view of Grochowski US 6,115,807 and Gschwind US 2009/0150657.
Regarding claim 15, Chishti in view of Grochowski teaches:
15. The data processing apparatus according to claim 1,
Chishti in view of Grochowski does not teach:
control circuitry configured to selectively control the throttle circuitry to enter a static mode of operation in which the throttle circuitry is configured to control throttling the speculation regardless of the availability of the instructions.
However, Gschwind teaches:
control circuitry configured to selectively control the throttle circuitry to enter a static mode of operation in which the throttle circuitry is configured to control throttling the speculation regardless of the availability of the instructions (a fetch throttle controller inhibits/controls throttling when the confidence for a branch is less than a second threshold, see [0024]).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Chishti in view of Grochowski to include a throttle controller that inhibits throttling when confidence for a branch is less than a second threshold as taught by Gschwind. By inhibiting throttling, the throttle controller of the combination controls the throttle circuitry to enter a static mode in which throttling is inhibited (i.e., control throttling speculation) regardless of the availability of the instructions. One of ordinary skill in the art would have been motivated to make this modification to enhance processing efficiency by allowing for processing instructions at full-speed when a redirect is likely (Gschwind [0024]).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KASIM ALLI whose telephone number is (571)270-1476. The examiner can normally be reached Monday - Friday 9am 5pm.
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/KASIM ALLI/Examiner, Art Unit 2183
/ANDREW CALDWELL/Supervisory Patent Examiner, Art Unit 2182
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