Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments, with respect to Liu have been fully considered and are persuasive. The previous rejection has been withdrawn. Applicant's Remarks with respect to Liu have been fully considered but they are not persuasive.
The Remarks contend the limitations the circuitry that controls NFETs 92/93 receive power from the enable terminal are not found in Lam. In response, Applicant has not placed such a requirement in the claims. The claims in relevant part recites “circuitry having a power terminal coupled to the enable terminal”. This is contrasted by the Remarks which contend the claims require the control circuitry for the NFETs to receive power from the enable terminal. In Lam the enable terminal (236) is clearly shown connected to a power terminal (see power terminal inputting voltage level to MUX 3) in Fig. 3. In this case the features upon which applicant argument relies (i.e., receiving power from the enable terminal) are not recited in the rejected claims. Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
The Remarks further do not separately argue the rejections of claim 8 and 15. Instead the Remarks (at 8) contend claims 8 and 15 are allowable for at least the same reasons as claim 1.
In response, the claim limitations of claims 8 and 15 however do not recite the claim limitations of claim 1. In particular claim 1 recites “fault circuitry having an enable terminal and a fault terminal, the enable terminal coupled to the supply terminal, the fault terminal coupled to the enable terminal of the fuse circuitry, the fault circuitry including circuitry having a power terminal coupled to the enable terminal and an output coupled to the fault terminal” in contrast claim 8 fails to recite fault circuitry is not required to have a power terminal coupled to a the enable terminal. Therefore, the claims differ in scope.
The rejection is therefore proper and has been made FINAL.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 5-10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lam et al. (US 2020/0366183).
With respect to claims 1 and 7 Lam teaches an apparatus comprising: a supply terminal; fuse circuitry (see 92/93 having a first terminal (left side), a second terminal (right side), and an enable terminal (gate terminal), the first terminal of the fuse circuitry coupled to the supply terminal (Vin); fault circuitry (see control circuitry and logic elements in Fig. 3) having an enable terminal (236) and a fault terminal (Iset 238), the enable terminal coupled to the supply terminal (see connection shown in Fig. 3), the fault terminal coupled to the enable terminal of the fuse circuitry, the fault circuitry including circuitry having a power terminal (see power terminal inputting voltage level to MUX 3) coupled (see coupling at VIN and VIN_OV_REF) to the enable terminal and an output (263) coupled to the fault terminal (coupled via 291); and converter circuitry (see switching converter) having a terminal coupled to the second terminal of the fuse circuitry (see Vout terminal Fig. 3).
With respect to claim 8 Lam teaches an apparatus comprising: a supply terminal (Vin terminal Fig. 2 for example); fault detection circuitry (see for example 258) having a terminal; fault latch circuitry (see internal circuit elements in 257, comparators and logic elements) having a first terminal (236), a second terminal (see UV, OV terminal 264, 285 or HC terminal), and a third terminal (see for example override bit input, terminals form M3 and M5 with transistors or inputs for Mux 3 in Fig. 3 for programming the voltage levels), the first terminal of the fault latch circuitry being a power terminal (see 236 coupled to Vin) coupled to the supply terminal, the second terminal of the fault latch circuitry coupled to the terminal of the fault detection circuitry (see UV, OV and HC input to fault detecting OV,UV and HC inputs of 258); and a transistor (92/93) having a first terminal (left side) and a control terminal (gate terminal), the first terminal coupled to the supply terminal (see connection to Vin), the control terminal of the transistor (gate terminal) coupled to the third terminal (see Fig. 3) of the fault latch circuitry.
With respect to claim 9 Lam teaches fuse circuitry having a first terminal, a second terminal, and a control terminal (see terminals of 92 and 93), the first terminal of the fuse circuitry coupled to the supply terminal, the control terminal of the fuse circuitry coupled to the first terminal of the transistor (see M3 or M5 for example); and converter circuitry having a terminal coupled to the second terminal of the fuse circuitry.
With respect to claims 5 and 10 Lam teaches the fuse circuitry is first fuse circuitry, the terminal of the converter circuitry is a first terminal, the converter circuitry further having a second terminal, the apparatus further comprising: a logic device (see Fig. 2A and 3 see logic element on SSD) having a first terminal (see connection with 235 and 235) and a second terminal, the first terminal of the logic device coupled to the enable terminal (see connection with the control of gates of 92-93) of the first fuse circuitry and the fault terminal of the fault circuitry; and second fuse circuitry (93) having a first terminal and an enable terminal, the first terminal of the second fuse circuitry coupled to the second terminal of the converter circuitry, the enable terminal of the second fuse circuitry coupled to the second terminal of the logic device.
With respect to claim 6 Lam teaches a first resistor (R2) having a first terminal and a second terminal, the first terminal of the first resistor coupled to the supply terminal; and a second resistor (R1) having a first terminal and a second terminal, the first terminal of the second resistor coupled to the enable terminal of the fault circuitry and the second terminal of the first resistor, the second terminal of the second resistor coupled to a common potential.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-3, 9, 11, 14-18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Lam in view of Jenkins et al. (US 20230076383).
With respect to claims 2 and 9 Lam teaches the terminal of the converter circuitry (see buck/boost switching converter) is a first terminal, the converter circuitry further has a second terminal, the fault circuitry includes: fault detection circuitry (see terminal in Fig. 3) having a first terminal and a second terminal, the first terminal of the fault detection circuitry coupled to the second terminal of the converter circuitry; fault latch (paragraph 40-41) circuitry coupled with the suppled and fault circuity and a transistor (see M3 and M5) having a first terminal and a control terminal, the first terminal coupled to the enable terminal of the fuse circuitry, the control terminal of the transistor coupled to the third terminal of the fault latch circuitry. Lam does not teach the terminals of the latching having a first terminal, a second terminal, and a third terminal. Latching circuits are known to include first second and third terminals. Jenkins teaches latching circuitry having a first terminal, a second terminal, and a third terminal (see Fig. 3), the first terminal of the fault latch circuitry coupled to the supply terminal, the second terminal of the fault latch circuitry coupled to the second terminal of the fault detection circuitry. It would have been obvious to one of ordinary skill in the art at the time of the invention to modify Lam to include a latch and terminal connections for the predictable result of maintaining the abnormal operation.
With respect to claims 3 and 11 Lam teaches the fault circuitry includes open loop regulation (see for example soft start regulation) a first terminal and a second terminal (input and output of Vin to Vout), the first terminal of the open loop regulator circuitry coupled to the supply terminal; and latch circuitry however does not teach the second terminal of the open loop regulator circuitry, the second terminal of the latch circuitry coupled to the enable terminal of the fuse circuitry. Jenkins teaches second terminal of the open loop regulator circuitry (from 122 across 150 to 114), the second terminal of the latch circuitry coupled to the enable terminal of the fuse circuitry. It would have been obvious to one of ordinary skill in the art at the time of the invention to modify Lam to include connection of open loop circuitry with a latch for the predictable result of ensuring the proper voltage is maintained.
With respect to claim 14 Lam teaches the fault latch circuitry (292) further includes: voltage clamp (see voltage clipping paragraph 0055) circuitry having a terminal; and supply rail monitor circuitry (OV and UV) having a terminal coupled to the second terminal of the open loop regulator circuitry, the first terminal of the latch circuitry and the terminal of the voltage clamp circuitry.
With respect to claims 15 and 20 Lam teaches fuse circuitry (see Fig. 3 for example 92-93) configured to control a supply of power; and fault circuitry (see circuitry determining overvoltage under voltage and current abnormalities Fig. 3) coupled to (see connection to 92-93) the fuse circuitry, the fault circuitry configured to: generate an assert fault indication (see over under voltage outputs and current control) responsive to a fault condition being met; set a fault gate indication (output to control M3 or M5) responsive to latching the assert fault indication (paragraph 0040-41); disable the supply of power (opening 92-93) by the fuse circuitry responsive to latching the assert fault indication; and setting normal operation when condition are met (operating normal mode paragraph 0041). Lam does not teach the resetting operation. Jenkins teaches the known use of resetting (paragraph 0030-31) after conditions are met. It would have been obvious to one of ordinary skill in the art at the time of the invention to modify Lam to reset operations for the predictable result of allowing normal operations after the passing of a disturbance.
With respect to claim 16 Lam teaches the fault circuitry further configured to pull-down a control terminal of the fuse circuitry responsive to the fault circuitry latching the assert fault indication (see connection with ground when M3 or M5 is open).
With respect to claim 17 Lam teaches the fuse circuitry is first fuse circuitry, the apparatus further comprising second fuse circuitry (93) coupled to the fault circuitry, the fault circuitry further configured to disable the supply of power by the second fuse circuitry responsive to latching the assert fault indication.
With respect to claim 18 Lam teaches the fault circuitry however does not detail the resetting operations. Jenkins teaches the known use of a latch (302) for holding the state the fault gate indication. It would have been obvious to one of ordinary skill in the art at the time of the invention to modify Lam to include the known use of holding a fault for the predictable result of ensuring fault is held until the system in in a normal state of operation to protect the connected load.
Allowable Subject Matter
Claims 4, 12-13 and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter:
With respect to claims 4, 12 and 19 Lam teaches the latch circuity however does not teach the latch circuitry further has a third terminal, and the fault latch circuitry further includes: level shifter circuitry having a first terminal and a second terminal, the first terminal of the level shifter circuitry coupled to the third terminal of the latch circuitry; and voltage clamp circuitry having a terminal coupled to the second terminal of the open loop regulator circuitry, the first terminal of the latch circuitry, and the second terminal of the level shifter circuitry. At least this further limitation is not taught or rendered obvious by the prior art of record.
With respect to claim 13 Lam teaches the fault latch circuitry however does not teach latch safety circuitry having a first terminal and a second terminal, the first terminal of the latch safety circuitry coupled to the second terminal of the open loop regulator circuitry and the first terminal of the latch circuitry; and latch reset circuitry having a terminal coupled to the second terminal of the latch circuitry and the second terminal of the latch safety circuitry. At least this further limitation is not taught or rendered obvious by the prior art of record.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Michael Fin whose telephone number is (571)272-5921. The examiner can normally be reached Monday-Friday 9am-5:30.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Rexford Barnie can be reached at 571-272-7429. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
MICHAEL FIN
Primary Examiner
Art Unit 2836
/MICHAEL R. FIN/Primary Examiner, Art Unit 2836