DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement(s) (IDS/IDSs) submitted on 2/28/2024, 4/7/2025, 5/15/2025, & 12/30/2025 is/are in compliance with the provisions of 37 CFR 1.97. Accordingly, the IDS/IDSs is/are being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 15, 17-20, and 23 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by United States Patent App. Pub. No. 20210083567 to Hasan.
Regarding claim 1, Hasan teaches a current sensing system for sensing current through first and second circuit elements of a circuit in which the first and second circuit elements are active in respective first and second phases of an operational cycle of the circuit, the current sensing system comprising:
first current sensing circuitry for sensing a current through the first circuit element (281);
second current sensing circuitry for sensing a current through the second circuit element (282); and
summation circuitry coupled to an output of the first current sensing circuitry and an output of the second current sensing circuitry (283), wherein the summation circuitry is configured to output a summation signal indicative of a sum of the sensed current through the first circuit element and the sensed current through the second circuit element so as to provide an indication of a total current drawn over an operational cycle of the circuit (fig. 9 & ¶ [0057]).
Regarding claim 15, Hasan teaches the current sensing system of claim 1, further comprising control circuitry operable to activate or enable the first current sense circuitry when the first circuit element is active and to activate or enable the second current sense circuitry when the second circuit element is active (¶ [0034]).
Regarding claim 17, Hasan teaches the current sensing system of claim 1, wherein the current sensing system further comprises a filter coupled to an output of the summation circuitry, the filter comprising:
a sample switch (613); and
a hold capacitor (631),
wherein in operation of the current sensing system, the filter is operable to maintain a substantially constant filter output for the duration of a non-overlap period of operation of the circuit (fig. 6; ¶ [0051]).
Regarding claim 18, Hasan teaches the current sensing system of claim 17, wherein in operation of the current sensing system, the filter is operable to sample a signal indicative of an output current of the summation circuitry at a time immediately before the start of the non-overlap period, and to output a filter output voltage based on the sampled signal for the duration of the non-overlap period (¶¶ [0051]-[0053]).
Regarding claim 19, Hasan teaches an integrated circuit comprising a current sensing system according to claim 1 (¶ [0033]).
Regarding claim 20, Hasan teaches an inductive power converter comprising:
a low-side switch for coupling a terminal of an inductor to a reference voltage supply in a first phase of operation of the inductive power converter (claim 8);
a high-side switch for coupling the terminal of the inductor to an output node of the inductive power converter in a second phase of operation of the inductive power converter (claim 8);
switch control circuitry configured to control operation of the low-side switch and the high-side switch over an operational cycle of the inductive power converter, wherein an operational cycle includes the first phase of operation and the second phase of operation (claim 8); and
a current sensing system for sensing current through the low-side switch and the high-side switch (fig. 6), the current sensing system comprising:
first current sensing circuitry for sensing a current through the low-side switch (281);
second current sensing circuitry for sensing a current through the high-side switch (282); and
summation circuitry coupled to an output of the first current sensing circuitry and an output of the second current sensing circuitry (283), wherein the summation circuitry is configured to output a summation signal indicative of a sum of the sensed current through the low-side switch and the sensed current through the high-side switch so as to provide an indication of a total current drawn over an operational cycle of the inductive power converter (fig. 9 & ¶ [0057]).
Regarding claim 23, Hasan teaches a current sensing system for sensing current in a circuit that comprises first and second switches, wherein the circuit is configured to implement a switching control scheme that includes a non-overlap period in which the first and second switches are both open, the system comprising a filter comprising:
a sample switch (613); and
a hold capacitor (631),
wherein in operation of the current sensing system, the filter is operable to maintain a substantially constant filter output for the duration of the non-overlap period (fig. 6; ¶ [0051]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hasan in view of United Kingdom Patent App. No. GB2606440A to Zanbaghi et al.
Regarding claim 2, Hasan teaches current sensing system of claim 1, but does not teach explicitly further comprising analog to digital converter (ADC) circuitry for converting the summation signal to a digital signal indicative of the total current drawn over an operational cycle of the circuit.
But Zanbaghi teaches further comprising analog to digital converter (ADC) circuitry for converting the summation signal to a digital signal indicative of the total current drawn over an operational cycle of the circuit (¶ [0022]).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to add an ADC to the system of claim 1 in order to provide a digital output, thereby simplifying the computing power required to process the signal downstream.
The examiner notes that the applicant in ¶ [0060] of the specification as filed stated explicitly that an ADC is not required; the applicant also does not provide any explanation of how an ADC provides any advantage over or patently distinguish the claimed system from the prior art.
Claim(s) 21 & 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hasan.
Regarding claims 21 & 22, Hasan teaches the system of claim 1 but does not teach explicitly the remaining limitations. However, implementing a known function on a computer has been deemed obvious to one of ordinary skill in the art if the automation of the known function on a general purpose computer is nothing more than the predictable use of prior art elements according to their established functions. KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007); see also MPEP § 2143, Exemplary Rationales D and F and MPEP § 2114(IV). Because the limitations of claims 21 & 22 are known other than mere basic programming, i.e., merely general purpose computer-based implementation of the method, that limitation does not patentably distinguish the claim over the prior art.
Allowable Subject Matter
Claims 3-14 & 16 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Specifically, the prior art of record does not teach or fairly suggest the following limitations:
in claim 3, “wherein the first current sensing circuitry and the second current sensing circuitry each comprise: a first current sense path having an input for coupling to a first node of the respective first or second circuit element, the first current sense path comprising a first plurality of replica devices; a second current sense path having an input for coupling to a second node of the respective first or second circuit element, the second current sense path comprising a second plurality of replica devices, wherein the second plurality is equal to the first plurality; and differential amplifier circuitry having a first input coupled to an output of the first current sense path and a second input coupled to an output of the second current sense path, wherein the differential amplifier circuitry is configured to output a differential replica current pair indicative of the current through the respective first or second circuit element,” and
in claim 4, “wherein the summation circuitry comprises transimpedance amplifier circuitry and a conversion element,”
in combination with all other limitations.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
United States Patent App. Pub. No. 20230341444 to Desai et al. discloses a power converter that includes a feedback circuit for controlling a voltage of the sense transistor to ensure it is biased according to the bias of a switching transistor of the power converter.
United States Patent App. Pub. No. 20230275508 to Guedon et al. discloses a wireless power reception system that utilizes a switched capacitor DC-DC voltage converter to charge a load.
United States Patent App. Pub. No. 20180301174 to Arno discloses a low offset current sense amplifier having first and second intermediate nodes coupled to first and second nodes of a sense resistor by a chopper, and to respective branches of a current mirror.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Robert P Alejnikov whose telephone number is (571)270-5164. The examiner can normally be reached 10:00a-6:00p M-F.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Arleen Vazquez, can be reached at 571.272.2619. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ROBERT P ALEJNIKOV JR/Examiner, Art Unit 2857
/ARLEEN M VAZQUEZ/Supervisory Patent Examiner, Art Unit 2857