DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Claims 1, 2, 4-10, and 16-18 are allowed due to incorporating the previously indicated allowable subject matter of claim 3 into independent claim 1.
A new rejection in view of Matsuda et al (2022/0200328) has been issued to address the amendments made as seen below.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 11 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Matsuda et al (2022/0200328).
In re Claim 11, Matsuda teaches a method comprising: providing power to a load (10 and/or 130) with a power supply (50) (as seen in Figures 2 and 6) via a switch circuit (55), wherein the switch circuit comprises a forward-blocking semiconductor switch (55B) and a reverse-blocking semiconductor switch (55A), the forward-blocking semiconductor switch arranged in series with the reverse-blocking semiconductor switch (as seen in Figure 6); sensing current of the power supply (via 53, paragraph 63); and blocking, in response to the current exceeding a threshold, forward current from an electrical source with the forward-blocking semiconductor switch while simultaneously allowing reverse current to flow to the electrical source (Paragraphs 71 and 86 teach that both semiconductor switches 55A and 55B are activated during normal operation and that when a current larger than a threshold is detected only the forward blocking semiconductor switch 55B is turned off. As such, in this state reverse current is allowed to flow via the still activated switch 55A and diode 56B).
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Matsuda et al (2022/0200328).
In re Claim 12, Matsuda teaches a capacitor 41 to provide power to the load 130 (paragraph 88), but does not specifically teach a capacitor bank (i.e., a plurality of capacitors).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to implement the single capacitor of Matsuda as a plurality of capacitors since it was known in the art that a single capacitor can be replaced with a plurality of capacitors connected in series and/or parallel to achieve an equivalent overall capacitance.
Claim(s) 13, 14, and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Matsuda et al (2022/0200328) in view of Tsukamoto et al (2020/0402738).
In re Claim 13, Matsuda teaches that the forward blocking semiconductor switch 55B is switched off (paragraph 86), but does not teach a latch as claimed.
Tsukamoto teaches a power supply arrangement as seen in Figure 1 that involves a switch 2 being controlled by a controller 5, wherein the arrangement further comprises current feedback circuitry to monitor current through the switch for an overcurrent condition comprising resistor R1, amplifier 42, and comparator 43 (paragraph 45). Tsukamoto further teaches the current feedback circuity comprises a latch circuit 45 that receives input from the comparator and outputs logic low level signal, in the event an overcurrent is detected, to an AND gate 41 so that the switch remains biased in an open state (paragraphs 49-50).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to implement the current sensor of Matsuda with the current feedback circuitry including the latch as taught by Tsukamoto since it would provide current feedback and control logic that keeps the switch biased off in the event of an overcurrent without having to rely on an additional controller processing to make an overcurrent determination.
In re Claim 14, Matsuda teaches that the forward blocking semiconductor switch is turned off (paragraph 86), while reverse current is still allowed to flow through diode 56B as seen in Figure 6.
In re Claim 19, Matsuda teaches a current sensor 53, but does not teach a specific implementation.
Tsukamoto teaches a power supply arrangement as seen in Figure 1 that involves a switch 2 being controlled by a controller 5, wherein the arrangement further comprises current feedback circuitry to monitor current through the switch for an overcurrent condition comprising resistor R1, amplifier 42, and comparator 43 (paragraph 45).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to implement the current sensor of Matsuda with a resistor and operational amplifier as taught by Tsukamoto since Tsukamoto teaches a concrete arrangement for implementing a current sensor.
Allowable Subject Matter
Claims 1, 2, 4-10, and 16-18 are allowed.
Claims 15 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 1 has been amended to incorporate the previously indicated allowable subject matter of claim 3 as discussed above.
In re Claim 15, Matsuda fails to teach that the power provided is pulsed power to a patient via a probe.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER JAY CLARK whose telephone number is (571)270-1427. The examiner can normally be reached Monday - Friday, 10:00am - 6:00pm EST.
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/CHRISTOPHER J CLARK/Examiner, Art Unit 2838
/THIENVU V TRAN/ Supervisory Patent Examiner, Art Unit 2838