DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-4 are pending in this application.
Information Disclosure Statement
The information disclosure statement (IDS) was submitted on 01/06/2025. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 112
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 3 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 3 lines 1-3 recites “the SC fault is first monitored by the fault monitoring circuit at a time, t2, since no falling dv/dt of Vds is sensed”. Since no falling is sensed, what happens next is unclear. Specification paragraph [0020] does not provide any further clarification. For the purpose of examination, the above limitation is interpreted as -- the SC fault is first monitored by the fault monitoring circuit at a time, t2, by sensing fall in dv/dt of Vds, where in t2 is shorter than the blanking time t5--.
Claim 3 lines 4-5 recites “wherein once the SC fault is monitored at time t2 by the fault monitoring circuit”. Based on specification paragraph [0020], examiner interprets the above limitation as -- wherein once the SC fault is detected at time t2 by the fault monitoring circuit--.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2 and 4 are rejected under 35 U.S.C. 103 as being unpatentable over AAPA (Applicant’s Admitted Prior Art), and further in view of Liu (CN 110838787 B; Translation attached).
Regarding claim 1, AAPA teaches a circuit (e.g. conventional desaturation protection circuit, fig.1A) that provides blanking-time-less desaturation protection ([0006], trigger the protection once vds exceeds a threshold) for a power device ([0006], vds of power devices) during a fault ([0006], vds exceeds a threshold), comprising:
a desaturation protection sub-circuit (e.g. desaturation protection circuit, fig.1A); and
a totem-pole driver sub-circuit (e.g. circuit comprising transistors between Vcc and Vee, fig.1A),
wherein a drain-source voltage, Vds, of the power device are monitored during the fault ([0006], vds exceeds a threshold).
AAPA does not teach, a fault monitoring sub-circuit; and wherein a rate of change of the drain-source voltage, dv/dt, of the power device are monitored during the fault.
Liu teaches in a similar field of endeavor of SiC MOSFET power device, a fault monitoring sub-circuit (i.e. the dVDS/dt detection circuit (2), fig.4); and wherein a rate of change of the drain-source voltage, dv/dt, of the power device are monitored during the fault (page 7, the voltage value of the output voltage Vdv is: Vdv= - (R7/R8) * (C1 *R9) * (dVds/dt), the voltage signal Vdv and the PWM voltage Vpwm in the main drive circuit are output to the turn-off process detection judging circuit as input quantity).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included a fault monitoring sub-circuit; and wherein a rate of change of the drain-source voltage, dv/dt, of the power device are monitored during the fault in AAPA, as taught by Liu, as it provides the advantage of lower delay time and switch loss of the SiCMOSFET active driving circuit.
Regarding claim 2, AAPA and Liu teach the circuit of claim 1, wherein the fault comprises an over-current (OC) fault and detection of Vds by the desaturation protection sub-circuit is used to monitor the OC fault (AAPA, [0005], detects drain-source voltage vds of SiC MOSFET to monitor … over-current (OC) fault) (Liu, page 3, capable of inhibiting SiC MOSFET switch process of over-voltage/over-current).
Regarding claim 4, AAPA and Liu teach the system of claim 1, wherein the power device comprises a Si, SiC (AAPA, [0003], SiC MOSFETs (metal-oxide-semiconductor field effect transistors)) (Liu, [0004], SiC metal-oxide semiconductor field effect transistors (MOSFETs)), or GaN power device.
Allowable Subject Matter
As allowable subject matter has been indicated, applicant's reply must either comply with all formal requirements or specifically traverse each requirement not complied with. See 37 CFR 1.111(b) and MPEP § 707.07(a).
Claim 3 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 3, AAPA (Applicant’s Admitted Prior Art) and Liu (CN 110838787 B; Translation attached) teach the circuit of claim 1, wherein the fault comprises a short-circuit (SC) fault (AAPA, [0005], Desaturation protection detects drain-source voltage vds of SiC MOSFET to monitor both SC fault at hard-switching-fault (HSF) condition) and then monitored by the desaturation protection circuit at time t5 (AAPA, [0005], Desaturation protection detects drain-source voltage vds of SiC MOSFET to monitor both SC fault at hard-switching-fault (HSF) condition).
AAPA and Liu do not teach the SC fault is first monitored by the fault monitoring circuit at a time, t2, by sensing fall in dv/dt of Vds, where in t2 is shorter than the blanking time t5, and
wherein once the SC fault is detected at time t2 by the fault monitoring circuit, active gate clamping is activated by the totem-pole driver sub-circuit to mitigate a SC current until desaturation protection is triggered at time t5, after which the power device is fully turned off,
wherein the circuit provides a fault response time (t0 to t2) that is shorter than a blanking time (t0 to t5) required by conventional desaturation protection methods.
Prior art Geng (WO 2022088010 A1), Li (US 20210098982 A1) and Kim (WO 2021040153 A1) are found to be the closest prior art.
However, none of the prior art, taken singly or in combination, teach “the SC fault is first monitored by the fault monitoring circuit at a time, t2, by sensing fall in dv/dt of Vds, where in t2 is shorter than the blanking time t5, and
wherein once the SC fault is detected at time t2 by the fault monitoring circuit, active gate clamping is activated by the totem-pole driver sub-circuit to mitigate a SC current until desaturation protection is triggered at time t5, after which the power device is fully turned off,
wherein the circuit provides a fault response time (t0 to t2) that is shorter than a blanking time (t0 to t5) required by conventional desaturation protection methods.”
Conclusion
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/SREEYA SREEVATSA/ Primary Examiner, Art Unit 2838 10/22/2025