Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. This application claims domestic priority to 08/26/2022.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 9, 17, and 19 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
3. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
4. Claims 1, 9, 17, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Nishiguchi et al. Pub. No. US 2011/0238947 A1 (hereafter Nishiguchi) in view of Kissell Pub. No. US 2006/0195683 and Wei et al. Pub. No. US 2022/0083468 A1 (hereafter Wei).
5. Regarding claim 1, Nishiguchi teaches “A method, implemented by a computer system, wherein the method comprises: allocating, from a first address space identifier (ASID) resource pool, first ASIDs identifiers to first processes configured to be run by a first processor core of the computer system ([0056] teaches allocating an ASID to a process), allocating a second ASID to a second process configured to be run by a second processor core of the computer system, wherein the second processor core is in an isolated environment ([0056] teaches allocating an ASID to a process, wherein [0036-0039] teaches that the process may be configured to be run by an OS operating on a VM, one of the VM’s being for full-virtualization that can directly operate OS without modifying the OS such that the cores allocated to that VM is isolated); and when the first ASIDs in the ASID resource pool are exhausted; … invalidating the first ASIDs; and refreshing a translation lookaside buffer (TLB) ... in the first processor core ([0068] teaches when all actual ASIDs are in use such that they are exhausted; the ASID management section may then set TLB necessity flags to necessary as well as overlap flags, which may cause the invalidation of the ASID as described in [0070]. [0089] teaches determining whether a TLB flush is necessary, and by extracting entries whose flags are marked necessary, that may determine if a flush is necessary as taught in [0104-0108]).”
Nishiguchi does not explicitly teach of iterating a generation identifier after the ASID pool is exhausted.
Kissell teaches an ASID generation rollover to a new generation such that it teaches the limitation “and when the first ASIDs in the ASID resource pool are exhausted; updating the first ASIDs in an ASID generation iteration manner to provide updated first ASIDs ([0200-0205])”.
It would have been obvious to a person of ordinary skill in the art before the effective
filing date to combine the teachings of Kissell to the invention of Nishiguchi for using the ASID generation iteration rollover when all ASIDs are exhausted. A person having ordinary skill in the art would have been motivated to make this combination to reuse ASIDs reduce the frequency of TLB flushing.
The combination may not explicitly teach of flushing only the first core.
Wei teaches a TLB shootdown method that may target TLBs in specific cores to be flushed such that it teaches the limitation “and refreshing a translation lookaside buffer (TLB) only in the first processor core ([0018-0020] teaches that a core may trigger a TLB shootdown wherein it requires flushing, wherein it may be just the first core that requires the flushing as it may be the only core whose page table entries have become stale, and as a result may cause a flush of the entirety of the TLB)”.
It would have been obvious to a person of ordinary skill in the art before the effective
filing date to combine the teachings of Wei to the invention of Nishiguchi and Kissell to implement a TLB shootdown configuration for flushing TLBs. A person having ordinary skill in the art would have been motivated to incorporate the TLB shootdown method of Wei to the combination of Nishiguchi and Kissell in order to flush the TLB when determining that all actual ASIDs are in use, causing a necessary flag which may trigger a TLB shootdown within a specific core. Applying the TLB shootdown configuration would provide a predictable way to determine an appropriate scope of the flush when available ASIDs are exhausted, thereby avoiding unnecessary flushing of other TLBs. Together, Wei in combination with Nishiguchi and Kissell teach every limitation of the claimed invention. Since the teachings were analogous art known at the filing time of the invention, one of ordinary skill could have applied said teachings to achieve expected results.
6. Regarding claim 9, it is similar to claim 1 and is rejected for the same reasons. Claim 9 is directed towards “A computing device, a computer-readable storage medium configured to store instruction, and one or more processors comprising a first processor core and a second processor core, wherein the second processor core is in an isolated environment, coupled to the computer-readable storage medium, and configured to execute the instructions (Nishiguchi [0002-0003], [0034-0037])”.
7. Regarding claim 17, it is similar to claim 1 and is rejected for the same reasons. Claim 17 is directed towards “A chip system comprising one or more processors, comprising a first processor core and a second processor core that is in an isolated environment (Kissell [0210])”.
8. Regarding claim 19, it is similar to claim 1 and is rejected for the same reasons. Claim 19 is directed towards “A computer program product comprising computer-executable instructions that are stored on a non-transitory computer-readable storage medium (Nishiguchi [Claim 11], or Kissell [0026] for product)”.
9. Claims 2, 10, 18, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Nishiguchi, Kissell, and Wei as used in claims 1, 9, 17, and 19 above, and in further view of Manczak et al. Pub. No. US 2007/0283125 A1 (hereafter Manczak).
10. Regarding claim 2, the combination does not explicitly teach a second ASID resource pool.
Manczak teaches different process IDs associated with different address ranges such that it teaches the limitation “The method of claim 1, wherein allocating the second ASID to the second process comprises allocating the second ASID from a second ASID resource pool to the second process, wherein the second ASID resource pool comprises third ASIDs, and wherein the second ASID is one of the third ASIDs (Fig. 10 & [0111-0113] teach specific address ranges allocated to a single process ID such that it could represent different pools of address space identifiers being used for certain processes)”.
It would have been obvious to a person of ordinary skill in the art before the effective
filing date to combine the teachings of Manczak to the combination of Nishiguchi and Kissell for having separate address ranges for different processes. A person having ordinary skill in the art would have been motivated to make this combination to have reserved address ranges for more critical/higher access processes like system software (Manczak [0113]). Together, Manczak in combination with Nishiguchi and Kissell teach every limitation of the claimed invention. Since the teachings were analogous art known at the filing time of the invention, one of ordinary skill could have applied said teachings to achieve expected results.
11. Regarding claims 10, 18, and 20, they are similar to claim 2 and are rejected for the same reasons.
12. Claims 3-5, 8, 11-13, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Nishiguchi, Kissell, and Wei as used in claims 1 and 9 above, and in further view of Olgiati et al. Pat. No. US 9,858,199 B1 (hereafter Olgiati).
13. Regarding claim 3, the combination teaches “The method of claim 1, further comprising: further allocating the second ASID from the first ASID resource pool further comprises at least one third ASID, and wherein the second ASID is a third ASID (Nishiguchi [0067-0068] teaches allocating ASIDS that is not used by the same VM such that it may be another ASID for a different VM/process);
The combination does not explicitly teach of storing reservation information.
Olgiati teaches a bitmap indicating a reserved address such that it teaches the limitation “storing reservation information of the second ASID, wherein the reservation information indicates that the second ASID is reserved; and determining the first ASIDs based on the reservation information ([Col. 6, lines 36 – 54] teaches a bitmap with bit identifiers indicating whether or not a space has been allocated to such that it may be a second ASID being marked as reserved. It also mentions of multiple bitmaps such that there may be one for the first ASIDs to show that they are allocated)”.
It would have been obvious to a person of ordinary skill in the art before the effective
filing date to combine the teachings of Olgiati to the combination of Nishiguchi and Kissell to implement a bitmap for the reservation of allocated address spaces. A person having ordinary skill in the art would have been motivated to make this combination of having separate bitmaps to identify what address spaces are reserved/allocated. Together, Olgiati in combination with Nishiguchi and Kissell teach every limitation of the claimed invention. Since the teachings were analogous art known at the filing time of the invention, one of ordinary skill could have applied said teachings to achieve expected results.
14. Regarding claim 11, it is similar to claim 3 and is rejected for the same reasons.
15. Regarding claim 4, wherein the combination, Olgiati teaches “The method of claim 3, further comprising modifying, a first identifier in an identifier bit corresponding to the second ASID from an unreserved state to a reserved state in a reservation bitmap, wherein the reservation bitmap records a reservation status of each of the at least one third ASID and the first ASID ([Col. 6, lines 36 – 54] teach a bitmap with a bit that indicates whether an address space is allocated; 0 for no, and 1 for reserved such that it records the reservation status of every ASID, or based on each different bitmap doing so for its respective ASIDs)”.
16. Regarding claim 12, it is similar to claim 4 and is rejected for the same reasons.
17. Regarding claim 5, the combination teaches “The method of claim 4, further comprising: determining, the first ASIDs on which generation iteration are to be performed based on a global bitmap and the reserved state wherein the global bitmap records allocation statuses of the first ASIDs and the at least one third ASID (Nishiguchi [0007] teaches that when a domain is overlapped, it requires a TLB flush such that it would trigger a generation rollover as taught and combined in Kissell [0205] to be performed, and it also teaches of a global and a local domain such that they may be represented by a bitmap as taught and combined with by Olgiati [Col. 6, lines 36 – 54]); and modifying, second identifiers that are in the global bitmap and that indicate first statuses of the first ASIDs from an allocated state to an unallocated state after updating the first ASIDs in the ASID generation iteration manner (Kissell [0205-0206] teaches after the ASID generation rollover occurs, old ASIDs retained may generate new TLB entries such that they will be marked in the bitmap as reserved as taught in Olgiati)”.
18. Regarding claim 13, it is similar to claim 5 and is rejected for the same reasons.
19. Regarding claim 8, the combination teaches “The method of claim 4, further comprising: obtaining a context identifier of the second process identifying that the context identifier comprises a non-isolation identifier (Nishiguchi [0043] teaches using VMID and virtual ASIDs as keys such that a VMID may represent the isolated VM and the virtual ASIDs on that VM are the context identifiers); and in response to identifying that the context identifier comprises the non-isolation identifier: modifying the non-isolation identifier into an isolation identifier and modifying a second identifier that is of a fourth ASID comprised in the context identifier (Nishiguchi [0139-0140] teaches of virtual ASIDs having an overlapped state or non-overlapped state based on their priority, and the relation to overlapped virtual ASIDs can be changed until the overlap of the virtual ASID whose use frequency is low is eliminated essentially shows the states changed from overlapped (shared, non-isolated) state to a non-overlapped (isolated) state) and that is in the reservation bitmap from the unreserved state to the reserved state (Olgiati [Col. 6, lines 34 – 64] teach of the multiple bitmaps such that one may represent the local bitmap and would indicate a reserved state as such if the ASIDs are retained and allocated).”
20. Regarding claim 16, it is similar to claim 8 and is rejected for the same reasons.
21. Claims 6, 7, 14, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Nishiguchi, Kissell, Wei, and Olgiati as used in claims 4 and 5 above, and in further view of TAVALLAEI et al. Pub. No. US 2022/0179780 A1 (hereafter TAVALLAEI).
22. Regarding claim 6, the combination teaches “The method of claim 4, further comprising: identifying that the first ASID resource pool comprises an unallocated ASID, and a quantity of the at least one third ASID allocated to third processes configured to be run by the second processor core exceeds a waterline, wherein the waterline indicates a maximum quantity of the at least one third ASID reserved for the second processor core (Nishiguchi [0068] teaches when all actual ASIDs are in use such that it may represent the quantity of third ASIDs reaching a waterline, causing the allocation of non-overlapped actual ASIDs from another identified VM such that the identified VM still has unallocated ASIDs available from its pool); and in response to identifying that the first ASID resource pool further comprises the unallocated ASID and the quantity of the at least one third ASID exceeds the waterline; allocating the unallocated ASID to a fourth process configured to be run by the second processor core (Nishiguchi [0068] teaches allocating non-overlapped ASIDs to a VM that has all of its ASIDs in use such that it may be allocating to a new (fourth) process to be run by the VM that is isolated); and modifying a second identifier bit that is of the unallocated ASID and that is in the reservation bitmap from the unreserved state to the reserved state (Olgiati [Col. 6, lines 36 – 54] teaches that newly allocated address spaces will change the bit identifier to 1 to indicate a reserved address space)”.
The combination may not explicitly define a waterline such that it represents a maximum amount of memory space allocated to a processor.
TAVALLAEI teaches an address space size which may exceed physical memory available such that it teaches the limitation “a quantity of the at least one third ASID allocated to third processes configured to be run by the second processor core exceeds a waterline, wherein the waterline indicates a maximum quantity of the at least one third ASID reserved for the second processor core… ([0030] teaches address space size exceeding physical memory available to a compute node, wherein availability refers to the amount of memory from the pool of memory that was assigned to that node such that it may represent the waterline for a max amount of ASIDs allocated)”.
It would have been obvious to a person of ordinary skill in the art before the effective
filing date to combine the teachings of TAVALLAEI to the combination of Nishiguchi, Kissell, and Olgiati to show an amount of allocated memory space being exceeded. A person having ordinary skill in the art would have been motivated to make this combination to set a trigger condition of allocating more address spaces from another unallocated space to one that requires it, improving utilization efficiency and avoiding ASID exhaustion/frequent flushing. Together, TAVALLAEI in combination with Nishiguchi, Kissell, and Olgiati teach every limitation of the claimed invention. Since the teachings were analogous art known at the filing time of the invention, one of ordinary skill could have applied said teachings to achieve expected results.
23. Regarding claim 14, it is similar to claim 6 and is rejected for the same reasons.
24. Regarding claim 7, the combination teaches “The method of claim 5, further comprising: identifying that the first ASID resource pool does not include an unallocated ASID and a quantity of the at least one third ASID allocated to third processes configured to be run by the second processor core exceeds a waterline, wherein the waterline indicates a maximum quantity of the at least one third ASID reserved for the second processor core (Nishiguchi [0138] teaches the VM requesting an allocation of virtual ASIDs larger than the number of ASIDs, causing it to allocate ASIDs in an overlapped manner such that it has run out of actual non-overlapped ASIDs (unallocated ASIDs) and have reached a limit of ASIDs, the ratio possibly indicating a max amount of actual ASIDs); and in response to identifying that the first ASID resource pool does not include the unallocated ASID and the quantity of the at least one third ASID exceeds the waterline, updating the first ASIDs and the at least one third ASID; modifying third identifiers that indicate second statuses of the first ASIDs and the at least one third ASID and that are in the global bitmap from the allocated state to the unallocated state; and modifying fourth identifiers in the reservation bitmap from a from the reserved state to the unreserved state (Olgiati [Col. 6, lines 36 – 64] teaches multiple bitmaps indicating a reserved state or an unreserved state with a ‘1’ or ‘0’ respectively, such that after a TLB flush taught in Nishiguchi, and regions unallocated would inherently indicate the address space as such, such that the multiple bitmaps may be bitmaps of a local domain and a global domain respectively)”.
25. Regarding claim 15, it is similar to claim 7 and is rejected for the same reasons.
Conclusion
26. THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
27. Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRANDON A NGUYEN whose telephone number is (571)272-6074. The examiner can normally be reached Mon-Fri (10am-6pm).
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/BRANDON NGUYEN/Examiner, Art Unit 2195
/Aimee Li/Supervisory Patent Examiner, Art Unit 2195
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