Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 is/are rejected under 35 U.S.C. 103 as being unpatentable over Limberge et al [ 20210097419], in view of Govindu [20140189316]
As to claim 1,
Limberge et al [ 20210097419] teach: A method, comprising: identifying, by a computing apparatus, a plurality of configurations of executing a program on a device [ 0003: “a system can comprise a memory that stores computer executable components and a processor that executes the computer executable components stored in the memory. ”, 0022: “quantum platform routing system 102 and/or components thereof can employ such one or more classical and/or quantum computing resources to execute one or more classical and/or quantum: mathematical function, calculation, and/or equation; computing and/or processing script; algorithm; model (e.g., artificial intelligence (AI) model, machine learning (ML) model, etc.) ” and 0130; “any computing processing unit or device comprising, but not limited to, single-core processors; single-processors with software multithread execution capability; multi-core processors; multi-core processors with software multithread execution capability; multi-core processors with hardware multithread technology; parallel platforms; and parallel platforms with distributed shared memory. 0043: “Memory 104 can store one or more computer and/or machine readable, writable, and/or executable components and/or instructions that, when executed by processor 106 (e.g., a classical processor, a quantum processor, etc.), can facilitate performance of operations defined by the executable component(s) and/or instruction(s). ” and 0045: “Processor 106 can comprise one or more types of processors and/or electronic circuitry (e.g., a classical processor, a quantum processor, etc.) that can implement one or more computer and/or machine readable, writable, and/or executable components and/or instructions that can be stored on memory 104 ”- when it reads and processes data, memory has to store in specific location for the each devices.];
determining, by the computing apparatus, performance metrics of the configurations in execution of the program [0050: “one or more computer and/or machine readable, writable, and/or executable components and/or instructions that, when executed by processor 106, can facilitate performance of operations defined by such component(s) and/or instruction(s).”- performance is determined]; and
identifying, by the computing apparatus from the plurality of configurations in response to one or more criteria, a first configuration of executing the program on the device based on the one or more criteria and the performance metrics [0057: “each quantum platform can comprise certain (e.g., desirable) qualities such as, for instance, speed, accuracy, noise, etc., determination component 110 can select at least one quantum platform comprising quantum hardware and/or quantum software that can execute one or more components of a quantum application based on one or more defined run criteria related to, for instance: a) feasibility (e.g., whether or not a quantum platform supports one or more certain components of a certain quantum application); and/or b) achieving defined results (e.g., a certain quantum platform may produce results that are more desirable than that of another quantum platform). ”- criteria can be multiple things from device selection, software selection, or speed while the achieving defined results is a performance metrics desired.].
But does not explicitly teach the program configured to identify data flows through memory locations
Govindu [20140189316] the program configured to identify data flows through memory locations [ 0034: “the scheduler may detect a data dependency by performing a register location comparison of a store instruction and a load instruction that is younger than the store instruction. Detecting dependences when data flows through the register file may be more straightforward than when data flows through memory, since register names can be more or less fixed at the time of issue. Dependences that flow through memory locations may be more complex to detect because address computation has to be done before dependences can be detected.”] And a plurality of circuit units configured to operate in parallel [0041: “during a data forwarding operation, the forwarding logic may be configured to control the bypass network to send data received from the producing execution subunit to the load/store unit and the consuming execution subunit in parallel. ”]
It would have been obvious to person of ordinary skill in the art to combine teaching of Limberge and Govindu because both are directed toward computing task by executing instruction. Furthermore, Govindu improves upon Limberge by being able to flow of data from memory location in order for system to handle data smoothly for faster processing.
Response to Arguments
Applicant's arguments filed 2/25/2026 have been fully considered but they are not persuasive. because
Applicant argument: The prior art references Limberge (20210097419), and Govindu (20140189316) fail to teach or disclose providing techniques of configuring a coarse grained reconfigurable array to run an assembly language program specifying data flows through memory locations represented by memory variables, as claimed by Applicant.
Limberge (20210097419) is limited to disclosing a quantum platform routing of a quantum application component. As disclosed, computer executable components can comprise a dissection component that identifies components of a quantum application. The computer executable components can further determine a component that selects at least one quantum platform to execute the one or more components of the quantum application based on a defined run criterion.
Govindu (20140189316) is limited to disclosing an execution pipeline having a plurality of execution subunits, a method of using a bypass network to directly forward data from a producing execution subunit to a consuming execution subunit. The method includes producing output data with the producing execution subunit, consuming input data with the consuming execution subunit. For one or more intervening operations whose input is the output data from the producing execution subunit and whose output is the input data to the consuming execution subunit. Evaluating those one or more intervening operations to determine whether their execution would compose an identify function. If the one or more intervening operations would compose such an identity function, controlling the bypass network to forward the producing execution subunit's output data directly to the consuming execution subunit.
Accordingly, the prior art references Limberge (20210097419), and Govindu (20140189316) fail to teach or disclose providing techniques of configuring a coarse-grained reconfigurable array to run an assembly language program specifying data flows through memory locations represented by memory variables, as claimed by Applicant.
Examiner’s answer: Limberge teaches 0057: “each quantum platform can comprise certain (e.g., desirable) qualities such as, for instance, speed, accuracy, noise, etc., determination component 110 can select at least one quantum platform comprising quantum hardware and/or quantum software that can execute one or more components of a quantum application based on one or more defined run criteria related to, for instance: a) feasibility (e.g., whether or not a quantum platform supports one or more certain components of a certain quantum application); and/or b) achieving defined results (e.g., a certain quantum platform may produce results that are more desirable than that of another quantum platform). ”- where in selecting at least one quantum plantform comprising hardware and/or software is method identifying and based on its speed, accuracy, or any qualities because determination is not a random selection, it takes consideration of one or the other thing, selecting at least one meaning it has to have more than one platform.
Furthermore, claim does not recite independent claim “configuring a coarse-grained reconfigurable array to run an assembly language program” as applicant claimed.
Allowable Subject Matter
Claim 11- 20 allowed.
Claim 2-10 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KESHAB R PANDEY whose telephone number is (571)270-0176. The examiner can normally be reached Monday-Friday 9:00-5:00(ET).
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/KESHAB R PANDEY/ Primary Examiner, Art Unit 2176
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