Prosecution Insights
Last updated: July 17, 2026
Application No. 18/590,512

POWER AMPLIFIER INTEGRATED CIRCUIT WITH TUNABLE IMPEDANCE MATCHING

Non-Final OA §102
Filed
Feb 28, 2024
Priority
Nov 20, 2023 — EU 23307006.9
Examiner
CHOE, HENRY
Art Unit
Tech Center
Assignee
NXP Semiconductors N.V.
OA Round
1 (Non-Final)
93%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
91%
With Interview

Examiner Intelligence

Grants 93% — above average
93%
Career Allowance Rate
1258 granted / 1359 resolved
+32.6% vs TC avg
Minimal -1% lift
Without
With
+-1.2%
Interview Lift
resolved cases with interview
Fast prosecutor
1y 10m
Avg Prosecution
24 currently pending
Career history
1371
Total Applications
across all art units

Statute-Specific Performance

§101
0.7%
-39.3% vs TC avg
§103
49.9%
+9.9% vs TC avg
§102
36.3%
-3.7% vs TC avg
§112
3.0%
-37.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1359 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim(s) 16, 24 and 30 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by [Kingsley (Figs 1B, 7); 2015/0180426]. Regarding claims 16 and 24, Kingsley discloses an amplifier Integrated Circuit (Fig. 1B) comprising a power amplifier (106) having an output (112), a output node (output terminal of 106) coupled to the output (112) of the power amplifier (106), and a tunable impedance matching network (116) comprising a tunable inductor (210, 206, 201) coupled to the output node (output terminal of 106) and the tunable inductor (210, 206, 201) comprising a plurality of switches (206, 201) configured to selectively modify the tunable inductor to have a first inductance (inductance of 210 when the switches 201 and 206 are ON) in a test mode (when the switches 201 and 206 are ON) and a second inductance (inductance of 210 when the switches 201 and 206 are OFF) in a functional mode (when the switches 201 and 206 are OFF). Regarding claim 30, Kingsley discloses an amplifier Integrated Circuit (Fig. 1B) comprising a signal source (the element generating the input signal RF IN) configured to generate a signal (RF IN), Fig. 1B of Kingsley inherently includes an antenna since it (Fig. 1B) would not work without a load (antenna), an integrated circuit (Fig. 1B) coupled between the signal source (the element generating the input signal RF IN) and the antenna (load connecting to the output terminal 122), the Integrated Circuit (Fig. 1B) comprising a power amplifier (106) having an output (112), a output node (output terminal of 106) coupled to the output (112) of the power amplifier (106), and a tunable impedance matching network (116) comprising a tunable inductor (210, 206, 201) coupled to the output node (output terminal of 106) and the tunable inductor (210, 206, 201) comprising a plurality of switches (206, 201) configured to selectively modify the tunable inductor to have a first inductance (inductance of 210 when the switches 201 and 206 are ON) in a test mode (when the switches 201 and 206 are ON) and a second inductance (inductance of 210 when the switches 201 and 206 are OFF) in a functional mode (when the switches 201 and 206 are OFF). Allowable Subject Matter Claims 17-23, 25-29 and 31-35 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. 9,143,172 teaches an amplifier circuit with the tunable matching circuit. 9,083,294 teaches an amplifier circuit with the tunable matching inductor circuit. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Henry Choe whose telephone number is (571)272-1760. The examiner can normally be reached MONDAY-FRIDAY 5AM-11:00PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Han can be reached at 571-272-2078. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /HENRY CHOE/ Primary Examiner, Art Unit 2843 #2974
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Prosecution Timeline

Feb 28, 2024
Application Filed
Jul 01, 2026
Non-Final Rejection mailed — §102 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12683564
RFIC WITH SUBSTRATE PARTITION
3y 1m to grant Granted Jul 14, 2026
Patent 12683567
INPUT STAGE CIRCUIT FOR AN OPERATIONAL AMPLIFIER WITH ENHANCED INPUT OFFSET VOLTAGE TRIMMING CAPABILITIES
2y 9m to grant Granted Jul 14, 2026
Patent 12671368
AMPLITUDE MODULATION-PHASE MODULATION (AM-PM) LINEARIZATION IN A POWER AMPLIFIER USING BIAS CIRCUITRY
4y 2m to grant Granted Jun 30, 2026
Patent 12671371
DIFFERENTIAL RADIO FREQUENCY AMPLIFIER
3y 8m to grant Granted Jun 30, 2026
Patent 12671375
ELECTRONIC CURRENT TUNING FOR QUIESCENT CURRENTS OF A GALLIUM NITRIDE BASED POWER AMPLIFIER
3y 1m to grant Granted Jun 30, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
93%
Grant Probability
91%
With Interview (-1.2%)
1y 10m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1359 resolved cases by this examiner. Grant probability derived from career allowance rate.

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