DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
The Examiner acknowledges the applicant's submission of the amendment dated 4/27/26, which has been entered.
1. ACKNOWLEDGEMENT OF REFERENCES CITED BY APPLICANT
Information Disclosure Statement
As required by M.P.E.P. ' 609 (C), the applicant's submission of the Information Disclosure Statement, dated 4/27/26, is acknowledged by the examiner and the cited references have been considered in the examination of the claims now pending. As required by M.P.E.P. ' 609 C(2), a copy of the PTOL-1449 initialed and dated by the examiner is attached to the instant office action.
2. REJECTIONS NOT BASED ON PRIOR ART
a. DEFICIENCIES IN THE CLAIMED SUBJECT MATTER
Claim Rejections - 35 USC ' 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea (e.g. "mental processes" which is defined as concepts performed in the human mind, and examples of mental processes include observations, evaluations, judgments, and opinions) without significantly more. The claim(s) recite(s)
(e.g. claim 1) an apparatus, comprising: prefetch table storage circuitry to store a prefetch table comprising entries corresponding to memory address regions and comprising access count indicators indicative of numbers of accesses to corresponding memory address regions and stream distance indicators having more than two stream distance indicating states, wherein a respective distance indicator of a respective entry is indicative of a respective stream distance between a respective memory address region corresponding to the respective entry and a respective root memory address region, wherein the respective root memory address region corresponds to a respective root entry of the prefetch table having a respective access count indicator indicating a number of accesses meeting a stream root detection threshold. (emphasis added) This is a judicial exception directed towards "mental processes" (i.e. data gathering/output) as it is an apparatus comprising a “prefetch table storage circuitry to store a prefetch table” comprising entries which corresponds to memory address regions and access count indicators and stream distance indicators. This judicial exception is not integrated into a practical application because it is merely performing a mental process which alternatively can be viewed as insignificant extra-solution activity, specifically pertaining to mere data gathering/output necessary to perform the abstract idea and is not sufficient to integrate the judicial exception into a practical application on a generic computer. The claim(s) does/do not include additional elements that are sufficient to amount to significantly more than the judicial exception because while it includes “prefetch table storage circuitry”, they do not add significantly more to the exception. The other independent claims and dependent claims do not add any other steps to overcome the rejection noted above, and rejected under a similar rationale.
3. REJECTIONS BASED ON PRIOR ART
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC ' 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-14 and 16-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kocev (US 20080288751).
With respect to claim 1, the Kocev reference teaches an apparatus, comprising:
prefetch table storage circuitry (e.g. MPT 200; and paragraph 15, where the system 100 includes multiple prefetch engines (PEs) 110, e.g., one for each device that reads data from the memory 114) to store a prefetch table comprising entries corresponding to memory address regions and comprising access count indicators indicative of numbers of accesses to corresponding memory address regions and stream distance indicators having more than two stream distance indicating states, (paragraph 15, where a memory prefetch table (MPT) 200 is illustrated that includes multiple of the PEs 110, which each maintain information for tracking strides for a different address stream. The MPT 200 may include, for example, eight PEs each of which include a current address field, a previous stride field, a current stride field, and a confidence counter field for a respective tracked address stream)
wherein a respective stream distance indicator of a respective entry is indicative of a respective stream distance between a respective memory address region corresponding to the respective entry and a respective root memory address region, (paragraph 15, where MPT 200 may include, for example, eight PEs each of which include a current address field, a previous stride field, a current stride field, and a confidence counter field for a respective tracked address stream) wherein the respective root memory address region corresponds to a respective root entry of the prefetch table having a respective access count indicator indicating a number of accesses meeting a stream root detection threshold. (paragraph 19, where in decision block 322, the PE 110 determines whether the confidence counter is greater than a threshold (e.g., ten). If the confidence counter is not greater than the threshold in block 322, control transfers to block 330. If the confidence counter is greater than the threshold in block 322, control transfers to block 328, where the PE 110 prefetches data for the tracked thread, based on the current address and the detected stride. For example, the PE 110 may prefetch, for the tracked thread, data from the memory at a next address in the memory that corresponds to a sum of a current address of the tracked thread and a next stride or a sum-of-strides included in the detected stride pattern)
With respect to claim 2, the Kocev reference teaches the apparatus of claim 1, wherein a first stream distance indicator of a first entry is indicative of a number of contiguous memory regions from a first root memory address region to a first memory address region corresponding to the first entry. (paragraph 12, where the term "stride" means a change in an address between consecutive reads. For example, if a current read address is `100` and a next read address is `101` then the stride is `+1`. As another example, if a current read address is `105` and a next read address is `101` then the stride is `-4`)
With respect to claim 3, the Kocev reference teaches the apparatus of claim 1, wherein a first access count indicator of a first entry is indicative of a number of unique accesses to cache-lines having addresses falling within a first memory address region corresponding to the first entry. (paragraph 19, where in decision block 322, the PE 110 determines whether the confidence counter is greater than a threshold (e.g., ten). If the confidence counter is not greater than the threshold in block 322, control transfers to block 330. If the confidence counter is greater than the threshold in block 322, control transfers to block 328, where the PE 110 prefetches data for the tracked thread, based on the current address and the detected stride. For example, the PE 110 may prefetch, for the tracked thread, data from the memory at a next address in the memory that corresponds to a sum of a current address of the tracked thread and a next stride or a sum-of-strides included in the detected stride pattern)
With respect to claim 4, the Kocev reference teaches the apparatus of claim 1, wherein a first stream distance indicator is to indicate a first stream distance of a first entry based on a second stream distance indicated by a second stream distance indicator of a second entry corresponding to a second memory address region adjacent to a first memory address region corresponding to the first entry. (paragraph 15, where MPT 200 may include, for example, eight PEs each of which include a current address field, a previous stride field, a current stride field, and a confidence counter field for a respective tracked address stream)
With respect to claim 5, the Kocev reference teaches the apparatus of claim 4, wherein the first stream distance indicator is to indicate the first stream distance based on an access count indicated by a second access count indicator of the second entry not meeting the stream root detection threshold. (paragraph 19, where in decision block 322, the PE 110 determines whether the confidence counter is greater than a threshold (e.g., ten). If the confidence counter is not greater than the threshold in block 322, control transfers to block 330. If the confidence counter is greater than the threshold in block 322, control transfers to block 328, where the PE 110 prefetches data for the tracked thread, based on the current address and the detected stride. For example, the PE 110 may prefetch, for the tracked thread, data from the memory at a next address in the memory that corresponds to a sum of a current address of the tracked thread and a next stride or a sum-of-strides included in the detected stride pattern)
With respect to claim 6, the Kocev reference teaches the apparatus of claim 4, wherein the first stream distance indicator is to indicate the first stream distance based on the second stream distance indicator indicating a second stream distance less than a maximum value. (paragraph 19, where in decision block 322, the PE 110 determines whether the confidence counter is greater than a threshold (e.g., ten). If the confidence counter is not greater than the threshold in block 322, control transfers to block 330. If the confidence counter is greater than the threshold in block 322, control transfers to block 328, where the PE 110 prefetches data for the tracked thread, based on the current address and the detected stride. For example, the PE 110 may prefetch, for the tracked thread, data from the memory at a next address in the memory that corresponds to a sum of a current address of the tracked thread and a next stride or a sum-of-strides included in the detected stride pattern)
With respect to claim 7, the Kocev reference teaches the apparatus of claim 4, wherein the first stream distance indicator is to indicate the first stream distance based on the first stream distance being less than a preexisting distance indicated by a preexisting first stream distance indicator of the first entry. (paragraph 19, where in decision block 322, the PE 110 determines whether the confidence counter is greater than a threshold (e.g., ten). If the confidence counter is not greater than the threshold in block 322, control transfers to block 330. If the confidence counter is greater than the threshold in block 322, control transfers to block 328, where the PE 110 prefetches data for the tracked thread, based on the current address and the detected stride. For example, the PE 110 may prefetch, for the tracked thread, data from the memory at a next address in the memory that corresponds to a sum of a current address of the tracked thread and a next stride or a sum-of-strides included in the detected stride pattern)
With respect to claim 8, the Kocev reference teaches the apparatus of claim 1, wherein a first stream distance indicator is to indicate a first stream distance of a first entry based on the access count indicator of a first root entry meeting the stream root detection threshold, wherein a first root memory address region corresponding to the first root entry is adjacent to a first memory address region corresponding to the first entry. (paragraph 15, where MPT 200 may include, for example, eight PEs each of which include a current address field, a previous stride field, a current stride field, and a confidence counter field for a respective tracked address stream; and paragraph 12, where the stride pattern is detected based upon whether sums of a current stride and a previous stride are equal for a number of consecutive reads during a learning mode.)
With respect to claim 9, the Kocev reference teaches the apparatus of claim 1, wherein a first entry comprises a first access count indicator meeting the stream root detection threshold and a first stream distance indicator to indicate a first stream distance of the first entry to a first root entry. (paragraph 15, where MPT 200 may include, for example, eight PEs each of which include a current address field, a previous stride field, a current stride field, and a confidence counter field for a respective tracked address stream)
With respect to claim 10, the Kocev reference teaches the apparatus of claim 1, wherein a stream distance indicator of a first root entry comprises a stream distance indicating state indicative of zero stream distance. (paragraph 13, where in order for a read from memory to "match" one or more tracked threads a new address associated with the read is required to be within some predetermined .+-. range of an address stored in a PE)
With respect to claim 11, the Kocev reference teaches the apparatus of claim 1, wherein entries of the prefetch table comprise stream direction indicators, and a first stream direction indicator of a first entry is indicative of a first stream direction from a first root memory address region of a first root entry to a first memory address region corresponding to the first entry. (paragraph 13, where in order for a read from memory to "match" one or more tracked threads a new address associated with the read is required to be within some predetermined .+-. range of an address stored in a PE)
With respect to claim 12, the Kocev reference teaches the apparatus of claim 11, wherein a first stream distance indicator of the first entry is to indicate a first stream distance based on a second stream distance indicated by a second stream distance indicator and a second stream direction indicator of a second entry, the second entry corresponding to a second memory address region adjacent to the first memory address region corresponding to the first entry. (paragraph 15, where MPT 200 may include, for example, eight PEs each of which include a current address field, a previous stride field, a current stride field, and a confidence counter field for a respective tracked address stream; and paragraph 13, where in order for a read from memory to "match" one or more tracked threads a new address associated with the read is required to be within some predetermined .+-. range of an address stored in a PE)
With respect to claim 13, the Kocev reference teaches the apparatus of claim 12, wherein: a third entry of the prefetch table comprises a third stream direction indicator indicative of a different stream direction than the second stream direction indicator and a third stream distance indicator indicative of a third stream distance from a third memory address region to a second root memory address region of a second root entry, the third memory address region being adjacent to the first memory address region; and the first stream distance indicator of the first entry is based on the second stream distance being less than the third stream distance. (paragraph 15, where MPT 200 may include, for example, eight PEs each of which include a current address field, a previous stride field, a current stride field, and a confidence counter field for a respective tracked address stream; and paragraph 13, where in order for a read from memory to "match" one or more tracked threads a new address associated with the read is required to be within some predetermined .+-. range of an address stored in a PE)
With respect to claim 14, the Kocev reference teaches the apparatus of claim 1, further comprising: prefetch generation circuitry coupled to the prefetch control circuitry to initiate a prefetch operation associated with a first memory address region based on a stream distance value of a first entry corresponding to the first memory address region. (paragraph 15, where a memory prefetch table (MPT) 200 is illustrated that includes multiple of the PEs 110, which each maintain information for tracking strides for a different address stream. The MPT 200 may include, for example, eight PEs each of which include a current address field, a previous stride field, a current stride field, and a confidence counter field for a respective tracked address stream)
Claims 16-19 are the non-transitory computer-readable medium implementation of claims 1-14, and rejected under a similar rationale as shown in the rejections above.
Claim 20 are the method medium implementation of claims 1-14, and rejected under a similar rationale as shown in the rejections above.
Claim Rejections - 35 USC ' 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kocev (US 20080288751) in view of Hansen (US 20040098548).
With respect to claim 15, the Kocev reference does not explicitly teach the
apparatus of claim 1, further comprising: execution circuitry comprising a 6x128 bit vector datapath.
The Hansen reference teaches it is conventional to have execution circuitry comprising a 6x128 bit vector datapath. (paragraph 158, where contents of a general register (128 bits) is used as a source operand, partitioned into a vector of symbols, and multiplied with the matrix, producing a vector of width up to 128 bits of symbols of twice the size of the source operand symbols; and paragraph 127, where it is clear that conditions which are indicated as sequential steps in FIGS. 8 and 9 above can be performed in parallel [i.e. a 6 x 128 bit vector datapath as claimed], reducing the delay for such wide operand checking)
It would have been obvious to a person of ordinary skill in the art before the claimed invention was effectively filed to modify the Kocev reference to have wherein execution circuitry comprising a 6x128 bit vector datapath, as taught by the Hansen reference.
The suggestion/motivation for doing so would have been to allow specifying of the size and shape of a wide operand. (Hansen, paragraph 158)
Therefore it would have been obvious to combine the Kocev and Hansen references for the benefits shown above to obtain the invention as specified in the claim.
4. ARGUMENTS CONCERNING NON-PRIOR ART REJECTIONS
Rejections - USC 101
Applicant's arguments (see pages 8-10 of the remarks) with respect to claims 1-20 have been considered, and are not persuasive. As noted in the rejections above, claim 1 (as an example) recites a judicial exception directed towards "mental processes" (i.e. data gathering/output) as it is an apparatus comprising a “prefetch table storage circuitry to store a prefetch table” comprising entries which corresponds to memory address regions and access count indicators and stream distance indicators. This judicial exception is not integrated into a practical application because it is merely performing a mental process as it is directed towards a “prefetch table storage circuitry to store a prefetch table comprising entries corresponding to memory address regions," "access count indicators indicative of numbers of accesses to corresponding memory address regions," and "stream distance indicators having more than two stream distance indicating states indicative of a respective stream distance between a respective memory address region and a respective root memory address region," where the root entry memory region corresponds to an entry based on a "stream root detection threshold." Thus, the claimed invention is merely reciting a table comprising entries which corresponds to memory address regions and access count indicators and stream distance indicators, and a generic “prefetch table storage circuitry” which does not add significantly more to the exception. Further, as noted in MPEP 2106.04(a)(2), Section III (Mental Processes), “The courts consider a mental process (thinking) that "can be performed in the human mind, or by a human using a pen and paper" to be an abstract idea”, which is analogous in this claimed invention. Therefore, the Applicant’s arguments are not considered persuasive for the reasons set forth above.
5. ARGUMENTS CONCERNING PRIOR ART REJECTIONS
Rejections - USC 102/103
Applicant's arguments (see pages 11-16 of the remarks) with respect to claims 1-20 have been considered but are not persuasive.
Firstly, in response to applicant's argument (see page 12) that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., “stream distance indicators” and that it “represents how far a memory-access stream has moved relative to one or more memory address regions”) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). As noted above, the Applicant argues that stream distance indicators “represents how far a memory-access stream has moved relative to one or more memory address regions”, the claim does not require this and thus the Examiner contends the “tracking strides” as recited in paragraph 15 (where a memory prefetch table (MPT) 200 is illustrated that includes multiple of the PEs 110, which each maintain information for tracking strides for a different address stream. The MPT 200 may include, for example, eight PEs each of which include a current address field, a previous stride field, a current stride field, and a confidence counter field for a respective tracked address stream) meet the claim limitation.
Secondly, the Applicant argues (see pages 12-13) Kocev does not teach the limitations of "respective distance indicator of a respective entry is indicative of a respective stream distance between a respective memory address region corresponding to the respective entry and a respective root memory address region, wherein the respective root memory address region corresponds to a respective root entry of the prefetch table having a respective access count indicator indicating a number of accesses meeting a stream root detection threshold". The Kocev reference teaches (paragraph 19) in decision block 322, the PE 110 determines whether the confidence counter is greater than a threshold (e.g., ten). If the confidence counter is not greater than the threshold in block 322, control transfers to block 330. If the confidence counter is greater than the threshold in block 322, control transfers to block 328, where the PE 110 prefetches data for the tracked thread, based on the current address and the detected stride. For example, the PE 110 may prefetch, for the tracked thread, data from the memory at a next address in the memory that corresponds to a sum of a current address of the tracked thread and a next stride or a sum-of-strides included in the detected stride pattern. Thus, based on citations above, the confidence counter is compared to a threshold, and prefetches data for the tracked thread, based on the current address and the detected stride; and meets the limitation above as broadly and instantly claimed.
Also, in response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., “the respective root memory address region corresponds to a respective root entry of the prefetch table having a respective access count indicator indicating a number of accesses meeting a stream root detection threshold” which requires “distances between address regions or relationships between entries structured around a root entry”) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). As noted above, the Applicant argues Kovev does not teach “distances between address regions or relationships between entries structured around a root entry”, the claim does not require this and thus the Examiner contends the Kocev reference teaches limitation above as broadly and instantly claimed for the reasons set forth in the responses above.
The Examiner notes the arguments pertaining to obviousness (see pages 13-16 of the remarks) have been considered, but does not specifically argue how the combination of the Kocev and Hansen does not explicitly teach the limitations above. The Examiner notes the responses above on how the limitations are taught.
6. CLOSING COMMENTS
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PRASITH THAMMAVONG whose telephone number is (571) 270-1040. The examiner can normally be reached Monday - Friday 12-8 PM EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Arpan Savla can be reached on (571) 272-1077. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PRASITH THAMMAVONG/
Primary Examiner, Art Unit 2137
Prosecution Insights