Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 1/23/2026 has been entered.
Response to Arguments
Applicant's arguments filed 1/23/2026 have been fully considered but they are not persuasive. On pages 12-14, Applicant alleges that the previously cited reference Lucarelli (US Publication No. 2020/0119748) fails to disclose “coupling… measured qubits to other qubits.” Examiner respectfully disagrees. The measured ancilla qubits in the Lucarelli prior art are considered to be both the measure qubits and the syndrome qubits of claim 1. This is because they are measured to obtain a syndrome (see para. 88 of Lucarelli: “the logical parity syndrome is obtained through measurement 156 of each ancilla block.” As shown in fig. 10, these ancilla qubits (considered to be measurement and syndrome qubits) are coupled to each other via CNOT gates, therefore teaching “couple the syndrome qubits with measure qubits.”
Examiner’s Note
While the Examiner disagrees that the claims currently overcome the cited reference Lucarelli, the Examiner believes that further clarifying language could be added to distinguish the “measure qubits” and “syndrome qubits” of the instant application from the ancilla qubits of the Lucarelli reference, which would likely bring the application to allowance. Examiner respectfully recommends Applicant schedule an interview to discuss amendments that can be made to overcome the cited prior art.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-12, 14-33, and 42-47 are rejected under 35 U.S.C. 102a1 as being anticipated by Lucarelli (US Publication No. 2020/0119748).
Regarding claim 1, Lucarelli teaches:
A system comprising:
quantum hardware components of a quantum apparatus; (para. 34: Together, the quantum data plane 160 and the control and measurement plane 162 may be characterized as being quantum hardware components.)
one or more processors; (fig. 17: host processor 166)
memory storing machine executable instructions that when executed by the one or more processors, cause the quantum hardware components to:
construct at least one quantum circuit (para. 58: The logical parity encoder B (see FIG. 1) may construct a quantum circuit.)
to couple quantum codewords with syndrome qubits -(para. 59: For example, the logical parity encoder B (see FIG. 1) may construct the quantum circuit 130 from the resultant matrix Rm by coupling a number Nxn of the data qubits 102 to a number M of the ancilla qubits 106. And para. 4: data qubits represent the quantum codewords. And para. 88: the logical parity syndrome is obtained through measurement 156 of each ancilla block.)
based at least in part on at least one quantum check operator, and (Para. 58: the logical parity encoder B (see FIG. 1) may construct a quantum circuit 130 in accordance with the specification. And para. 55: the logical parity encoder B generates a specification from the binary matrix and the quantum check operator(s).)
to couple the syndrome qubits with measure qubits (para. 86: each ancilla qubit may be replaced by a block of ancilla qubits prepared in an entangled state and measured.) Measured ancilla qubits are measure qubits and syndrome qubits, because they are measured to obtain the logical parity syndrome. They are coupled together in an entangled state.
based at least in part on a parity-check code; and (para. 58: the logical parity encoder B may construct a quantum circuit 130 [including coupling measure ancilla qubits as a block in an entangled state] in accordance with the specification. And para. 55: the logical parity encoder B generates a specification from the binary matrix. And para. 97: The binary matrix may be implemented as a binary parity-check matrix [corresponding to a parity check code])
measure the measure qubits to determine whether any errors are present in the quantum codewords. (para. 41: the ancilla qubits are measured by the measurement apparatus C to obtain measurement data which is communicated… as measurement outcomes… the logical parity decoder D performs a logical parity decoding method 180 that uses the measurement outcomes to infer where errors (if any) occurred in the quantum codewords.)
Regarding claim 2, Lucarelli teaches the system of claim 1. Lucarelli further teaches:
wherein the at least one quantum check operator is associated with a quantum error correcting code. (para. 72: a quantum error correcting code may specific one or more quantum check operators for detecting Pauli-X type errors and a distinct set of one or more quantum check operators for detecting Pauli-Z type errors.)
Regarding claim 3, Lucarelli teaches the system of claim 1. Lucarelli further teaches:
Wherein the parity-check code is a classical error correcting code (para. 53: the binary matrix may be implemented as a binary parity-check matrix [associated with a parity-check code]. And para. 51: The binary matrix is based at least in part on a classical error correcting code.)
Regarding claim 4, Lucarelli teaches the system of claim 1. Lucarelli further teaches:
wherein the machine executable instructions, when executed by the one or more processors, cause the system to:
obtain a specification based at least in part on the parity-check code, wherein a portion of the at least one quantum circuit that is to couple the [ancilla] qubits with the measure qubits is constructed in accordance with the specification. (para. 55: logical parity encoder B generates a specification from the binary matrix. And para. 53: the binary matrix may be implemented as a binary parity-check matrix [associated with a parity-check code]. And para. 86: each ancilla qubit may be replaced by a block of ancilla qubits prepared in an entangled state and measured. [Measured ancilla qubits are measure qubits and ancilla qubits, a block of qubits in an entangled state are coupled together] And para. 58: the logical parity encoder B may construct a quantum circuit 130 [including coupling measure ancilla qubits as a block in an entangled state] in accordance with the specification.
Regarding claim 5, Lucarelli teaches the system of claim 4. Lucarelli further teaches:
Wherein the parity-check code comprises a parity-check matrix, and (para. 97: a parity-check matrix corresponding to the chose parity-check code 302.)
Obtaining the specification comprises determining a Kronecker product of the parity-check matrix and an identity matrix. (para. 53: the binary matrix may be implemented as a binary parity-check matrix [associated with a parity-check code]. And para 53: The parity-check matrix HL may be expressed in systematic form HL = [I PL] with the MxK dimensional sub-parity-check matrix PL and MxM identity matrix I. And para. 55: The specification may be based at least in part on a resultant matrix that is a matrix Kronecker product of the binary matrix [an identity matrix and a sub-parity-check matrix] and a binary representation of the quantum check operator(s).)
Regarding claim 6, Lucarelli teaches the system of claim 4. Lucarelli further teaches:
for use with the at least one quantum check operator comprising a plurality of quantum check operators, (para. 42: measuring multiple quantum check operators)
wherein the specification is obtained based at least in part on a first binary matrix that is based at least in part on the parity-check code, (para. 55: logical parity encoder B generates a specification from the binary matrix. And para. 53: the binary matrix may be implemented as a binary parity-check matrix [associated with a parity-check code].)
and the machine executable instructions, when executed by the one or more processors, cause the one or more processors to: form a second binary matrix comprising binary versions of the plurality of quantum check operators; (para. 55: a binary representation of the quantum check operators (represented by the variable S))
obtain a logical parity configuration matrix by determining a Kronecker product of the first and second binary matrices; (para. 56: the logical parity encoder B may be configured to couple the data qubits 102 encoded as the quantum codewords 104 to the ancilla qubits 106 according to the resultant matrix RM formed by the Kronecker product of the parity-check matrix HL and the variable S (which represents the quantum check operators).)
and use the logical parity configuration matrix to infer whether any errors are present in the quantum codewords. (para. 68: the logical parity decoder D uses configuration data and the measurement outcomes to identify a location of an error in the data qubits 102. The configuration data includes the quantum check operator(s) and the binary matrix that were used by the logical parity encoder B to specify which of the ancilla qubits were coupled to which of the data qubits.) In the embodiment outlined in para. 56, the configuration data would be the resultant matrix RM.
Regarding claim 7, Lucarelli teaches the system of claim 4. Lucarelli further teaches:
for use with the at least one quantum check operator comprising one or more Pauli-X operators and one or more Pauli-Z operators, (para. 72: a quantum error correcting code may specify one or more quantum check operators for detecting Pauli-X type errors and a distinct set of one or more quantum check operators for detecting Pauli-Z type errors.)
wherein the specification is to be obtained based at least in part on a first binary matrix that is based at least in part on the parity-check code, (para. 55: logical parity encoder B generates a specification from the binary matrix. And para. 53: the binary matrix may be implemented as a binary parity-check matrix [associated with a parity-check code].)
and the machine executable instructions, when executed by the one or more processors, cause the one or more processors to: define a second binary matrix comprising a first sub-matrix representing the one or more Pauli-X operators and a second sub-matrix representing the one or more Pauli-Z operators; (para. 72: a quantum error correcting code may specify one or more quantum check operators for detecting Pauli-X type errors and a distinct set of one or more quantum check operators for detecting Pauli-Z type errors. And para. 55: a binary representation of the quantum check operators (represented by the variable S))
define a logical parity configuration matrix based at least in part on a first Kronecker product of the first binary matrix and the first sub-matrix and a second Kronecker product of the first binary matrix and the second sub-matrix; (para. 72: a quantum error correcting code may specify one or more quantum check operators for detecting Pauli-X type errors and a distinct set of one or more quantum check operators for detecting Pauli-Z type errors. And para. 56: the logical parity encoder B may be configured to couple the data qubits 102 encoded as the quantum codewords 104 to the ancilla qubits 106 according to the resultant matrix RM formed by the Kronecker product of the parity-check matrix HL and the variable S (which represents the quantum check operators).)
and use the logical parity configuration matrix to infer whether any errors are present in the quantum codewords. (para. 68: the logical parity decoder D uses configuration data and the measurement outcomes to identify a location of an error in the data qubits 102. The configuration data includes the quantum check operator(s) and the binary matrix that were used by the logical parity encoder B to specify which of the ancilla qubits were coupled to which of the data qubits.) In the embodiment outlined in para. 56, the configuration data would be the resultant matrix RM.
Regarding claim 8, Lucarelli teaches the system of claim 1. Lucarelli further teaches:
wherein the machine executable instructions, when executed by the one or more processors, cause the quantum hardware components to: obtain a logical parity syndrome by the measuring of the measure qubits; (para. 41: the ancilla qubits are measured by the measurement apparatus C to obtain measurement data which is communicated… as measurement outcomes… The resulting binary valued measurement outcomes (referred to as “logical parity syndrome” in the following).)
and the machine executable instructions, when executed by the one or more processors, cause the one or more processors to determine the quantum codewords contain at least one error when the logical parity syndrome comprises a non-zero value. (para. 94: If, on the other hand, the full logical parity syndrome 210 is non-zero, the logical parity decoder D determines, in decision block 214, that one or more errors are present in the quantum codewords 206.)
Regarding claim 9, Lucarelli teaches the system of claim 1. Lucarelli further teaches:
wherein the machine executable instructions, when executed by the one or more processors, cause the quantum hardware components to: obtain a logical parity syndrome by the measuring of the measure qubits; (para. 41: the ancilla qubits are measured by the measurement apparatus C to obtain measurement data which is communicated… as measurement outcomes… The resulting binary valued measurement outcomes (referred to as “logical parity syndrome” in the following).)
and the machine executable instructions, when executed by the one or more processors, cause the one or more processors to determine the quantum codewords contain at least one error when the logical parity syndrome has a value of -1. (para. 94: If, on the other hand, the full logical parity syndrome 210 is non-zero, the logical parity decoder D determines, in decision block 214, that one or more errors are present in the quantum codewords 206.) -1 is a non-zero value and would be an obvious choice since it is in the range of non-zero values.
Regarding claim 10, Lucarelli teaches the system of claim 1. Lucarelli further teaches:
wherein the machine executable instructions, when executed by the one or more processors, cause the quantum hardware components to use data qubits to create the quantum codewords; (para. 38: the quantum encoder A receives the plurality of data qubits 102 and produces a plurality of quantum codewords 104.)
and the machine executable instructions, when executed by the one or more processors, cause the one or more processors to apply at least one corrective action to any of the data qubits associated with an error when it is determined that one or more errors are present in the quantum codewords. (para. 94: the error locations are passed to the control hardware implementing the corrective actions to correct one or more errors in the data qubits of the quantum codewords 206.)
Regarding claim 11, Lucarelli teaches the system of claim 1. Lucarelli further teaches:
wherein the quantum codewords were created using data qubits, (para. 38: the quantum encoder A receives the plurality of data qubits 102 and produces a plurality of quantum codewords 104.)
the machine executable instructions, when executed by the one or more processors, cause the quantum hardware components to obtain measurement outcomes based at least in part on the measuring of the measure qubits,
and the machine executable instructions, when executed by the one or more processors, cause the one or more processors to use the measurement outcomes to identify locations of any errors present in the data qubits. (para. 41: the ancilla qubits are measured by the measurement apparatus C to obtain measurement data which is communicated… as measurement outcomes… the logical parity decoder D performs a logical parity decoding method 180 that uses the measurement outcomes to infer where errors (if any) occurred in the quantum codewords.)
Regarding claim 12, Lucarelli teaches the system of claim 1. Lucarelli further teaches:
wherein the at least one quantum circuit is to couple the quantum codewords with the syndrome qubits after the at least one quantum circuit is to couple the syndrome qubits with the measure qubits. (para. 86: The logical parity encoder B constructs a quantum circuit by coupling the data qubits to the ancilla blocks.) This implies that the ancilla blocks have been formed (by coupling measured syndrome qubits to other measured syndrome qubits) prior to coupling the quantum codewords with the syndrome qubits.
Regarding claim 14, Lucarelli teaches the system of claim 1. Lucarelli further teaches:
wherein the at least one quantum check operator comprises at least one non-Calderbank-Shor-Steane ("CSS") quantum check operator. (para. 48: logical parity encoder B and logical parity decoder D may be configured to operate with a variety of quantum error detecting an quantum error correcting codes, including as non-limiting examples, the Calderbank-Shor-Steane (“CSS”) codes, and [non-CSS] codes.)
Regarding claim 15, Lucarelli teaches:
A system comprising: quantum hardware components of a quantum apparatus; (para. 34: the quantum data plane and the control and measurement plane may be characterized as being quantum hardware components)
one or more processors; (fig. 17: host processor 166)
memory storing machine executable instructions that when executed by the one or more processors, cause the quantum hardware components of the quantum apparatus to: couple at least one qubit with at least one syndrome qubit based at least in part on at least one quantum check operator; (para. 60: couple each of selected ones of the data qubits 102 to one or more of the ancilla qubits 106 in accordance with the couplings indicated in the specification. And para. 55: generates a specification from the binary matrix and the quantum check operator(s).)
couple the at least one syndrome qubit with at least one measure qubit based at least in part on a specification determined based at least in part on a parity- check code; (para. 86: each ancilla qubit may be replaced by a block of ancilla qubits prepared in an entangled state and measured. [Measured ancilla qubits are measure qubits and syndrome qubits, because ancilla qubits are measured to obtain syndromes. A block of qubits in an entangled state are coupled together.] And para. 58: the logical parity encoder B may construct a quantum circuit 130 [including coupling measure ancilla qubits as a block in an entangled state] in accordance with the specification. And para. 55: the logical parity encoder B generates a specification from the binary matrix. And para. 97: The binary matrix may be implemented as a binary parity-check matrix [corresponding to a parity check code])
and measure the at least one measure qubit to determine whether any errors are present in at least one quantum state of the at least one qubit. (para. 41: the ancilla qubits are measured by the measurement apparatus C to obtain measurement data which is communicated… as measurement outcomes… the logical parity decoder D performs a logical parity decoding method 180 that uses the measurement outcomes to infer where errors (if any) occurred in the quantum codewords.)
Regarding claim 16, Lucarelli teaches the system of claim 15. Lucarelli further teaches:
Wherein the at least one qubit and the at least one syndrome qubit have noisy resource states. (para. 99: A number of noisy resource states 306 are output of a previous round of quantum state distillation)
Regarding claim 17, Lucarelli teaches the system of claim 15. Lucarelli further teaches:
wherein the at least one syndrome qubit comprises a plurality of syndrome qubits coupled to define at least one block of coupled syndrome qubits. (para. 86: each ancilla qubit may be replaced by a block of ancilla qubits prepared in an entangled state and measured. [Measured ancilla qubits are measure qubits and syndrome qubits, a block of qubits in an entangled state are coupled together.])
Regarding claim 18, Lucarelli teaches the system of claim 15. Lucarelli further teaches:
wherein the machine executable instructions, when executed by the one or more processors, cause the quantum hardware components to: discard any of the at least one qubit having the at least one quantum state determined to include at least one error. (para. 95: quantum states are discarded if one or more errors are detected)
Regarding claim 19, Lucarelli teaches the system of claim 15. Lucarelli further teaches:
wherein the machine executable instructions, when executed by the one or more processors, cause the quantum hardware components to obtain a logical parity syndrome by the measuring the at least one measure qubit, (para. 41: the ancilla qubits are measured by the measurement apparatus C to obtain measurement data which is communicated… as measurement outcomes (referred to as a “logical parity syndrome” in the following).
and the machine executable instructions, when executed by the one or more processors, cause the one or more processors to determine the at least one quantum state includes one or more errors when the logical parity syndrome comprises a non- zero value. (para. 94: If, on the other hand, the full logical parity syndrome 210 is non-zero, the logical parity decoder D determines, in decision block 214, that one or more errors are present in the quantum codewords 206.)
Regarding claim 20, Lucarelli teaches the system of claim 15. Lucarelli further teaches:
wherein the machine executable instructions, when executed by the one or more processors, cause the quantum hardware components to join any of the at least one quantum state determined not to include at least one error to produce at least one higher fidelity resource state. (para 95: states with no errors, as determined by the logical parity decoder D, are joined by an unencoding procedure to produce a higher fidelity resource state.)
Regarding claim 21, Lucarelli teaches the system of claim 15. Lucarelli further teaches:
wherein the at least one quantum check operator is associated with a quantum error correcting code. (para. 72: a quantum error correcting code may specific one or more quantum check operators for detecting Pauli-X type errors and a distinct set of one or more quantum check operators for detecting Pauli-Z type errors.)
Regarding claim 22, Lucarelli teaches the system of claim 15. Lucarelli further teaches:
wherein the parity-check code is a classical error correcting code. (para. 53: the binary matrix may be implemented as a binary parity-check matrix [associated with a parity-check code]. And para. 51: The binary matrix is based at least in part on a classical error correcting code.)
Regarding claim 23, Lucarelli teaches the system of claim 15. Lucarelli further teaches:
wherein the specification is obtained based at least in part on a binary matrix that is based at least in part on the parity-check code. (para. 55: logical parity encoder B generates a specification from the binary matrix. And para. 53: the binary matrix may be implemented as a binary parity-check matrix [associated with a parity-check code].)
Regarding claim 24, Lucarelli teaches the system of claim 15. Lucarelli further teaches:
wherein the parity-check code comprises a parity-check matrix, and the machine executable instructions, when executed by the one or more processors, cause the one or more processors to obtain the specification by determining a Kronecker product of the parity-check matrix and an identity matrix. (para. 53: the binary matrix may be implemented as a binary parity-check matrix [associated with a parity-check code]. And para 53: The parity-check matrix HL may be expressed in systematic form HL = [I PL] with the MxK dimensional sub-parity-check matrix PL and MxM identity matrix I. And para. 55: The specification may be based at least in part on a resultant matrix that is a matrix Kronecker product of the binary matrix [an identity matrix and a sub-parity-check matrix] and a binary representation of the quantum check operator(s).)
Regarding claim 25, Lucarelli teaches the system of claim 15. Lucarelli further teaches:
wherein the machine executable instructions, when executed by the one or more processors, cause the quantum hardware components to: use the at least one quantum check operator to construct a first portion of a quantum circuit, the first portion to couple the at least one qubit with the at least one syndrome qubit; and use the specification to construct a second portion of the quantum circuit, the second portion to couple the at least one syndrome qubit with the at least one measure qubit. (para. 86: each ancilla qubit is replaced with an ancilla block using multiple ancilla qubits that may be prepared in an entangled state. [ancilla qubits are measure qubits and syndrome qubits, and a block of ancilla qubits in an entangled state is coupling at least one syndrome qubit with at least one measure qubits. This constitutes the second portion of the quantum circuit] … the logical parity encoder B, couples each of the data qubits to an ancilla block [coupling at least one qubit with at least one syndrome qubit. This constitutes the first portion of the quantum circuit].)
Regarding claim 26, Lucarelli teaches the system of claim 25. Lucarelli further teaches:
wherein the quantum circuit comprises Pauli-X gates positioned between the first portion and the second portion. (fig. 8: quantum check operator K2 between ancilla qubit and where ancilla is coupled to data qubit. And para. 86: each ancilla qubit is replaced with an ancilla block. And para. 72: a quantum error correcting code may specific one or more quantum check operators for detecting Pauli-X type errors and a distinct set of one or more quantum check operators for detecting Pauli-Z type errors.)
Regarding claim 27, Lucarelli teaches the system of claim 25. Lucarelli further teaches:
wherein coupling the at least one qubit with the at least one syndrome qubit produces a plurality of coupled qubits comprising a plurality of distillation blocks each comprising multiple coupled qubits, and the machine executable instructions, when executed by the one or more processors, cause the quantum hardware components to:
discard one or more of the plurality of distillation blocks to leave at least one distillation block when an error is found in a quantum state of any of the multiple coupled qubits of the one or more distillation blocks; (para. 95: quantum states are discarded if one or more errors are detected) A quantum state is comprised of a plurality of qubits, and is used for state distillation, therefore is considered to be a distillation block.
construct a new quantum circuit to couple the multiple coupled qubits of the at least one distillation block with multiple measure qubits; (para. 100: the logical parity encoder B directs the quantum computer to couple the N*n resource states [each being a distillation block, comprising multiple coupled qubits] to the ancilla qubits.)
and measure the multiple measure qubits to determine whether any errors are present in one or more states of the multiple coupled qubits of the at least one distillation block. (para. 101: In block 308, the ancilla qubits 304 are measured… to produce the binary valued logical parity syndrome. And para. 102: In block 314, the computing device implementing logical parity decoder D determines the type and location of any errors 316 present in the resource states from the full logical parity syndrome 310.)
Regarding claim 28, Lucarelli teaches the system of claim 27. Lucarelli further teaches:
wherein the new quantum circuit is constructed based on a new specification that has a size based at least in part on a size of the at least one distillation block. (para. 100: couple the N*n resource states 306 to the ancilla qubits 304 in the manner described previously and according to the resultant matrix RM described by equation 1. And para. 55: the specification is based at least in part on a resultant matrix (represented by RM) that is a Kronecker product of the binary matrix and a binary representation of quantum check operators.) The size of the binary matrix is directly related to the size of the distillation block, because it is based on the number of qubits. The specification is based on the binary matrix and so, the size of the specification in based on the binary matrix (based on the size of the distillation block).
Regarding claim 29, Lucarelli teaches the system of claim 27. Lucarelli further teaches:
wherein the new quantum circuit is constructed based on a new specification, and the machine executable instructions, when executed by the one or more processors, cause the one or more processors to: obtain the new specification based at least in part on the parity-check code. (para. 100: couple the N*n resource states 306 to the ancilla qubits 304 in the manner described previously and according to the resultant matrix RM described by equation 1. And Equation 1: the resultant matrix is equal to the Kronecker product of the parity check matrix H and a binary representation of the quantum check operator(s).)
Regarding claim 30, Lucarelli teaches the system of claim 25. Lucarelli further teaches:
wherein the at least one quantum check operator comprises at least one non-Calderbank-Shor-Steane ("CSS") quantum check operator. (para. 48: logical parity encoder B and logical parity decoder D may be configured to operate with a variety of quantum error detecting an quantum error correcting codes, including as non-limiting examples, the Calderbank-Shor-Steane (“CSS”) codes, and [non-CSS] codes.)
Regarding claim 31, Lucarelli teaches:
A system comprising:
at least one verification circuit of a quantum apparatus to couple multiple qubits with at least one [ancilla] qubit, (para. 103: verification circuit couples multiple-qubit entangled states to additional ancilla qubits.)
and to couple the at least one syndrome qubit with at least one measure qubit (para. 49: verification circuit for entangled state preparation. And para. 86:each ancilla qubit may be replaced by a block of ancilla qubits prepared in an entangled state) Ancilla qubits are considered to be measure qubits and syndrome qubits as they are measured to obtain a syndrome.
in accordance with a specification determined based at least in part on a parity-check matrix and an identity matrix, (And para. 58: the quantum circuit is constructed in accordance with the specification. And para. 55: the logical parity encoder B generates a specification from the binary matrix (represented by the variable H). And para. 53: the binary matrix (represented by the variable H) may be implemented as a parity-check matrix. The parity check matrix H may be expressed in systematic form H = [I PL] with the MxK dimensional sub-parity check matrix PL and MxM identity matrix I.)
the at least one verification circuit to be associated with a target multiple-qubit entangled state; (para. 103: multiple-qubit entangled states may be verified to be error free by specifying a verification circuit that couples the multiple-qubit entangled states.)
and a quantum decoder hardware component to measure the at least one measure qubit to determine which of the multiple qubits have the target multiple-qubit entangled state. (para. 108: logical parity decoder D determines the type and location of any errors 416 present in the multiple-qubit entangled states.)
Regarding claim 32, Lucarelli teaches the system of claim 31. Lucarelli further teaches:
wherein the quantum decoder hardware component is to discard any of the multiple qubits which do not have the target multiple-qubit entangled state. (para. 108discards any multiple-qubit entangled state containing an error as determined by the logical parity decoder D.) The target state is a state containing no-errors.
Regarding claim 33, Lucarelli teaches the system of claim 31. Lucarelli further teaches:
wherein one or more error free qubits of the multiple qubits are determined to have the target multiple-qubit entangled state, and the system further comprises: digital hardware components to cause the at least one verification circuit to use the one or more error free qubits as syndrome qubits. (para. 103: multiple-qubit entangled states… may be used as ancilla blocks… these entangled states may be verified to be error free before being used by any other process.)
Regarding claim 42, Lucarelli teaches the system of claim 1. Lucarelli further teaches:
Wherein the quantum codewords are coupled with the syndrome qubits before, the syndrome qubits are coupled with the measure qubits, and the measure qubits are measured after being coupled with the syndrome qubits. (see fig. 10: syndrome qubits (ancilla qubits) are coupled with the measure qubits via CNOT gates (for example, 150 and 152). This occurs before syndrome qubits (ancilla qubits) are coupled with measure qubits (other ancilla qubits) via CNOT gate (for example, in box 155). Box 156 is after this, and represents the measurement of each ancilla block (containing measurement qubits), as described in para. 88: the logical parity syndrome is obtained through measurement 156 of each ancilla block after decoding the ancilla preparation illustrated by a rectangle 155.)
Regarding claim 43, Lucarelli teaches the system of claim 1. Lucarelli further teaches:
Wherein the quantum hardware components comprise a logical syndrome compressor to couple the syndrome qubits with the measure qubits. (para. 86: logical parity encoder B and logical parity decoder B may be configured to use multiple-qubit ancilla to implement fault-tolerant syndrome extraction… each ancilla qubit is replaced with an ancilla block using multiple ancilla qubits that may be prepared in an entangled state.) Examiner notes that “logical syndrome compressor” is not a term well known in the art. Upon consultation of the instant specification, the term “logical syndrome compressor” is considered to be anything that couples measure qubits and syndrome qubits as described in pg. 7 lines 7-9: “the logical syndrome compressor B… may be implemented at least in part by software executing on the host processor 166,” and in pg. 8, lines 18-20: “the logical syndrome compressor B performs the logical syndrome compressor method 170 (see fig. 4), which couples each of the syndrome qubits 106 to one or more of the measure qubits 107.” Therefore, the logical parity encoder and decoder of Lucarelli is considered to be a logical syndrome compressor as they prepare an ancilla block in an entangled state.
Claims 44 and 46 correspond to claim 42, and are rejected accordingly.
Claims 45 and 47 correspond to claim 43, and are rejected accordingly.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Lucarelli in view Kandala (US Publication No. 20200175409).
Regarding claim 13, Lucarelli teaches the system of claim 1. Lucarelli further teaches:
Wherein the machine executable instructions, when executed by the one or more processors, cause the quantum hardware components to:
… couple the syndrome qubits with the … measure qubits (para. 86: each ancilla qubit may be replaced by a block of ancilla qubits prepared in an entangled state and measured.) Measured ancilla qubits are measure qubits and syndrome qubits, a block of qubits in an entangled state are coupled together.
However, Lucarelli fails to teach:
Reset the measure qubits to produce reset measure qubits;
In the analogous art of quantum computation, Kandala teaches:
Reset the measure qubits to produce reset measure qubits; (para. 9: resetting each qubit to a ground state.)
It would have been obvious to one of ordinary skill in the art, having the teachings of Lucarelli and Kandala before them before the effective filing date of the claimed invention, to incorporate resetting qubits taught by Kandala into the quantum computing system disclosed by Lucarelli, to allow for benefits such as maintaining qubit coherence (Kandala, para. 37).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JACK K BARNETT whose telephone number is (571)270-0431. The examiner can normally be reached M-Th 8-5, F 8-4 EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Mark Featherstone can be reached at 571-270-3750. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JACK KENSINGTON BARNETT/Examiner, Art Unit 2111
/MARK D FEATHERSTONE/Supervisory Patent Examiner, Art Unit 2111