►DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending in the application. Claims 13-20 are withdrawn from further consideration.
Election/Restrictions
Applicant’s election without traverse of claims 1-12 in the reply filed on 30 December 2025 is acknowledged.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
Acknowledgment is made of applicant’s Information Disclosure Statement(s) (IDS), Form PTO-1449, filed 28 February 2024. The information therein was considered.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
►Claim(s) 1-5 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shirakawa et al. (US 2020/0098432) (hereinafter, “Shirakawa”).
Re: claim 1, Shirakawa discloses in figs. 2-5 a semiconductor memory device comprising: a first semiconductor pillar (MP1); a second semiconductor pillar (MP9); a first string (fig. 5) provided on a first side of the first semiconductor pillar (side of MP1 coupled to 11-2), and including a plurality of first memory cells electrically connected in series (fig. 5); a second string (fig. 5) provided on a second side of the first semiconductor pillar (side of MP1 coupled to 11-3), and including a plurality of second memory cells electrically connected in series (fig. 5); a third string (fig. 5) provided on a first side of the second semiconductor pillar (side of MP9 coupled to 11-4), and including a plurality of third memory cells electrically connected in series (fig. 5); a fourth string (fig. 5) provided on a second side of the second semiconductor pillar (side of MP9 coupled to 11-3), and including a plurality of fourth memory cells electrically connected in series (fig. 5); a plurality of first word lines (including 11-2, 11-4, WLe0-WLe7, SU2), each of the first word lines electrically connected in common to one of the plurality of first memory cells and one of the plurality of third memory cells; a plurality of second word lines (including 11-3, WLo0-WLo7, SU1), each of the second word lines electrically connected in common to one of the plurality of second memory cells and one of the plurality of fourth memory cells; and a driver configured to supply different voltages to the first and second word lines during an erasing operation to erase data in the plurality of second memory cells and the plurality of fourth memory cells, wherein in the erasing operation, the driver supplies a first voltage higher than a reference voltage to the plurality of first word lines, and supplies the reference voltage to the plurality of second word lines (A recitation of the intended use of the claimed invention must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim. MPEP § 2114.).
Re: claim 2, Shirakawa discloses in figs. 2-5 the semiconductor memory device according to claim 1, further comprising: a third semiconductor pillar (MP3); a fourth semiconductor pillar (MP10); a fifth string (fig. 5) provided on a first side of the third semiconductor pillar (side of MP3 coupled to 11-6), and including a plurality of fifth memory cells electrically connected in series (fig. 5); a sixth string (fig. 5) provided on a second side of the third semiconductor pillar (side of MP3 coupled to 11-7), and including a plurality of sixth memory cells electrically connected in series (fig. 5); a seventh string (fig. 5) provided on a first side of the fourth semiconductor pillar (side of MP10 coupled to 11-6), and including a plurality of seventh memory cells electrically connected in series (fig. 5); an eighth string (fig. 5) provided on a second side of the fourth semiconductor pillar (side of MP10 coupled to 11-5), and including a plurality of eighth memory cells electrically connected in series (fig. 5); a plurality of third word lines (including 11-6, WLe0-WLe7, SU4), each of the third word lines electrically connected in common to one of the plurality of fifth memory cells and one of the plurality of seventh memory cells; and a plurality of fourth word lines (including 11-5, 11-7, SU3), each of the fourth word lines electrically connected in common to one of the plurality of sixth memory cells and one of the plurality of eighth memory cells, wherein in the erasing operation, the driver supplies the first voltage to the plurality of third word lines (A recitation of the intended use of the claimed invention must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim. MPEP § 2114.).
Re: claim 3, Shirakawa discloses in figs. 3-5 the semiconductor memory device according to claim 2, wherein in the erasing operation, the driver disconnects the plurality of fourth word lines from a voltage supply so that the third word lines are maintained in a floating state (A recitation of the intended use of the claimed invention must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim. MPEP § 2114.).
Re: claim 4, Shirakawa discloses in figs. 3-5 the semiconductor memory device according to claim 3, wherein a voltage of the fourth word lines increases to the first voltage during the erasing operation (A recitation of the intended use of the claimed invention must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim. MPEP § 2114.).
Re: claim 5, Shirakawa discloses in figs. 3-5 the semiconductor memory device according to claim 2, wherein the first, second, third, and fourth semiconductor pillars extend in a first direction and are aligned in a second direction that is orthogonal to the first direction, and the first, second, third, and fourth word lines are stacked in the first direction (fig. 5).
►Claim(s) 1 and 12 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Futatsuyama et al. (US 2018/0277565) (hereinafter, “Futatsuyama”).
Re: claim 1, Futatsuyama discloses in figs. 2-4 a semiconductor memory device comprising: a first semiconductor pillar (MP1); a second semiconductor pillar (MP2); a first string (fig. 2) provided on a first side of the first semiconductor pillar (side of MP1 coupled to 11-3), and including a plurality of first memory cells electrically connected in series (fig. 2); a second string (fig. 2) provided on a second side of the first semiconductor pillar (side of MP1 coupled to 11-4), and including a plurality of second memory cells electrically connected in series (fig. 2); a third string (fig. 2) provided on a first side of the second semiconductor pillar (side of MP2 coupled to 11-5), and including a plurality of third memory cells electrically connected in series (fig. 2); a fourth string (fig. 2) provided on a second side of the second semiconductor pillar (side of MP2 coupled to 11-6), and including a plurality of fourth memory cells electrically connected in series (fig. 2); a plurality of first word lines (including 11-3, 11-5, WLo0-WLo7), each of the first word lines electrically connected in common to one of the plurality of first memory cells and one of the plurality of third memory cells; a plurality of second word lines (including 11-4, 11-6, WLe0-WLe7), each of the second word lines electrically connected in common to one of the plurality of second memory cells and one of the plurality of fourth memory cells; and a driver configured to supply different voltages to the first and second word lines during an erasing operation to erase data in the plurality of second memory cells and the plurality of fourth memory cells, wherein in the erasing operation, the driver supplies a first voltage higher than a reference voltage to the plurality of first word lines, and supplies the reference voltage to the plurality of second word lines (A recitation of the intended use of the claimed invention must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim. MPEP § 2114.).
Re: claim 12, Futatsuyama discloses in figs. 2-5 the semiconductor memory device according to claim 1, wherein the first and second semiconductor pillars (MP1, MP2) extend in a first direction (Z-direction) and are aligned in a second direction (Y-direction) that is orthogonal to the first direction, and the first and second word lines (including 11-3, 11-5 and 11-4, 11-6) are stacked in the first direction (Z-direction) and each have finger portions (11-3, 11-5 and 11-4, 11-6) that extend in a third direction (X-direction) that is orthogonal to the first and second directions, and the first semiconductor pillar (MP1) is disposed in a first boundary region that is between one of the finger portions (11-3) of the first word line and one of the finger portions (11-4) of the second word line, and the second semiconductor pillar (MP2) is disposed in a second boundary region that is between another one of the finger portions (11-5) of the first word line and another one of the finger portions (11-6) of the second word line.
Allowable Subject Matter
Claims 6-11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The prior art of record fails to teach the claimed limitations in combination namely, as recited in claim 6, the semiconductor memory device according to claim 5, (including wherein the first, second, third and fourth semiconductor pillars are aligned in a second direction), further comprising: a plurality of dummy pillars extending in the first direction disposed in a boundary region that is between the second and third word lines in the second direction and extends in the first direction and a third direction that is orthogonal to the first and second directions; and as recited in claim 8, the semiconductor memory device according to claim 5 (including wherein the first, second, third and fourth semiconductor pillars are aligned in a second direction), further comprising: first and second bit lines extending in the second direction above the first, second, third, and fourth semiconductor pillars, wherein the first bit line is electrically connected to the second and third semiconductor pillars and the second bit line is electrically connected to the first and fourth semiconductor pillars.
Conclusion
The examiner has cited particular columns and line numbers in the references as applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. When responding to this office action, applicants are advised to provide the examiner with the line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALLISON BERNSTEIN whose telephone number is (571)272-9011. The examiner can normally be reached M-F 8AM-5PM.
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/ALLISON BERNSTEIN/Primary Examiner, Art Unit 2824 3/26/2026