DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicant’s amendment dated 06/15/2026, in which claim 1 was amended, claim 3 was cancelled, claims 9-16 were withdrawn, has been entered.
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d) to foreign application TW113100060 filed on 01/02/2024. The foreign application is not in English. The certified copy of the foreign priority application TW113100060 has been received.
Filing Dates for the Claims — All Claims Not Entitled to Priority Date
To be entitled to the filing date of the foreign priority application TW113100060 that is not in English, an English translation of the non-English language foreign application TW113100060 and a statement that the translation is accurate in accordance with 37 CFR 1.55 is required to perfect the claim for priority under 35 U.S.C. 119 (a)-(d). The foreign application must adequately support the claimed subject matter, meaning satisfy the written description and enablement requirements of 35 U.S.C. 112(a). See MPEP §§ 215 and 216. 37 C.F.R. 1.55(g)(3)(ii)-(iii). To demonstrate compliance with 35 U.S.C. 112(a), applicant should point to support for their claimed subject matter in their translations.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4-7 are rejected under 35 U.S.C. 103 as being unpatentable over Hwang et al. (US Pub. 20240274689), in view of Echigoya et al. (US Pub. 20160093691).
Regarding claims 1 and 5, Hwang et al. discloses in Fig. 1 a high electron mobility transistor, comprising:
a GaN substate [110 and 120][paragraph [0047], [0049], [0051]];
an AIGaN layer [134] on said GaN substrate [110 and 120][paragraph [0054], [0058]-[0059]];
a gate [138, 142, 146 and 150], comprising:
a first p-GaN layer [138] on said AIGaN layer [134][paragraph [0067]];
an etch stop layer [142] on said first p-GaN layer [138];
a second p-GaN layer [146] on said etch stop layer [142][paragraph [0077]]; and
an electrode layer [150] on said second p-GaN layer [146][paragraph [0078]]; and
a source [124] and a drain [128] respectively on said AlGaN layer [134] at two sides of said gate [138, 142, 146 and 150] in a first direction;
wherein a material of said etch stop layer [142] is AIGaN or AIN [paragraph [0058]-[0059], [0073]].
Huang et al. fails to disclose
wherein a width of said first p-GaN layer in said first direction is larger than a width of said second p-GaN layer in said first direction, so that said first p-GaN layer is provided with a ledge part protruding in said first direction, and sidewalls of said first p-GaN layer and said second p-GaN layer are flush at a side opposite to said ledge part, and said ledge part of said first p-GaN layer partially deplete a two-dimensional electron gas (2DEG) channel in said GaN substrate, and said 2DEG channel with reduced concentration is overlapped with said ledge part of said first p-GaN layer.
Echigoya et al. discloses in Fig. 32, Fig. 40, paragraph [0369], [0377]
wherein a width of said first p-GaN layer [44] or [64] in said first direction is larger than a width of said second p-GaN layer [45] or [71] in said first direction, so that said first p-GaN layer [44] or [64] is provided with a ledge part protruding in said first direction, sidewalls of said first p-GaN layer [44] or [64] and said second p-GaN layer [45] or [71] are flush at a side opposite to said ledge part.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Echigoya et al. into the method of Hwang et al. to include wherein a width of said first p-GaN layer in said first direction is larger than a width of said second p-GaN layer in said first direction, so that said first p-GaN layer is provided with a ledge part protruding in said first direction, and sidewalls of said first p-GaN layer and said second p-GaN layer are flush at a side opposite to said ledge part. The ordinary artisan would have been motivated to modify Hwang et al. in the above manner for the purpose of forming asymmetric gate structure to reduce contact resistance of the p-electrode so that it does not have an effect on the moving velocity of holes, improving the drain breakdown voltage, eliminating the occurrence of current collapse during switching and operate in high speed and further the loss is low [paragraph [0377]-[0382] of Echigoya et al.].
Incorporating said first p-GaN layer with a ledge part protruding in said first direction as suggested by Echigoya et al. into the device of Hwang et al. would result to “said ledge part of said first p-GaN layer partially deplete a two-dimensional electron gas (2DEG) channel in said GaN substrate, and said 2DEG channel with reduced concentration is overlapped with said ledge part of said first p-GaN layer.”
Regarding claim 2, Echigoya et al. discloses in Fig. 32,
wherein said ledge part protrudes toward said drain [47].
Regarding claim 4, Echigoya et al. discloses in Fig. 32
wherein a width of said electrode layer [49] in said first direction is smaller than said width of said second p-GaN layer [45] in said first direction.
Regarding claim 6, Hwang et al. discloses in paragraph [0078]
wherein a material of said electrode layer is TiN.
Regarding claim 7, Hwang et al. fails to explicitly disclose
wherein a thickness of said second p-GaN in a direction vertical to said GaN substrate is larger than a thickness of said first p-GaN in said direction vertical to said GaN substrate.
However, Hwang et al. suggests in paragraph [0076] “the second thickness T2 of the upper layer 146 may be less than, but not limited to, a first thickness T1 of the lower layer 138.”
One of ordinary skill in the art would have recognized the finite number of predictable solutions for a thickness of said second p-GaN with respect to a thickness of said first p-GaN: a thickness of said second p-GaN is less than/greater than/equal to a thickness of said first p-GaN. Absent unexpected results, it would have been obvious to try a thickness of said second p-GaN is greater than a thickness of said first p-GaN to yield suitable thickness of said first and second p-GaN with reasonable expectation of success.
In addition, Echigoya et al. discloses in Fig. 40, paragraph [0377], lines 14-23
wherein a thickness [40nm] of said second p-GaN [71] in a direction vertical to said GaN substrate is larger than a thickness [20nm] of said first p-GaN [64] in said direction vertical to said GaN substrate.
Consequently, the combination of Echigoya et al. and Hwang et al. discloses limitation of claim 7.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Hwang et al. (US Pub. 20240274689) in view of Echigoya et al. (US Pub. 20160093691) as applied to claim 1 above and further in view of Chou et al. (US Pub. 20230299169).
Regarding claim 8, Hwang et al. discloses in Fig. 1, paragraph [0047]-[0051]
wherein said GaN substrate [110 and 120] comprises a first GaN layer [110] and a GaN layer [120], and
said GaN layer [120] is between said first GaN layer [110] and said AlGaN layer [134].
Hwang et al. fails to disclose
wherein said first GaN layer comprises a carbon-doped GaN layer.
Chou et al. discloses in Fig. 1I, paragraph [0031]-[0032]
wherein said first GaN layer [a buffer layer] comprises a carbon-doped GaN layer [C-doped GaN buffer layer].
Chou et al. further discloses
said GaN layer [100] is between said carbon-doped GaN layer [buffer layer] and said AlGaN layer [102].
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Chou et al. into the method of Hwang et al. to include wherein said first GaN layer comprises a carbon-doped GaN layer, and said GaN layer is between said carbon-doped GaN layer and said AlGaN layer. The ordinary artisan would have been motivated to modify Hwang et al. in the above manner for the purpose of providing suitable material of said first GaN layer of the GaN substrate.
Response to Arguments
Applicant’s arguments with respect to claims 1-2, 4-8 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Overall, Applicant’s arguments are not persuasive. The claims stand rejected and the Action is made FINAL.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SOPHIA T NGUYEN whose telephone number is (571)272-1686. The examiner can normally be reached 9:00am -5:00 pm, Monday-Friday.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, BRITT D HANLEY can be reached at (571)270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SOPHIA T NGUYEN/Primary Examiner, Art Unit 2893
Prosecution Insights