DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-2 are rejected under 35 U.S.C. 103 as being unpatentable over Endo et al. (US 5,935,344) in view of Lee et al. (US 2016/0197204).
Regarding claim 1, Endo discloses a solar cell (abstract) comprising: a silicon substrate including a first surface and a second surface opposite to each other (7 in Fig. 3; C4/L44); a first doped layer disposed on the first surface (9 in Fig. 3) and in direct contact with the first surface (C7/L13-15 discloses layer 8 (between 7 and 9 in Fig. 3) may be eliminated); wherein the second doped layer extends to the side of the silicon substrate (10 in relation to 7 in Fig. 3), a doped type of the first doped layer is opposite to a doped type of the second doped layer (9 is p-type and 10 is n-type as depicted in Fig. 3); a first electrode (3 and 4 in Fig. 3) in direct contact with the first doped layer (9 in Fig. 3; a second electrode (3 and 5 in Fig. 3) in direct contact with the second doped layer (10 in Fig. 3); and an isolation trench penetrating the first doped layer along a thickness direction of the silicon substrate and surrounding the first electrode (1 in relation to 9 in Fig. 3).
Endo does not explicitly disclose a tunneling layer disposed on the second surface.
Lee discloses a photovoltaic element including a tunnel layer between an n-type crystalline semiconductor substrate and an n+ amorphous semiconductor layer (abstract; [0060] – [0062]; claim 12).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to include a tunnel layer, as disclosed by Lee, between the n-type crystalline semiconductor substrate and the n+ amorphous semiconductor layer of Endo, because as evidenced by Lee, the inclusion of a tunnel layer between a crystalline semiconductor substrate and an amorphous semiconductor layer of a photovoltaic element amounts to merely combining familiar elements according to known methods and does no more than yield predictable results. One of ordinary skill in the art at the time the invention was filed would have a reasonable expectation of success when including a tunnel layer between the substrate and a semiconductor layer of Endo based on the teaching of Lee.
Modified Endo discloses the tunneling layer extending to a side of the silicon substrate (modified Endo discloses a tunneling layer between 7 and 10 in Fig. 3 of Endo), wherein the tunneling layer covers a part of the side of the silicon substrate (modified Endo discloses a tunneling layer between 7 and 10 in Fig. 3 of Endo), the height of the tunneling layer on the side of the silicon substrate is less than a thickness of the silicon substrate (modified Endo discloses a tunneling layer between 7 and 10 in Fig. 3 of Endo; the height of 10 in Fig. 3 of Endo is less than the thickness of the substrate); the second doped layer covers a surface of the tunneling layer away from the silicon substrate (7 and 10 in relation to the tunneling layer of modified Endo).
While modified Endo does disclose the thickness of substrate 7 is 200 to 400 microns (Endo - C4/L46) and depicts a height of layer 10 on the side of the silicon substrate 7 in relation to the thickness of silicon substrate 7 (Endo - Fig. 3), modified Endo does not explicitly disclose the height of the tunneling layer on the side of the silicon substrate is equal to or greater than 0.1 microns.
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to form the tunneling layer of modified Endo on the side of the silicon substrate with a height which is equal to or greater than 0.1 microns because such a modification would have involved a mere change in the size (or dimension) of a component. A change in size (dimension) is generally recognized as being within the level of ordinary skill in the art. In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955). Where the only difference between the prior art and the claims is a recitation of relative dimensions of the claimed device, and the device having the claimed dimensions would not perform differently than the prior art device, the claimed device is not patentably distinct from the prior art device, Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984).
Regarding claim 2, modified Endo discloses all the claim limitations as set forth above. Endo further discloses a distance between the isolation trench and an edge of the first doped layer is less than 10 microns ~ 2000 microns (Figure 3 does not depict a distance between 1 and an edge of 9; it is noted that a distance of 0 is less than the claimed range of 10 microns ~ 2000 microns).
It is noted that with regard to the limitation “preset,” the limitation is directed to
the manner in which the device is made, and it is noted that said limitations are not given patentable weight in the product claims. Even though a product-by-process is defined by the process steps by which the product is made, determination of patentability is based on the product itself and does not depend on its method of production. In re Thorpe, 777 F.2d 695, 227 USPQ 964 (Fed. Cir. 1985).
Claims 5-7 are rejected under 35 U.S.C. 103 as being unpatentable over Endo et al. (US 5,935,344) in view of Lee et al. (US 2016/0197204) as applied to claim 1 above, and further in view of Lin et al. (US 2019/0221701).
Regarding claim 5, modified Endo discloses all the claim limitations as set forth above.
Modified Endo does not explicitly disclose a first passivation layer disposed on a surface of the first doped layer away from the silicon substrate.
Lin discloses a photovoltaic element including a passivation layer ([0014]; 106) between a doped amorphous silicon layer ([0014]; 104) and a TCO layer ([0014]; 108).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to include a passivation layer, as disclosed by Lin, on a surface of the first doped layer of modified Endo, because as taught by Lin, the passivation effect is improved and the short circuit current is increased so an overall efficiency of the solar cell can be improved ([0007]).
Additionally, as evidenced by Lin, the formation of a passivation layer between a doped amorphous silicon layer and a TCO layer in a photovoltaic device amounts to the use of a known material/component in the art for its intended purpose to achieve an expected result, and one of ordinary skill would have a reasonable expectation of success when forming a passivation layer between the doped amorphous silicon layer and TCO layer of modified Endo based on the teaching of Lin.
Regarding claim 6, modified Endo discloses all the claim limitations as set forth above. Modified Endo further discloses the first passivation layer covers a bottom side and a side of the isolation trench (modified Endo discloses a passivation layer between 3 and 9 in Fig. 3 of Endo; the disclosed passivation covers the sides of the isolation trench 1 because the limitation “covers” does not require direct physical contact with the respective side of isolation trench 1; additionally, the limitations “covers,” “bottom,” and “side” are not specific or limited to a particular spatial orientation of the device).
Regarding claim 7, modified Endo discloses all the claim limitations as set forth above.
Modified Endo does not explicitly disclose a second passivation layer disposed on a surface of the second doped layer away from the silicon substrate.
Lin discloses a photovoltaic element including a passivation layer ([0014]; 106) between a doped amorphous silicon layer ([0014]; 104) and a TCO layer ([0014]; 108).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to include a passivation layer, as disclosed by Lin, on a surface of the second doped layer of modified Endo, because as taught by Lin, the passivation effect is improved and the short circuit current is increased so an overall efficiency of the solar cell can be improved ([0007]).
Additionally, as evidenced by Lin, the formation of a passivation layer between a doped amorphous silicon layer and a TCO layer in a photovoltaic device amounts to the use of a known material/component in the art for its intended purpose to achieve an expected result, and one of ordinary skill would have a reasonable expectation of success when forming a passivation layer between the doped amorphous silicon layer and TCO layer of modified Endo based on the teaching of Lin.
Response to Arguments
Applicant's arguments filed 03/09/2026 have been fully considered but they are not persuasive. Specifically, Applicant argues that the metal electrode 4 of Endo is formed on the surface of conductive film 3 located on the front surface, and is not in direct contact with the p-doped amorphous silicon layer 9. Applicant argues the metal electrode 5 is formed on the surface of the conductive thin film 3 located on the back surface, and is not in direct contact with the n-doped amorphous silicon layer 10.
In response to Applicant’s argument, the amendment of claim 1 requiring direct contact between the first electrode and the first doped layer, and between the second electrode and the second doped layer is satisfied by the disclosure of Endo that states the conductive thin film 3 is a transparent conductive thin film such as indium tin oxide (ITO) (C5/L26-27), and the disclosure of 4 and 5 in Fig. 3 as metal electrodes. ITO is a TCO material, and an interpretation in which the structure of 3 and 4 of Endo is the first electrode, and the structure of 3 and 5 of Endo is the second electrode, is consistent with the limitations claimed and the disclosure of Endo with regard to the materials of 3, 4, and 5.
Applicant argues that the solar cell of the present invention is a TOPcon solar cell, and by contrast the photovoltaic element of Endo has a heterojunction constituted by combining a crystal semiconductor and an amorphous semiconductor. Applicant further argues that the stack of intrinsic amorphous silicon layer 8, amorphous silicon layers 9 and conductive thin film 3 is characteristic of HJT solar cells.
In response to Applicant’s argument, it is noted that the second embodiment in Endo (C6/L62) does not include intrinsic amorphous silicon layer 8. Further, even if Endo discloses an HJT cell, the structure disclosed by Endo satisfies the limitations of the solar cell claimed. It is noted that the features upon which applicant relies (i.e., features which differentiate a TOPCon solar cell from an HJT solar cell) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
Applicant argues that the p-doped amorphous silicon layer 9 on the side of the single crystal silicon substrate 7 is in direct contact with the n-doped amorphous silicon layer 10, and that this may result in a short circuit between the two film layers. Applicant further argues that the trench 1 may fail to completely interrupt the connection between the p-doped amorphous silicon layer 9 on the side and the p-doped amorphous silicon layer 9 on the front surface.
In response to Applicant’s argument, Applicant has not provided evidence supporting the assertion that the structure of Endo may result in a short circuit. It is noted that Applicant’s argument is not consistent with the conversion efficiency disclosed in Table 2 of Endo.
Applicant’s remaining arguments with respect to claims 1-2 and 5-7 have been considered but are moot because the remaining arguments are not directed to the current rejection(s).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TAMIR AYAD whose telephone number is (313) 446-6651. The examiner can normally be reached Monday - Friday, 8:30am - 5pm EST.
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/TAMIR AYAD/Primary Examiner, Art Unit 1726
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