Prosecution Insights
Last updated: May 29, 2026
Application No. 18/591,193

TRACKING ENERGY CONSUMPTION USING A BUCK-BOOSTING TECHNIQUE

Non-Final OA §103
Filed
Feb 29, 2024
Priority
Jul 12, 2013 — continuation of 9618545 +2 more
Examiner
ANDREWS, BRENT J
Art Unit
2858
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Texas Instruments Incorporated
OA Round
1 (Non-Final)
78%
Grant Probability
Favorable
1-2
OA Rounds
11m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 78% — above average
78%
Career Allowance Rate
244 granted / 313 resolved
+10.0% vs TC avg
Strong +28% interview lift
Without
With
+28.4%
Interview Lift
resolved cases with interview
Typical timeline
3y 2m
Avg Prosecution
11 currently pending
Career history
331
Total Applications
across all art units

Statute-Specific Performance

§101
0.4%
-39.6% vs TC avg
§103
92.6%
+52.6% vs TC avg
§102
2.8%
-37.2% vs TC avg
§112
3.2%
-36.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 313 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Information Disclosure Statement The information disclosure statement (IDS) submitted on 02/29/2024. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner. Claim Status Claims 11-30 are pending. Claim Rejections - 35 USC § 103 2. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. PNG media_image1.png 725 861 media_image1.png Greyscale 3. Claims 11-12, 14-15, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over ZHANG et al. (US 20130049626 A1) in view of NEWTON et al. (EP 0582813 A2). PNG media_image1.png 725 861 media_image1.png Greyscale 4. As to claim 11, ZHANG teaches a circuit device comprising: a buck energy transfer block (Fig. 1-6 Item 420b discloses booster converter in Paragraph [0071]) that includes: first and second inputs (Fig. 1-6 Item 421 & 422 discloses booster converter in Paragraph [0071]) configured to couple to a power supply (Fig. 1-6 Item 421 & 422 discloses two terminals coupled to the AC power supply in Paragraph [0071]); first and second outputs; and first and second switches (Fig. 1-6 Item 423 & 425); a set of boost energy transfer blocks (Fig. 1-6 Item 220 & 230 discloses boost and buck converter in Paragraph [0026 & 0030]) that each includes: third and fourth inputs, wherein: the third input is coupled to the first output of the buck energy transfer block (Fig. 1-6 Item 220 & 230 discloses boost and buck converter in Paragraph [0026 & 0030]).; and the fourth input is coupled to the second output of the buck energy transfer block (Fig. 1-6 Item 220 & 230 discloses boost and buck converter in Paragraph [0026 & 0030]).; and third (Fig. 1-6 Item 433) and fourth switches (Fig. 1-6 Item 435; and a controller (Fig. 1-6 Item 240 or 340 or 440 discloses controller respectively in Paragraph [0064]) coupled to the first energy transfer block and the set of boost energy transfer blocks (Fig. 1-6 Item 220 & 230 discloses boost and buck converter in Paragraph [0026 & 0030]).and configured such that switching (Fig. 1-6 Item 433) of the third and fourth switches (Fig. 1-6 Item 435of each of the set of boost energy transfer blocks (Fig. 1-6 Item 220 & 230 discloses boost and buck converter in Paragraph [0026 & 0030]).is aligned to a clock (Fig. 1-6 Item 240 discloses controller 240 provides pulses having a relatively high frequency, such as in the order of 100 KHz, in Paragraph [0027]). However ZHANG does not explicitly teach a set of energy transfer blocks coupled to the first energy transfer block that each include: However, NEWTON teaches a set of energy transfer blocks (Figs. 1 Item 5 discloses a set of energy transfer blocks) coupled to the first energy transfer block (Figs. 1 Item 4 discloses an energy transfer block): It would have been obvious to one skilled in the art before the effective filing date of the invention to modify a device for transferred electric energy in ZHANG to provide a set of energy transfer blocks by NEWTON in order to provide to a boost (step-up) voltage. 5. As to claim 12, ZHANG teaches the circuit device of claim 11, wherein the buck energy transfer block (Fig. 1-6 Item 420b discloses booster converter in Paragraph [0071]) includes: a first inductor (Fig. 1-6 Item 421) that includes a first terminal and a second terminal, wherein the second terminal is coupled to the first output of the buck energy transfer block (Fig. 1-6 Item 420b), wherein: the first switch (Fig. 1-6 Item 423) is coupled between the first input of the buck energy transfer block and the first terminal of the first inductor; and the second switch (Fig. 1-6 Item 425) is coupled between the second input of the buck energy transfer block (Fig. 1-6 Item 420b) and the first terminal of the first inductor; a capacitor (Fig. 1-6 Item 424) coupled between the second terminal of the first inductor and the second input of the buck energy transfer block (Fig. 1-6 Item 420b); and a first diode (Fig. 1-6 Item 426 or 427 or 232 discloses diode) coupled between the second input of the buck energy transfer block (Fig. 1-6 Item 420b) and the first terminal of the first inductor (Fig. 1-6 Item 421). 6. As to claim 14, ZHANG teaches the circuit device of claim 11, wherein the controller includes: a first control logic block (Fig. 1-6 Item 240 or 340 or 440 discloses controller respectively in Paragraph [0064]) coupled to the first energy transfer block (Fig. 1-6 Item 420b discloses booster converter in Paragraph [0071]) to control switching of the first switch (Fig. 1-6 Item 423) and the second switch (Fig. 1-6 Item 425); and a set of control logic blocks (Fig. 1-6 Item 440 discloses controller which can be one respectively for each block in Paragraph [0064]) that includes a respective block coupled to each of the set of energy transfer blocks (Fig. 1-6 Item 420B and 430 are energy transfer blocks) to control switching of the third and fourth switches of the respective energy transfer block (Fig. 1-6 Item 440 discloses controller changes the transistors 423, 425, 433 and 436 switches 1-4 in order to detect voltage levels in Paragraph [0064]). 7. As to claim 15, ZHANG teaches the circuit device of claim 14 further comprising a capacitor (Fig. 1-6 Item 424) that is coupled between the third and fourth outputs of each of the set of boost energy transfer blocks (Fig. 1-6 Item 420B). 8. As to claim 20, ZHANG teaches the circuit device of claim 11, wherein the controller (Fig. 1-6 Item 240 or 340 or 440 discloses controller respectively in Paragraph [0064]) is configured to cause a plurality of the third switches of the set of energy transfer blocks to be active concurrently (Fig. 1-6 Item 240 or 340 or 440 discloses controller 440 respectively provides first pulses to the first switch 433, and second pulses to the second switch 436, and respectively adjusts duty cycle of the first pulses and duty cycle of the second pulses to generate the output voltage VOUT1 in Paragraph [0064]). 9. Claims 17-19, 21-22, 24-26, and 28-30 are rejected under 35 U.S.C. 103 as being unpatentable over ZHANG et al. (US 20130049626 A1) in view of NEWTON et al. (EP 0582813 A2) in further view of Zipperer et al. (US 2013/0154594 A1). 10. As to claim 17, ZHANG teaches the circuit device of claim 11. However ZHANG does not explicitly teach wherein the controller and each of the set of control logic blocks is configured such that the third and fourth switches of each of the set of energy transfer blocks has a constant width ON-time. However, Zipperer teaches wherein the controller (Fig. 1-2 Item 10 discloses a control logic CNTL 5) and each of the set of control logic blocks (Fig. 1-2 Item 6 & 5) is configured such that the third and fourth switches (Fig. 1-2 Item Ls) of each of the set of energy transfer blocks has a constant width ON (Fig. 1-2 Item 10 discloses a generated with the constant clock signal CLK received from the oscillator OSC 4 to provide a constant width ON in Paragraph [0018]) - It would have been obvious to one skilled in the art before the effective filing date of the invention to modify a device for transferred electric energy in ZHANG to provide an energy transfer block and measuring device by Zipperer in order to provide an electronic device and a method for measuring a power consumption in a switched mode power converter in Paragraph [0006]). 11. As to claim 18, ZHANG teaches the circuit device of claim 11. However ZHANG does not explicitly teach a reference impedance that includes: a resistor coupled to the third output of each of the set of energy transfer blocks; and a fifth switch coupled between the resistor and the fourth output of each of the set of energy transfer blocks. However, Zipperer teaches a reference impedance (Fig. 1-2 Item R & L discloses a reference impedance in form of a reference resistor R can be coupled through switch LS to the output in Paragraph [0019]) that includes: a resistor (Fig. 1-2 Item R & Ls discloses a R can be coupled through switch LS to the output in Paragraph [0019]) coupled to the third output of each of the set of energy transfer blocks (Fig. 1-2 Item 10 discloses a measuring power converter MPC 10 Paragraph [0017]); and a fifth switch coupled between the resistor and the fourth output of each of the set of energy transfer blocks (Fig. 1-2 Item Ls discloses a switch LS to the output of measuring power converter MPC 10 in Paragraph [0019]). It would have been obvious to one skilled in the art before the effective filing date of the invention to modify a device for transferred electric energy in ZHANG to provide an energy transfer block and measuring device by Zipperer in order to provide an electronic device and a method for measuring a power consumption in a switched mode power converter in Paragraph [0006]). 12. As to claim 19, ZHANG teaches the circuit device of claim 18. However ZHANG does not explicitly teach wherein the controller includes a calibration block coupled to the reference impedance. However, Zipperer teaches wherein the controller includes (Fig. 1-2 Item 5, LS, and R) a calibration block (Fig. 1-2 Item Ls discloses a switch LS to the output. During a reference measurement for calibrating/normalizing the power measurement in Paragraph [0019]) coupled to the reference impedance (Fig. 1-2 Item R). It would have been obvious to one skilled in the art before the effective filing date of the invention to modify a device for transferred electric energy in ZHANG to provide an energy transfer block and measuring device by Zipperer in order to provide an electronic device and a method for measuring a power consumption in a switched mode power converter in Paragraph [0006]). 13. As to claim 21, ZHANG teaches a system comprising: a buck energy transfer block (Fig. 1-6 Item 420b discloses booster converter in Paragraph [0071]) that includes: first and second inputs (Fig. 1-6 Item 421 & 422 discloses booster converter in Paragraph [0071]) configured to couple to a power supply (Fig. 1-6 Item 421 & 422 discloses booster converter in Paragraph [0071]) first and second outputs; and a first switch (Fig. 1-6 Item 423); third and fourth inputs, wherein: the third input is coupled to the first output of the buck energy transfer block; and the fourth input is coupled to the second output of the buck energy transfer block; and a third switch (Fig. 1-6 Item 433), wherein switching of the third switch (Fig. 1-6 Item 433) of each of the set of boost energy transfer blocks is aligned to a clock (Fig. 1-6 Item 240 discloses controller 240 provides pulses having a relatively high frequency, such as in the order of 100 KHz, in Paragraph [0027]).; and However ZHANG does not explicitly teach a set of energy transfer blocks coupled to the first energy transfer block that each include: However, NEWTON teaches a set of energy transfer blocks (Figs. 1 Item 5 discloses a set of energy transfer blocks) coupled to the first energy transfer block (Figs. 1 Item 4 discloses an energy transfer block): It would have been obvious to one skilled in the art before the effective filing date of the invention to modify a device for transferred electric energy in ZHANG to provide a set of energy transfer blocks by NEWTON in order to provide to a boost (step-up) voltage. However ZHANG does not explicitly teach a reference impedance that includes: a resistor coupled to the third output of each of the set of energy transfer blocks; and a fifth switch coupled between the resistor and the fourth output of each of the set of energy transfer blocks. However, Zipperer teaches a reference impedance (Fig. 1-2 Item R & L discloses a reference impedance in form of a reference resistor R can be coupled through switch LS to the output in Paragraph [0019]) that includes: a resistor (Fig. 1-2 Item R & Ls discloses a R can be coupled through switch LS to the output in Paragraph [0019]) coupled to the third output of each of the set of energy transfer blocks (Fig. 1-2 Item 10 discloses a measuring power converter MPC 10 Paragraph [0017]); and a fifth switch coupled between the resistor and the fourth output of each of the set of energy transfer blocks (Fig. 1-2 Item Ls discloses a switch LS to the output of measuring power converter MPC 10 in Paragraph [0019]). It would have been obvious to one skilled in the art before the effective filing date of the invention to modify a device for transferred electric energy in ZHANG to provide an energy transfer block and measuring device by Zipperer in order to provide an electronic device and a method for measuring a power consumption in a switched mode power converter in Paragraph [0006]). 14. As to claim 22, ZHANG teaches the system of claim 21, wherein the buck energy transfer block (Fig. 1-6 Item 420b discloses booster converter in Paragraph [0071]) includes: a first inductor (Fig. 1-6 Item 421) that includes a first terminal and a second terminal, wherein the second terminal is coupled to the first output of the buck energy transfer block (Fig. 1-6 Item 420b), wherein: the second terminal is coupled to the first output of the buck energy transfer block; and the first switch (Fig. 1-6 Item 423) is coupled between the first input of the buck energy transfer block and the first terminal of the first inductor (Fig. 1-6 Item 421); and a capacitor (Fig. 1-6 Item 424) coupled between the second terminal of the first inductor and the second input of the buck energy transfer block (Fig. 1-6 Item 420b); and a first diode (Fig. 1-6 Item 426 or 427 or 232 discloses diode) coupled between the second input of the buck energy transfer block (Fig. 1-6 Item 420b) and the first terminal of the first inductor (Fig. 1-6 Item 421). 15. As to claim 24, ZHANG teaches the system of claim 21, further comprising a controller (Fig. 1-6 Item 240 or 340 or 440 discloses controller respectively in Paragraph [0064]) coupled to the first energy transfer block (Fig. 1-6 Item 420b discloses booster converter in Paragraph [0071]) and the set of boost energy transfer blocks and configured to control switching (Fig. 1-6 Item 423 & 425) of the third switch of each of the set of boost energy transfer blocks (Fig. 1-6 Item 420B and 430 are energy transfer blocks). 16. As to claim 25, ZHANG teaches the system of claim 24, wherein the controller includes: a first control logic block (Fig. 1-6 Item 240 or 340 or 440 discloses controller respectively in Paragraph [0064]) coupled to the first energy transfer block (Fig. 1-6 Item 420b discloses booster converter in Paragraph [0071]) to control switching of the first switch (Fig. 1-6 Item 423) and the second switch (Fig. 1-6 Item 425); and a set of control logic blocks (Fig. 1-6 Item 440 discloses controller which can be one respectively for each block in Paragraph [0064]) that includes a respective block coupled to each of the set of energy transfer blocks (Fig. 1-6 Item 420B and 430 are energy transfer blocks) to control switching of the third and fourth switches of the respective energy transfer block (Fig. 1-6 Item 440 discloses controller changes the transistors 423, 425, 433 and 436 switches 1-4 in order to detect voltage levels in Paragraph [0064]). 17. As to claim 26, ZHANG teaches the system of claim 25 further comprising a capacitor (Fig. 1-6 Item 424) that is coupled between the third and fourth outputs of each of the set of boost energy transfer blocks (Fig. 1-6 Item 420B). 18. As to claim 28, ZHANG teaches the system of claim 24. However ZHANG does not explicitly teach wherein the controller and each of the set of control logic blocks is configured such that the third and fourth switches of each of the set of energy transfer blocks has a constant width ON-time. However, Zipperer teaches wherein the controller (Fig. 1-2 Item 10 discloses a control logic CNTL 5) and each of the set of control logic blocks (Fig. 1-2 Item 6 & 5) is configured such that the third and fourth switches (Fig. 1-2 Item Ls) of each of the set of energy transfer blocks has a constant width ON (Fig. 1-2 Item 10 discloses a generated with the constant clock signal CLK received from the oscillator OSC 4 to provide a constant width ON in Paragraph [0018]) - It would have been obvious to one skilled in the art before the effective filing date of the invention to modify a device for transferred electric energy in ZHANG to provide an energy transfer block and measuring device by Zipperer in order to provide an electronic device and a method for measuring a power consumption in a switched mode power converter in Paragraph [0006]). 19. As to claim 29, ZHANG teaches the system of claim 24. However ZHANG does not explicitly teach wherein the controller includes a calibration block coupled to the reference impedance. However, Zipperer teaches wherein the controller includes (Fig. 1-2 Item 5, LS, and R) a calibration block (Fig. 1-2 Item Ls discloses a switch LS to the output. During a reference measurement for calibrating/normalizing the power measurement in Paragraph [0019]) coupled to the reference impedance (Fig. 1-2 Item R). It would have been obvious to one skilled in the art before the effective filing date of the invention to modify a device for transferred electric energy in ZHANG to provide an energy transfer block and measuring device by Zipperer in order to provide an electronic device and a method for measuring a power consumption in a switched mode power converter in Paragraph [0006]). 20. As to claim 30, ZHANG teaches the system of claim 24, wherein the controller (Fig. 1-6 Item 240 or 340 or 440 discloses controller respectively in Paragraph [0064]) is configured to cause a plurality of the third switches of the set of energy transfer blocks to be active concurrently (Fig. 1-6 Item 240 or 340 or 440 discloses controller 440 respectively provides first pulses to the first switch 433, and second pulses to the second switch 436, and respectively adjusts duty cycle of the first pulses and duty cycle of the second pulses to generate the output voltage VOUT1 in Paragraph [0064]). Allowable Subject Matter Claim 13 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims and overcome the double patenting rejection set forth above. Claim 16 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims and overcome the double patenting rejection set forth above. Claim 23 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims and overcome the double patenting rejection set forth above. Claim 27 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims and overcome the double patenting rejection set forth above. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRENT J ANDREWS whose telephone number is (571)272-6101. The examiner can normally be reached 10am-5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Judy Nguyen can be reached at (571)272-2258. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /BRENT J ANDREWS/ Examiner, Art Unit 2858 /JUDY NGUYEN/ Supervisory Patent Examiner, Art Unit 2858
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Prosecution Timeline

Feb 29, 2024
Application Filed
Apr 29, 2026
Non-Final Rejection mailed — §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
78%
Grant Probability
99%
With Interview (+28.4%)
3y 2m (~11m remaining)
Median Time to Grant
Low
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