Prosecution Insights
Last updated: April 19, 2026
Application No. 18/591,194

CIRCUIT BOARD ASSEMBLY AND TERMINAL DEVICE

Non-Final OA §102§103§112
Filed
Feb 29, 2024
Examiner
MILAKOVICH, NATHAN J
Art Unit
2847
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Triple Win Technology(Shenzhen) Co. Ltd.
OA Round
1 (Non-Final)
78%
Grant Probability
Favorable
1-2
OA Rounds
2y 5m
To Grant
97%
With Interview

Examiner Intelligence

Grants 78% — above average
78%
Career Allow Rate
543 granted / 699 resolved
+9.7% vs TC avg
Strong +19% interview lift
Without
With
+19.3%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
16 currently pending
Career history
715
Total Applications
across all art units

Statute-Specific Performance

§101
0.7%
-39.3% vs TC avg
§103
40.7%
+0.7% vs TC avg
§102
27.2%
-12.8% vs TC avg
§112
22.7%
-17.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 699 resolved cases

Office Action

§102 §103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Priority Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Drawings The drawings were received on February 29, 2024. These drawings are accepted. Specification The disclosure including the abstract is objected to because of the following informalities: As below regarding the claims, the use of the term “welding” throughout the application appears to be an error and should be changed to “soldering”. The joining of two materials by melting a filler material (e.g., soldering) is not welding. The base materials are not melted during soldering. Welding is the melting of two base materials to fuse them together. While some forms of welding use a filler materiel, welding is a process distinct from brazing and soldering. Appropriate correction is required. For purposes of examination, “soldering” is presumed to be intended. Claim Objections Claims 6 and 15 are objected to because of the following informalities: Claims 6 and 15: “the flexible circuit board is electrically connected the first substrate to the second substrate” should be, “the flexible circuit board electrically connects the first substrate to the second substrate” or similar language. Appropriate correction is required. Claim Rejections - 35 USC § 112 Claims 1-17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Where applicant acts as his or her own lexicographer to specifically define a term of a claim contrary to its ordinary meaning, the written description must clearly redefine the claim term and set forth the uncommon definition so as to put one reasonably skilled in the art on notice that the applicant intended to so redefine that claim term. Process Control Corp. v. HydReclaim Corp., 190 F.3d 1350, 1357, 52 USPQ2d 1029, 1033 (Fed. Cir. 1999). The term “welding” is used in the claims to mean “soldering” while the accepted meaning is “joining two materials by melting them to fuse the materials.” The term is indefinite because the specification does not clearly redefine the term. If Applicant does intend “welding”, the specification should expressly set forth a definition and the use of solder in the specification should be more clearly explained. For purposes of examination, “soldering” is presumed to be intended. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-5, 7-12, 14, and 16-17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US Publication 2019/0221507 to Kimura et al. (hereinafter Kimura). Claim 1 Kimura discloses a circuit board assembly comprising: a first substrate (101-103) comprising a first surface, a second surface, and a side surface, the first surface and the second surface being opposite to each other along a first direction, the side surface connecting the first surface to the second surface, at least one groove (3) defined on the side surface and extending through the first surface and the second surface; and at least one first pad (5), each of the at least one first pad (5) accommodated in a corresponding groove (3) of the at least one groove (3; paragraph 26) and connecting to a groove wall of the corresponding groove (3), each of the at least one first pad (5) comprising a first welding surface, a second welding surface, and a third welding surface, the first welding surface connecting to the first surface, the second welding surface connecting to the second surface, the third welding surface connecting the first welding surface to the second welding surface (paragraph 32). Claim 2 Kimura discloses the circuit board assembly of claim 1, wherein the third welding surface (of 5) comprises a receiving groove (see detail FIG. 2B). Claim 3 Kimura discloses the circuit board assembly of claim 2, wherein the third welding surface (of 5) further comprises a first connecting surface and two second connecting surfaces each connected to a respective side of the first connecting surface, the first connecting surface is arc-shaped and comprises the receiving groove, and each of the two second connecting surface connects to the respective first connecting surface to the side surface (see detail FIG. 2B). Claim 4 Kimura discloses the circuit board assembly of claim 3, wherein when viewed along the first direction, a projection of the first welding surface and a projection of the second welding surface coincide (see detail FIG. 2B). Claim 5 Kimura discloses the circuit board assembly of claim 1, wherein the first substrate (101-103) further comprises a plurality of conductive layers (2), and at least one insulating layer (102), the plurality of conductive layers (2) and the at least one insulating layer (102) are stacked in the first direction, an insulating layer (102) of the at least one insulating layer (102) is disposed between two adjacent of the plurality of conductive layers (2; see detail FIG. 6), and the third welding surface (of 5) is connected to an exposed portion of the plurality of conductive layers (2) from the groove (3; see detail FIG. 6). Claim 7 Kimura discloses the circuit board assembly of claim 1, wherein a positioning groove (10) is defined on the side surface of the first substrate (101-103), and the positioning groove (10) is spaced apart from the at least one groove (3). Claim 8 Kimura discloses the circuit board assembly of claim 1, wherein the at least one first pad (5) is made of copper (paragraph 26). Claim 9 Kimura discloses a terminal device comprising: a circuit board assembly comprising: a first substrate (101-103) comprising a first surface, a second surface, and a side surface, the first surface and the second surface being opposite to each other along a first direction, the side surface connecting the first surface to the second surface, at least one groove (3) defined on the side surface and extending through the first surface and the second surface; and at least one first pad (5), each of the at least one first pad (5) accommodated in a corresponding groove (3) of the at least one groove (3; paragraph 26) and connecting to a groove wall of the corresponding groove (3), each of the at least one first pad (5) comprising a first welding surface, a second welding surface, and a third welding surface, the first welding surface connecting to the first surface, the second welding surface connecting to the second surface, the third welding surface connecting the first welding surface to the second welding surface (paragraph 32); an external circuit board (21); and at least one second pad (solder between 27 and 5) electrically connecting the circuit board assembly to the external circuit board (21). Claim 10 Kimura discloses the terminal device of claim 9, wherein the third welding surface (of 5) comprises a receiving groove (see detail FIG. 2B), the at least one second pad (solder between 27 and 5) is accommodated in the receiving groove (of 5) and disposed on at least one of the first surface and second surface (paragraph 51). Claim 11 Kimura discloses the terminal device of claim 10, wherein the third welding surface (of 5) further comprises a first connecting surface and two second connecting surfaces each connected to a respective side of the first connecting surface, the first connecting surface is arc-shaped and comprises the receiving groove, and each of the two second connecting surface connects to the respective first connecting surface to the side surface (see detail FIG. 2B). Claim 12 Kimura discloses the terminal device of claim 11, wherein when viewed along the first direction, a projection of the first welding surface and a projection of the second welding surface coincide (see detail FIG. 2B). Claim 14 Kimura discloses the terminal device of claim 9, wherein the first substrate (101-103) further comprises a plurality of conductive layers (2), and at least one insulating layer (102), the plurality of conductive layers (2) and the at least one insulating layer (102) are stacked in the first direction, each of the at least one insulating layer (102) is disposed between two adjacent of the plurality of conductive layers (2; see detail FIG. 6), and the third welding surface (of 5) is connected to an exposed portion of the plurality of conductive layers (2) from the groove (3; see detail FIG. 6). Claim 16 Kimura discloses the terminal device of claim 9, wherein a positioning groove (10) is defined on the side surface of the first substrate (101-103), and the positioning groove (10) is spaced apart from the at least one groove (3), the external circuit board comprises a positioning portion (solder corresponding portion of 25 for 31), the positioning portion (solder) is clamped in the positioning groove (10; paragraph 42) Claim 17 Kimura discloses the terminal device of claim 9, wherein the at least one first pad (5) is made of copper (paragraph 26). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 6, 13, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Kimura in view of US Patent 6,147,876 to Yamaguchi et al. (hereinafter Yamaguchi). Claim 6 Kimura discloses the circuit board assembly of claim 1, as shown above. Kimura does not expressly disclose a second substrate, an electronic component, and a flexible circuit board, wherein the electronic component is connected to the second substrate, and the flexible circuit board is electrically connected the first substrate to the second substrate, as recited in claim 6. Yamaguchi (FIG. 7-8, 30) teaches a second substrate (5A), an electronic component (201), and a flexible circuit board (F), wherein the electronic component (201) is connected to the second substrate (5A), and the flexible circuit board (F) is electrically connected a first substrate (additional 5A) to the second substrate (5A). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Yamaguchi with Kimura to incorporate additional electronic components, substrates, and flexible circuit boards as taught by Yamaguchi in the structure taught by Kimura, as one having ordinary skill in the art would have been motivated to do this with a reasonable expectation of success because such a combination and/or modification allows for disposing multi-chip modules in three dimensions (Yamaguchi column 15 lines 27-29), allowing for more options when routing and assembling. Claim 13 Kimura discloses the terminal device of claim 9, as shown above. Kimura does not expressly an adhesive layer, wherein the adhesive layer is between the first surface and the external circuit board or between the second surface and the external circuit board, as recited in claim 13. Yamaguchi (column 11 lines 38-41) applying an adhesive layer between components and a board. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Yamaguchi with Kimura to incorporate an adhesive as taught by Yamaguchi in the structure taught by Kimura and thereby have an adhesive layer between the first surface and the external circuit board or between the second surface and the external circuit board, as one having ordinary skill in the art would have been motivated to do this with a reasonable expectation of success because such a combination and/or modification allows for accurately positioning components before soldering or reflow and using adhesives with varying properties such as flexibility or repositionability, depending on design constraints. Claim 15 Kimura discloses the terminal device of claim 9, as shown above. Kimura does not expressly disclose a second substrate, an electronic component, and a flexible circuit board, wherein the electronic component is connected to the second substrate, and the flexible circuit board is electrically connected the first substrate to the second substrate, as recited in claim 15. Yamaguchi (FIG. 7-8, 30) teaches a second substrate (5A), an electronic component (201), and a flexible circuit board (F), wherein the electronic component (201) is connected to the second substrate (5A), and the flexible circuit board (F) is electrically connected a first substrate (additional 5A) to the second substrate (5A). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Yamaguchi with Kimura to incorporate additional electronic components, substrates, and flexible circuit boards as taught by Yamaguchi in the structure taught by Kimura, as one having ordinary skill in the art would have been motivated to do this with a reasonable expectation of success because such a combination and/or modification allows for disposing multi-chip modules in three dimensions (Yamaguchi column 15 lines 27-29), allowing for more options when routing and assembling. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: US 20160163610 (see, e.g., FIG. 4C); US 20240349428 (see, e.g., FIG. 4); US 20240243499 (see, e.g., FIG. 3-6); US 6534726 (see, e.g., FIG. 4); and US 5982626 (see, e.g., FIG. 1-2). Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATHAN MILAKOVICH whose telephone number is (571) 270-3087. The examiner can normally be reached Monday - Friday 9:00 AM - 5:00 PM EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Dole can be reached at (571) 272-2229. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /NATHAN MILAKOVICH/Primary Examiner, Art Unit 2848
Read full office action

Prosecution Timeline

Feb 29, 2024
Application Filed
Sep 30, 2025
Non-Final Rejection — §102, §103, §112 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12603226
MULTILAYERED CAPACITOR
2y 5m to grant Granted Apr 14, 2026
Patent 12604404
CIRCUIT BOARD WELD STRUCTURE
2y 5m to grant Granted Apr 14, 2026
Patent 12603223
MULTILAYER ELECTRONIC COMPONENT
2y 5m to grant Granted Apr 14, 2026
Patent 12597565
MULTILAYER ELECTRONIC COMPONENT
2y 5m to grant Granted Apr 07, 2026
Patent 12579914
WINDING-TYPE DISPLAY DEVICE AND METHOD FOR DETECTING LIGHT EMISSION INFORMATION OF WINDING-TYPE DISPLAY DEVICE
2y 5m to grant Granted Mar 17, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

AI Strategy Recommendation

Get an AI-powered prosecution strategy using examiner precedents, rejection analysis, and claim mapping.
Powered by AI — typically takes 5-10 seconds

Prosecution Projections

1-2
Expected OA Rounds
78%
Grant Probability
97%
With Interview (+19.3%)
2y 5m
Median Time to Grant
Low
PTA Risk
Based on 699 resolved cases by this examiner. Grant probability derived from career allow rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month