DETAILED ACTION
This Office Action is in response to the application filed on 29 February 2024.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 4, 10, 12-14, 18, and 19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In regards to claim 4, claim 4 recites in pertinent part “wherein each of the lower interface layer and the upper interface layer comprises….” Claim 4 is dependent on claim 3 which recites in pertinent part “further comprising at least one of a lower interface layer … and an upper interface layer….” While claim 3 appears to only require one of a lower or an upper interface layer, claim 4 appears to require both. Therefore, it is unclear how there can be both a lower and an upper interface layer when only one of said layers is required. For the purposes of examination, claim 4 will be read to be commensurate with claim 3 and only require “at least one of a lower interface layer … and an upper interface layer….”
In regards to claim 10, claim 10 is dependent from claim 9. Claim 9 appears to recite limitations pertaining to a “final” device or at least a device which is more complete. Claim 10 appears to recite limitations pertaining to a device which is intermediate to the device as claimed in claim 9; therefore, it is unclear whether the final device of claim 9 is being claimed or whether the intermediate device of claim 10 is being claimed. For the purposes of examination, claim 10 will be read to be commensurate with the limitations of claim 9 and only the final element of a crystalline dielectric layer will be treated on the merits.
In regards to claim 12, claim 12 is dependent from claim 9. Both claims appear be drawn towards a product/device, however, claim 12 appears to recite process/method limitations. It is unclear whether a product/device or a process/method is being claimed in claim 12. Since no product/device limitations appear to be present in claim 12, it is not possible to treat claim 12 on the merits.
In regards to claim 13, claim 13 is dependent from claim 12. Claim 12 is rejected under 35 U.S.C. § 112 and as such claim 13 is rejected as well. Furthermore, both claims appear to be drawn towards a product/device, however, both claims appear to recite process/method limitations. It is unclear whether a product/device or a process/method is being claimed in claim 13. Since no product/device limitations appear to be present in claim 13, it is not possible to treat claim 13 on the merits.
In regards to claim 14, claim 14 is dependent from claim 12. Claim 12 is rejected under 35 U.S.C. § 112 and as such claim 14 is rejected as well. Furthermore, both claims appear to be drawn towards a product/device, however, both claims appear to recite process/method limitations. It is unclear whether a product/device or a process/method is being claimed in claim 14. Since no product/device limitations appear to be present in claim 14, it is not possible to treat claim 14 on the merits.
In regards to claim 18, claim 18 is dependent from claim 17. Both claims appear be drawn towards a product/device, however, claim 18 appears to recite process/method limitations. It is unclear whether a product/device or a process/method is being claimed in claim 18. Since no product/device limitations appear to be present in claim 18, it is not possible to treat claim 18 on the merits.
In regards to claim 19, claim 19 is dependent from claim 18. Claim 18 is rejected under 35 U.S.C. § 112 and as such claim 19 is rejected as well. Furthermore, both claims appear to be drawn towards a product/device, however, both claims appear to recite process/method limitations. It is unclear whether a product/device or a process/method is being claimed in claim 19. Since no product/device limitations appear to be present in claim 19, it is not possible to treat claim 19 on the merits.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 12-14, 18, and 19 are rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject matter. The claim(s) does/do not fall within at least one of the four categories of patent eligible subject matter.
In regards to claim 12-14, 18, and 19, are drawn towards and depend on claims that are drawn towards a product/device. However, the claims in question all recite only process/method limitations. It is unclear which statutory category the claims in question belong since they appear to mix two statutory categories. The issue is further complicated by the fact that there are no product/device limitations recited by the claims in question. As such it is not clear to which statutory category claims 12-14, 18, and 19 belong and it is not possible to treat the claims in question on the merits.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 and 9-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Alzate et al. (US 2020/0194434 A1; hereinafter Alzate), in view of Nakanishi et al. (US 2002/0149044 A1; hereinafter Nakanishi).
In regards to claim 1, Alzate teaches, e.g. in figs. 1 and 4, a semiconductor device comprising:
a lower electrode (163) [0052] disposed on a substrate (151) [0049];
a dielectric layer (165) [0052] covering the lower electrode (fig. 1(c)); and
an upper electrode (161) [0052] spaced apart from the lower electrode, wherein the dielectric layer is disposed between the upper electrode and the lower electrode (fig. 1(c)).
Alzate appears to be silent as to, but does not preclude, the limitations wherein the dielectric layer has a specific range of thickness, and wherein the dielectric layer has a specific range of grain sizes. Nakanishi teaches the limitations wherein the dielectric layer has a specific range of thickness [0146], and wherein the dielectric layer has a specific range of grain sizes [0044]. It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by Alzate with the aforementioned limitations taught by Nakanishi to affect storage capacitance characteristics of a memory device (Nakanishi [0044], [0146]).
The combination of Alzate and Nakanishi appears to be silent as to the limitations wherein a thickness of the dielectric layer is less than or equal to 6 nm, and a grain size in the dielectric layer is between 3 nm and 30 nm; however, where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. See MPEP §2144.05 II A; see also In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). In the case at hand, Nakanishi teaches the general conditions of claim 1. Specifically, Nakanishi teaches that the thickness of a capacitor dielectric and the grain size of a capacitor are variables that have the effect of changing capacitor dielectric density and therefore storage capacitance ([0044], [0146]). Therefore, one having ordinary skill in the at the time the application at hand would find it obvious to discover the optimum or workable ranges wherein a thickness of the dielectric layer is less than or equal to 6 nm, and a grain size in the dielectric layer is between 3 nm and 30 nm using only routine skill in the art.
In regards to claim 9, claim 9 is drawn to a product/device, however claim 9 appears to recite process/method limitations that do not appear to materially affect the structural elements of the product/device. Therefore, claim 9 will be interpreted as a “product by process” claim.
A "product by process" claim is directed to the final product per se, no matter how it is actually made. In re Hirao and Sato et al., 190 USPQ 15, 17 (CCPA 1976) (footnote 3); see also In re Brown and Saffer, 173 USPQ 685 (CCPA 1972); In re Luck and Gainer, 177 USPQ 523 (CCPA 1973); In re Fessmann, 180 USPQ 324 (CCPA 1974); and In re Marosi et al., 218 USPQ 289 (CAFC 1983). It is the patentability of the final product per se which must be determined in a "product by process" claim, and not the patentability of the process, and that an old or obvious product, produced by a new method is not patentable as a product, whether claimed in "product by process" claims or not. Id. Note that Applicant has the burden of proof in such cases. Id. Furthermore, “[e]ven though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process.” In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985) (citations omitted).
Specifically, the limitations “wherein the dielectric layer is deposited to an initial thickness that is greater than 6 nm and less than or equal to 15 nm and is etched to a final thickness that is less than or equal to 6 nm” appear to be process/method limitations. For the purposes of examination, only the device limitations will be examined on the merits, i.e. the limitation in question will be read as “wherein the dielectric layer has a thickness that is less than or equal to 6 nm.”
Further in regards to claim 9, Alzate teaches, e.g. in figs. 1 and 4, a semiconductor device comprising:
a lower electrode (163) [0052] disposed on a substrate (151) [0049];
a dielectric layer (165) [0052] covering the lower electrode (fig. 1(c)); and
an upper electrode (161) [0052] spaced apart from the lower electrode, wherein the dielectric layer is disposed between the upper electrode and the lower electrode (fig. 1(c)).
Alzate appears to be silent as to, but does not preclude, the limitations wherein the dielectric layer has a specific range of thickness. Nakanishi teaches the limitations wherein the dielectric layer has a specific range of thickness [0146]. It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by Alzate with the aforementioned limitations taught by Nakanishi to affect storage capacitance characteristics of a memory device (Nakanishi [0044], [0146]).
The combination of Alzate and Nakanishi appears to be silent as to the limitation wherein a thickness of the dielectric layer is less than or equal to 6 nm; however, where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. See MPEP §2144.05 II A; see also In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). In the case at hand, Nakanishi teaches the general conditions of claim 9. Specifically, Nakanishi teaches that the thickness of a capacitor dielectric and the grain size of a capacitor are variables that have the effect of changing capacitor dielectric density and therefore storage capacitance ([0044], [0146]). Therefore, one having ordinary skill in the at the time the application at hand would find it obvious to discover the optimum or workable ranges wherein a thickness of the dielectric layer is less than or equal to 6 nm using only routine skill in the art.
In regards to claim 10, claim 10 is drawn to a product/device, however claim 10 appears to recite process/method limitations that do not appear to materially affect the structural elements of the product/device. Therefore, claim 10 will be interpreted as a “product by process” claim.
A "product by process" claim is directed to the final product per se, no matter how it is actually made. In re Hirao and Sato et al., 190 USPQ 15, 17 (CCPA 1976) (footnote 3); see also In re Brown and Saffer, 173 USPQ 685 (CCPA 1972); In re Luck and Gainer, 177 USPQ 523 (CCPA 1973); In re Fessmann, 180 USPQ 324 (CCPA 1974); and In re Marosi et al., 218 USPQ 289 (CAFC 1983). It is the patentability of the final product per se which must be determined in a "product by process" claim, and not the patentability of the process, and that an old or obvious product, produced by a new method is not patentable as a product, whether claimed in "product by process" claims or not. Id. Note that Applicant has the burden of proof in such cases. Id. Furthermore, “[e]ven though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process.” In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985) (citations omitted).
Specifically, the limitations wherein the dielectric layer is crystallized at a temperature between 300℃ and 450℃ after being deposited to a thickness that is greater than 6 nm and less than or equal to 15 nm appear to be process/method limitations. For the purposes of examination, only the device limitations will be examined on the merits. For the purposes of examination, the final device limitation “wherein the dielectric layer is crystalline” will be treated on the merits.
Further in regards to claim 10, the combination of Alzate and Nakanishi teaches the method discussed above in addressing claim 9. Nakanishi further teaches the limitations wherein the dielectric layer is crystalline [0044]. It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by Alzate with the aforementioned limitations taught by Nakanishi to affect storage capacitance characteristics of a memory device (Nakanishi [0044], [0146]).
In regards to claim 11, the combination of Alzate and Nakanishi teaches the limitations discussed above in addressing claim 9. The combination of Alzate and Nakanishi appears to be silent as to the limitations wherein a grain size in the dielectric layer is between 3 nm and 15 nm; however, where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. See MPEP §2144.05 II A; see also In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). In the case at hand, Nakanishi teaches the general conditions of claim 11. that the thickness of a capacitor dielectric and the grain size of a capacitor are variables that have the effect of changing capacitor dielectric density and therefore storage capacitance ([0044], [0146]). Therefore, one having ordinary skill in the at the time the application at hand would find it obvious to discover the optimum or workable ranges wherein a grain size in the dielectric layer is between 3 nm and 15 nm using only routine skill in the art.
Claim(s) 2 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Alzate and Nakanishi as respectively applied to claims 1 and 9 above, and further in view of Lee et al. (US 6,010,940 A; hereinafter Lee).
In regards to claim 2, the combination of Alzate and Nakanishi teaches the limitations discussed above in addressing claim 1. The combination of Alzate and Nakanishi appears to be silent as to, but does not preclude, the limitations wherein the dielectric layer comprises at least one selected from fluorine (F) and chloride (Cl). Lee teaches the limitations wherein the dielectric layer comprises at least one selected from fluorine (F) and chloride (Cl) (col. 5/lns. 58-67). It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by the combination of Alzate and Nakanishi with the aforementioned limitations taught by Lee to reduce current leakage (Lee col. 5/lns. 58-67).
The combination of Alzate, Nakanishi, and Lee appears to be silent as to the limitations wherein a content of at least one selected from F and Cl in the dielectric layer is between 0.01 at% and 15 at%; however, where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. See MPEP §2144.05 II A; see also In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). In the case at hand, Lee teaches the general conditions of claim 2. Specifically, Lee teaches that the content of F or Cl in a capacitor dielectric is a variable that, when changed, has the effect of changing the leakage current of a capacitor (col. 5/lns. 58-67). Therefore, one having ordinary skill in the at the time the application at hand would find it obvious to discover the optimum or workable ranges wherein a content of at least one selected from F and Cl in the dielectric layer is between 0.01 at% and 15 at% using only routine skill in the art.
In regards to claim 15, the combination of Alzate and Nakanishi teaches the limitations discussed above in addressing claim 9. The combination of Alzate and Nakanishi appears to be silent as to, but does not preclude, the limitations wherein the dielectric layer comprises at least one selected from fluorine (F) and chloride (Cl). Lee teaches the limitations wherein the dielectric layer comprises at least one selected from fluorine (F) and chloride (Cl) (col. 5/lns. 58-67). It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by the combination of Alzate and Nakanishi with the aforementioned limitations taught by Lee to reduce current leakage (Lee col. 5/lns. 58-67).
The combination of Alzate, Nakanishi, and Lee appears to be silent as to the limitation wherein a content of at least one selected from F and Cl in the dielectric layer is between 0.01 at% and 15 at%; however, where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. See MPEP §2144.05 II A; see also In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). In the case at hand, Lee teaches the general conditions of claim 2. Specifically, Lee teaches that the content of F or Cl in a capacitor dielectric is a variable that, when changed, has the effect of changing the leakage current of a capacitor (col. 5/lns. 58-67). Therefore, one having ordinary skill in the at the time the application at hand would find it obvious to discover the optimum or workable ranges wherein a content of at least one selected from F and Cl in the dielectric layer is between 0.01 at% and 15 at% using only routine skill in the art.
Claim(s) 16 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Alzate, in view of Sharma et al. (US 2020/0279953 A1; hereinafter Sharma), in view of Nakanishi.
In regards to claim 16, Alzate teaches, e.g. in figs. 1 and 4, a semiconductor device comprising:
an active region (160) defined (interpreted as surrounded) by a device isolation layer ((175) and (153)) in a substrate (151) [0049];
word lines (W1/W2) ([0050], [0067]) extending in a first horizontal direction ([0051]: e.g. word line direction);
bit lines (B1/B2) ([0050], [0067]) extending in a second horizontal direction and
a capacitor structure (170) electrically connected (e.g. by (162)) to the active region [0050] at a vertical level that is higher than the bit lines ([0050]: (170) is connected to (160) at (162) which is above the point where bitlines exist in the region at (171)), wherein the capacitor structure comprises:
a lower electrode (163) [0052] extending in a vertical direction perpendicular to the first horizontal direction and the second horizontal direction (e.g. fig. 1(c): vertical portions of U-shaped (163));
a dielectric layer (165) [0052] covering the lower electrode (fig. 1(c)); and
an upper electrode (161) [0052] spaced apart from the lower electrode, wherein the dielectric layer is disposed between the upper electrode and the lower electrode (fig. 1(c)).
Alzate appears to be silent as to, but does not preclude, the limitations wherein bit lines extend in a second horizontal direction perpendicular to a first horizontal direction. Sharma teaches the limitations wherein bit lines extend in a second horizontal direction perpendicular to a first horizontal direction (fig. 7: Bit lines (730/770) run perpendicularly to word lines (720)). It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by Alzate with the aforementioned limitations taught by Sharma to form a logic circuit layout for a memory device (Sharma [0055]).
The combination of Alzate and Sharma appears to be silent as to, but does not preclude, the limitations wherein the dielectric layer has a specific range of thickness, and wherein the dielectric layer has a specific range of grain sizes. Nakanishi teaches the limitations wherein the dielectric layer has a specific range of thickness [0146], and wherein the dielectric layer has a specific range of grain sizes [0044]. It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by the combination of Alzate and Sharma with the aforementioned limitations taught by Nakanishi to affect storage capacitance characteristics of a memory device (Nakanishi [0044], [0146]).
The combination of Alzate, Sharma, and Nakanishi appears to be silent as to the limitations wherein a thickness of the dielectric layer is less than or equal to 6 nm, and a grain size in the dielectric layer is between 3 nm and 30 nm; however, where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. See MPEP §2144.05 II A; see also In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). In the case at hand, Nakanishi teaches the general conditions of claim 16. Specifically, Nakanishi teaches that the thickness of a capacitor dielectric and the grain size of a capacitor are variables that have the effect of changing capacitor dielectric density and therefore storage capacitance ([0044], [0146]). Therefore, one having ordinary skill in the at the time the application at hand would find it obvious to discover the optimum or workable ranges wherein a thickness of the dielectric layer is less than or equal to 6 nm, and a grain size in the dielectric layer is between 3 nm and 30 nm using only routine skill in the art.
In regards to claim 17, claim 17 is drawn to a product/device, however claim 17 appears to recite process/method limitations that do not appear to materially affect the structural elements of the product/device. Therefore, claim 17 will be interpreted as a “product by process” claim.
A "product by process" claim is directed to the final product per se, no matter how it is actually made. In re Hirao and Sato et al., 190 USPQ 15, 17 (CCPA 1976) (footnote 3); see also In re Brown and Saffer, 173 USPQ 685 (CCPA 1972); In re Luck and Gainer, 177 USPQ 523 (CCPA 1973); In re Fessmann, 180 USPQ 324 (CCPA 1974); and In re Marosi et al., 218 USPQ 289 (CAFC 1983). It is the patentability of the final product per se which must be determined in a "product by process" claim, and not the patentability of the process, and that an old or obvious product, produced by a new method is not patentable as a product, whether claimed in "product by process" claims or not. Id. Note that Applicant has the burden of proof in such cases. Id. Furthermore, “[e]ven though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process.” In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985) (citations omitted).
Specifically, the limitations “wherein the dielectric layer is deposited to an initial thickness that is greater than 6 nm and less than or equal to 15 nm and is etched to a final thickness that is less than or equal to 6 nm” appear to be process/method limitations. For the purposes of examination, only the device limitations will be examined on the merits, i.e. the limitation in question will be read as “wherein the dielectric layer has a thickness that is less than or equal to 6 nm.”
Further in regards to claim 17, the combination of Alzate, Sharma, and Nakanishi teaches the method discussed above in addressing claim 16. Nakanishi further teaches the limitations wherein the dielectric layer has a specific range of thickness [0146]. It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by Alzate with the aforementioned limitations taught by Nakanishi to affect storage capacitance characteristics of a memory device (Nakanishi [0044], [0146]).
The combination of Alzate, Sharma, and Nakanishi appears to be silent as to the limitation wherein a thickness of the dielectric layer is less than or equal to 6 nm; however, where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. See MPEP §2144.05 II A; see also In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). In the case at hand, Nakanishi teaches the general conditions of claim 9. Specifically, Nakanishi teaches that the thickness of a capacitor dielectric and the grain size of a capacitor are variables that have the effect of changing capacitor dielectric density and therefore storage capacitance ([0044], [0146]). Therefore, one having ordinary skill in the at the time the application at hand would find it obvious to discover the optimum or workable ranges wherein a thickness of the dielectric layer is less than or equal to 6 nm using only routine skill in the art.
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Alzate, Sharma, and Nakanishi as applied to claim 16 above, and further in view of Lee.
In regards to claim 20, the combination of Alzate, Sharma, and Nakanishi teaches the limitations discussed above in addressing claim 1. The combination of Alzate, Sharma, and Nakanishi appears to be silent as to, but does not preclude, the limitations wherein the dielectric layer comprises at least one selected from fluorine (F) and chloride (Cl). Lee teaches the limitations wherein the dielectric layer comprises at least one selected from fluorine (F) and chloride (Cl) (col. 5/lns. 58-67). It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by combination of Alzate, Sharma, and Nakanishi with the aforementioned limitations taught by Lee to reduce current leakage (Lee col. 5/lns. 58-67).
The combination of Alzate, Sharma, Nakanishi, and Lee appears to be silent as to the limitations wherein a content of at least one selected from F and Cl in the dielectric layer is between 0.01 at% and 15 at%; however, where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. See MPEP §2144.05 II A; see also In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). In the case at hand, Lee teaches the general conditions of claim 2. Specifically, Lee teaches that the content of F or Cl in a capacitor dielectric is a variable that, when changed, has the effect of changing the leakage current of a capacitor (col. 5/lns. 58-67). Therefore, one having ordinary skill in the at the time the application at hand would find it obvious to discover the optimum or workable ranges wherein a content of at least one selected from F and Cl in the dielectric layer is between 0.01 at% and 15 at% using only routine skill in the art.
Claim(s) 3-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Alzate and Nakanishi as applied to claim 1 above, and further in view of Kim (US 2020/0020780 A1; hereinafter Kim).
In regards to claim 3, the combination of Alzate and Nakanishi teaches the limitations discussed above in addressing claim 1. The combination of Alzate and Nakanishi appears to be silent as to, but does not preclude, the limitations further comprising at least one of a lower interface layer between the dielectric layer and the lower electrode, and an upper interface layer between the dielectric layer and the upper electrode, wherein a thickness of each of the lower interface layer and the upper interface layer is less than or equal to 1.5 nm.
Kim teaches, e.g. in figs. 2, the limitations further comprising at least one of a lower interface layer between the dielectric layer and the lower electrode, and an upper interface layer (204) between the dielectric layer (202) and the upper electrode (203) [0058], wherein a thickness of each of the lower interface layer and the upper interface layer is less than or equal to 1.5 nm [0069]. It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by the combination of Alzate and Nakanishi with the aforementioned limitations taught by Kim to reduce current leakage of a capacitor in a memory device (Kim [0040]).
In regards to claim 4, the combination of Alzate, Nakanishi, and Kim teaches the limitations discussed above in addressing claim 3. Kim further teaches the limitations wherein the at least one of the lower interface layer and the upper interface layer comprises at least one selected from tantalum (Ta), antimony (Sb), molybdenum (Mo), cobalt (Co), niobium (Nb), copper (Cu), nickel (Ni), vanadium (V), tungsten (W), an oxide thereof, and a nitride thereof [0058]. It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by the combination of Alzate and Nakanishi with the aforementioned limitations taught by Kim to reduce current leakage of a capacitor in a memory device (Kim [0040]).
In regards to claim 5, the combination of Alzate and Nakanishi teaches the limitations discussed above in addressing claim 1. The combination of Alzate and Nakanishi appears to be silent as to, but does not preclude, the limitations wherein the dielectric layer is a multiple layer including a first dielectric layer and a second dielectric layer, which are stacked on each other. Kim teaches the limitations wherein the dielectric layer (202) is a multiple layer (202A-202C) including a first dielectric layer (e.g. (202A)) and a second dielectric layer (e.g. (202C)), which are stacked on each other (figs. 2). It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by the combination of Alzate and Nakanishi with the aforementioned limitations taught by Kim to reduce current leakage of a capacitor in a memory device (Kim [0040]).
In regards to claim 6, the combination of Alzate, Nakanishi, and Kim teaches the limitations discussed above in addressing claim 5. Kim further teaches the limitations wherein the dielectric layer further comprises an insertion layer (e.g. (202B)) which is between the first dielectric layer (e.g. (202A)) and the second dielectric layer (e.g. (202C)), and which includes a different material from materials for forming the first dielectric layer and the second dielectric layer [0057]. It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by the combination of Alzate and Nakanishi with the aforementioned limitations taught by Kim to reduce current leakage of a capacitor in a memory device (Kim [0040]).
In regards to claim 7, the combination of Alzate, Nakanishi, and Kim teaches the limitations discussed above in addressing claim 6. Kim further teaches the limitations wherein the insertion layer (e.g. (202B)) comprises at least one selected from aluminum oxide (Al2O3), yttrium oxide (Y2O3), niobium oxide (Nb2O5), vanadium oxide (V2O5), and lanthanum oxide (La2O3) [0057]. It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by the combination of Alzate and Nakanishi with the aforementioned limitations taught by Kim to reduce current leakage of a capacitor in a memory device (Kim [0040]).
In regards to claim 8, the combination of Alzate and Nakanishi teaches the limitations discussed above in addressing claim 1. The combination of Alzate and Nakanishi appears to be silent as to, but does not preclude, the limitations wherein the dielectric layer comprises at least one selected from zirconium oxide (ZrO2), hafnium oxide (HfO2), and titanium oxide (TiO2). Kim teaches the limitations wherein the dielectric layer comprises at least one selected from zirconium oxide (ZrO2), hafnium oxide (HfO2), and titanium oxide (TiO2) (figs. 2) [0057]. It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by the combination of Alzate and Nakanishi with the aforementioned limitations taught by Kim to reduce current leakage of a capacitor in a memory device (Kim [0040]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CALVIN Y CHOI whose telephone number is (571)270-7882. The examiner can normally be reached M-F 8-4 (Pacific Time).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William (Blake) Partridge can be reached at (571) 270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
CALVIN CHOI
Patent Examiner
Art Unit 2812
/CALVIN Y CHOI/Patent Examiner, Art Unit 2812
Prosecution Insights