DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
New corrected drawings in compliance with 37 CFR 1.121(d) are required in this application because the waveguide item 220 as described in par. 0052 of the published application is not labeled in the specification. Furthermore, as seen in the original filed or the amended drawings filed on 4/21/26 the electrode assembly is not over, partially or fully, the pn junction 299, it is merely at a higher level. Examiner notes that the drawings of figs. 1 and 6 show only overlapping N or P regions and not a junction as claimed. For examiner purposes examiner shall examine based on the drawings as presented by the applicant.
Applicant is advised to employ the services of a competent patent draftsperson outside the Office, as the U.S. Patent and Trademark Office no longer prepares new drawings. The corrected drawings are required in reply to the Office action to avoid abandonment of the application. The requirement for corrected drawings will not be held in abeyance.
Response to Arguments
Applicant’s arguments filed on 4/21/26 have been fully considered but they are not persuasive. Regarding applicant’s argument, “Applicant respectfully submits that Liu does not disclose the newly added limitation that "the dielectric gap being located between the two metal layers and thereby separating the two metal layers”, Examiner respectfully asserts that the dielectric material of 403 is between the metal layers as seen in at least fig. 5. Moreover, par. 0058 teaches that insulator (dielectric) is between either 507 and 508 or between each of layer 508 and layer 507 to form a capacitance region.
Allowable Subject Matter
Claims 7 – 9, 11 and 12 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
The allowable subject matter as indicated in the office action mailed on 1/28/26 has been placed into base claim 7.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 – 6 and 15 – 18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Liu et al. (U.S. PG Pub. # 2020/0073197 A1).
In Re claim 1, ‘197 teaches an optical modulator semiconductor device comprising: at least one p-n junction disposed on a substrate, the at least one p-n junction comprising a positive doped region (502) and a negative doped region (501), the at least one p-n junction being optically connected to at least one waveguide (pars. 0056, fig. 5); and an electrode assembly disposed at least partially over (interpreted as higher than as the drawings do not show the electrodes over the junction) the at least one p-n junction, the electrode assembly comprising a first metal layer (507) and a second metal layer (508), a first electrical signal pathway (509) being formed between the two metal layers at least partially by a dielectric gap (material of 403 between 507 and 508, fig. 5, par. 0058), the dielectric gap being located between the two metal layers and thereby separating the two metal layers (as seen in fig. 5), and a second electrical signal pathway (at least one of 509, fig. 5) being formed by a metal contact from the electrode assembly to one of the positive doped region and the negative doped region, when in use, alternating current (AC) signals being propagated through the first signal pathway and direct current (DC) signals being propagated through the second signal pathway (fig. 1).
Furthermore, the patentability of an apparatus depends only on the claimed structural limitations. ‘197 teaches a structure that is substantially identical to that of the claimed invention, therefore the claimed properties or functions are presumed to be inherent. The burden is on the applicant to show that the ‘197 device does not possess these functional characteristics. See MPEP 2112.01.
Alternatively, In Re claim 1, ‘197 teaches an optical modulator semiconductor device comprising: at least one p-n junction disposed on a substrate, the at least one p-n junction comprising a positive doped region (502) and a negative doped region (501), the at least one p-n junction being optically connected to at least one waveguide (pars. 0056, fig. 5); and an electrode assembly disposed at least partially over (interpreted as higher than as the drawings do not show the electrodes over the junction) the at least one p-n junction, the electrode assembly comprising a first metal layer (left 507 or 508) and a second metal layer (right 507 or 508, respectively), a first electrical signal pathway (capacitance, par. 0058) being formed between the two metal layers at least partially by a dielectric gap (material of 403, par. 0058), the dielectric gap being located between the two metal layers and thereby separating the two metal layers (as seen in fig. 5), and a second electrical signal pathway (at least one of 509, fig. 5) being formed by a metal contact from the electrode assembly to one of the positive doped region and the negative doped region, when in use, alternating current (AC) signals being propagated through the first signal pathway and direct current (DC) signals being propagated through the second signal pathway (fig. 1).
In Re claims 2 – 6, ‘197 teaches wherein the first electrical signal pathway is configured to support the propagation of AC signal and the second electrical signal pathway is configured to support the propagation of DC signal (fig. 1, par. 0058);
wherein the at least one p-n junction includes a plurality of p-n junctions arranged in series (par.0048);
wherein the dielectric gap of the first signal pathway effectively forms a capacitor using a parasitic capacitance effect (par. 0058);
wherein: the first signal pathway includes a plurality of first signal pathways; and the second signal pathway includes a plurality of second signal pathways (4 pathsways of each of 509 , fig. 5);
wherein: at least some of the first electrical signal pathways are formed by metallic contacts forming a sub-group of first electrical signal pathways that support AC signals (figs. 1, 5, 12A 12B); the sub-group of the first electrical signal pathways is spatially distributed according to a distribution function; and the first metal layer of the electrode assembly effectively forms a resistor (all material has resistance to some degree).
In Re claim 15, ‘197 teaches an optical modulator semiconductor device comprising: a substrate (401); at least one p-n junction disposed on the substrate, the at least one p-n junction comprising a positive doped portion (502) and a negative doped portion (501); a first metal layer disposed (507) at least partially over and in contact with one of the positive doped portion and the negative doped portion (fig. 5); and a second metal layer (508) disposed at least partially over the first metal layer, a first portion of the second metal layer comprising a metal contact (one of 509) connecting the second metal layer to the first metal layer, a second portion of the second metal layer being electrically connected (par. 0058) to the first metal layer through a dielectric gap (fig. 5),
the dielectric gap being located between the two metal layers and thereby separating the two metal layers (fig. 5).
In Re claims 16 – 18, ‘197 teaches the first metal layer is formed from a plurality of separated metal contacts (509, or each 507 of 310, 320 as they connect at A-A fig. 3); the first portion of the second metal layer is in contact with one of the plurality of separated metal contacts (figs. 3, 5); and the second portion of the second metal layer is in contact with an other one of the plurality of separated metal contacts (figs. 3 and 5);
wherein the at least one p-n junction includes a plurality of p-n junctions arranged in series (fig. 3);
wherein the dielectric gap of the second signal pathway effectively forms a capacitor using a parasitic capacitance effect (par. 0058).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHAD SMITH whose telephone number is (571)270-1294. The examiner can normally be reached M-F 7:30 - 5.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Uyen-Chau Le can be reached at 1-571-272-2397. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CHAD H SMITH/Primary Examiner, Art Unit 2874
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