DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, “an electrode assembly disposed at least partially over the at least one p-n junction” must be shown or the feature(s) canceled from the claim(s). No new matter should be entered. Examiner notes that the drawings of figs. 1 and 6 show only overlapping N or P regions and not a junction as claimed. For examiner purposes examiner shall examine base on the drawings as presented by the applicant.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claim 7 is objected to because of the following informalities: “first third” in line 14 should read “third”. Appropriate correction is required.
Claims 13 and 14 are objected to because of the following informalities: “the impedance component” “an impedance component” . Appropriate correction is required.
Allowable Subject Matter
Claim 14 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: The prior art of record, taken alone or in combination, fails to disclose or render obvious a device comprising, among other things, an inductor as claimed. The closest relevant prior art of record, Liu et al. (U.S. PG Pub. # 2020/0073197 A1), fails to teach or suggest an inductor as claimed.
Thus, with no teaching from the prior art, and without the benefit of applicant's teachings, there is no motivation for one of ordinary skill in the art to combine/modify the prior art of record in a manner so as to create the claimed invention.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 – 13 and 15 – 18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Liu et al. (U.S. PG Pub. # 2020/0073197 A1).
In Re claim 1, ‘197 teaches An optical modulator semiconductor device comprising: at least one p-n junction disposed on a substrate, the at least one p-n junction comprising a positive doped region (502) and a negative doped region (501), the at least one p-n junction being optically connected to at least one waveguide (pars. 0056, fig. 5); and an electrode assembly disposed at least partially over (interpreted as higher than as the drawings do not show the electrodes over the junction) the at least one p-n junction, the electrode assembly comprising a first metal layer (507) and a second metal layer (508), a first electrical signal pathway (509) being formed between the two metal layers at least partially by a dielectric gap (403, fig. 5), and a second electrical signal pathway (509, fig. 5) being formed by a metal contact from the electrode assembly to one of the positive doped region and the negative doped region, when in use, alternating current (AC) signals being propagated through the first signal pathway and direct current (DC) signals being propagated through the second signal pathway (fig. 1).
Furthermore, the patentability of an apparatus depends only on the claimed structural limitations. ‘197 teaches a structure that is substantially identical to that of the claimed invention, therefore the claimed properties or functions are presumed to be inherent. The burden is on the applicant to show that the ‘197 device does not possess these functional characteristics. See MPEP 2112.01.
In Re claims 2 – 6, ‘197 teaches wherein the first electrode assembly is configured to support the propagation of AC signal and the second electrode assembly is configured to support the propagation of DC signal (fig. 1);
wherein the at least one p-n junction includes a plurality of p-n junctions arranged in series (par.0048);
wherein the dielectric gap of the first signal pathway effectively forms a capacitor using a parasitic capacitance effect (par. 0058);
wherein: the first signal pathway includes a plurality of first signal pathways; and the second signal pathway includes a plurality of second signal pathways (4 pathsways of each of 509 , fig. 5);
wherein: at least some of the second electrical signal pathways are formed by metallic contacts forming a sub-group of first electrical signal pathways that support AC signals (figs. 1, 5, 12A 12B); the sub-group of the second electrical signal pathways is spatially distributed according to a distribution function; and the first metal layer of the electrode assembly effectively forms a resistor (all material has resistance to some degree).
In Re claim 7, ‘197 teaches an optical modulator semiconductor device comprising: at least one p-n junction disposed on a substrate, the at least one p-n junction comprising a positive doped region (502) and a negative doped region (501), the at least one p-n junction being optically connected to at least one waveguide (par. 0056); a first electrode assembly disposed at least partially over the at least one p-n junction, the first electrode assembly comprising a first metal layer (507, of 121) and a second metal layer (508 of 121), with a first electrical signal pathway being formed between the two metal layers at least partially by a dielectric gap (403, fig. 5), and a second electrical signal pathway (509) being formed by a metal contact from the first electrode assembly to one of the positive doped region and the negative doped region (fig. 5); a second electrode assembly disposed in proximity to the first electrode assembly, the second electrode assembly comprising a third metal layer (507 of 122) and a fourth metal layer (508 or 122), the two metal layers being connected via a metal (509) contact forming a third electrical signal pathway; and an impedance element (503 or 504 as all material has impedance to some degree) connecting the first metal layer of the first electrode assembly and the first third metal layer of the second electrode assembly forming a fourth electrical signal pathway, when in use, alternating current (AC) signals being propagated through the first and second signal pathways and direct current (DC) signals being propagated through the third and fourth signal pathways (figs. 1, 10).
Furthermore, the patentability of an apparatus depends only on the claimed structural limitations. ‘197 teaches a structure that is substantially identical to that of the claimed invention, therefore the claimed properties or functions are presumed to be inherent. The burden is on the applicant to show that the ‘197 device does not possess these functional characteristics. See MPEP 2112.01.
In Re claims 8 and 9, ‘197 teaches wherein the first electrode assembly is configured to support the propagation of AC signal and the second electrode assembly is configured to support the propagation of DC signal (fig. 1);
wherein the at least one p-n junction includes a plurality of p-n junctions (125) arranged in series (figs. 3, 11, 13).
Alternatively, In Re claim 7, ‘197 teaches an optical modulator semiconductor device comprising: at least one p-n junction disposed on a substrate, the at least one p-n junction comprising a positive doped region (502) and a negative doped region (501), the at least one p-n junction being optically connected to at least one waveguide (par. 0056); a first electrode assembly disposed at least partially over the at least one p-n junction, the first electrode assembly comprising a first metal layer (507 of 1021) and a second metal layer (508 of 1021), with a first electrical signal pathway being formed between the two metal layers at least partially by a dielectric gap (403, fig. 5), and a second electrical signal pathway (509) being formed by a metal contact from the first electrode assembly to one of the positive doped region and the negative doped region (fig. 5); a second electrode assembly disposed in proximity to the first electrode assembly, the second electrode assembly comprising a third metal layer (507 of 122) and a fourth metal layer (508 of 122), the two metal layers being connected via a metal (509) contact forming a third electrical signal pathway; and an impedance element (503 or 504 as all material has impedance to some degree) connecting the first metal layer of the first electrode assembly and the third metal layer of the second electrode assembly forming a fourth electrical signal pathway (fig. 5), when in use, alternating current (AC) signals being propagated through the first and second signal pathways and direct current (DC) signals being propagated through the third and fourth signal pathways (figs. 1, 11, 12 A, 12B, 13).
Furthermore, the patentability of an apparatus depends only on the claimed structural limitations. ‘197 teaches a structure that is substantially identical to that of the claimed invention, therefore the claimed properties or functions are presumed to be inherent. The burden is on the applicant to show that the ‘197 device does not possess these functional characteristics. See MPEP 2112.01.
In Re claims 8 – 14, ‘197 teaches wherein the first electrode assembly is configured to support the propagation of AC signal and the second electrode assembly is configured to support the propagation of DC signal (fig. 1);
wherein the at least one p-n junction includes a plurality of p-n junctions (125) arranged in series (figs. 3, 11, 13);
wherein for both electrode assemblies: the first metal layer is formed from a plurality of separated metal contacts; the first portion of the second metal layer is in contact (at least indirectly through oxide 403 or the entire structure) with one of the plurality of separated metal contacts; and the second portion of the second metal layer is in contact (at least indirectly through oxide 403 or the entire structure) with an other one of the plurality of separated metal contact;
the first signal pathway includes a plurality of first signal pathways (along each area of an occurring 125); the second signal pathway includes a plurality of second signal pathways; the third signal pathway includes a plurality of third signal pathways; and the fourth signal pathway includes a plurality of fourth signal pathways (figs. 12A, 12B).
each one of the plurality of first signal pathways is defined through a corresponding one of the plurality of p-n junctions; each one of the plurality of second signal pathways is defined through a corresponding one of the plurality of p-n junctions; each one of the plurality of third signal pathways is defined through a corresponding one of the plurality of p-n junctions; and each one of the plurality of fourth signal pathways is defined through a corresponding one of the plurality of p-n junctions (fig. 5 is reproduced along each 125 of figs .11 and 13);
at least some of the first electrical signal pathways are formed by metallic contacts forming a sub-group of first electrical signal pathways that support AC signals (figs. 12A, 12B); the sub-group of the first electrical signal pathways is spatially distributed according to a distribution function (inherent during design an manufacture); and the impedance component that connects the first metal layer of the first electrode assembly and the third metal layer of the second electrode assembly forming a fourth electrical signal pathway is a resistor (5 and 12A, 12B).
In Re claim 15, ‘197 teaches an optical modulator semiconductor device comprising: a substrate (401); at least one p-n junction disposed on the substrate, the at least one p-n junction comprising a positive doped portion (502) and a negative doped portion (501); a first metal layer disposed (507) at least partially over and in contact with one of the positive doped portion and the negative doped portion (fig. 5); and a second metal layer (508) disposed at least partially over the first metal layer, a first portion of the second metal layer comprising a metal contact (one of 509) connecting the second metal layer to the first metal layer, a second portion of the second metal layer being electrically connected (at least through another of 509) to the first metal layer through a dielectric gap (509 extends through 403 between the layers, fig. 5).
In Re claims 16 – 18, ‘197 teaches the first metal layer is formed from a plurality of separated metal contacts (509, or each 507 of 310, 320 as they connect at A-A fig. 3); the first portion of the second metal layer is in contact with one of the plurality of separated metal contacts (figs. 3, 5); and the second portion of the second metal layer is in contact with an other one of the plurality of separated metal contacts (figs. 3 and 5);
wherein the at least one p-n junction includes a plurality of p-n junctions arranged in series (fig. 3);
wherein the dielectric gap of the second signal pathway effectively forms a capacitor using a parasitic capacitance effect (par. 0058).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHAD SMITH whose telephone number is (571)270-1294. The examiner can normally be reached M-F 7:30 - 5.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Uyen-Chau Le can be reached at 1-571-272-2397. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/CHAD H SMITH/ Primary Examiner, Art Unit 2874