1DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 6-7 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Behzad (US 6,696,892 B1 hereinafter Behzad).
As to claim 1, Behzad discloses in Figs. 4-5, 11-14, 22-25, 26-28, col. 3 lines 25-60, col. 4 lines 10-40, col. 5 lines 50-60, col. 6 lines 1-10, an attenuator circuit (programmable gain attenuator circuit in Figs. 4-5, col. 3 lines 1-20), comprising:
a first circuit (resistive ladder/divider in Figs. 4-5, col. 3 lines 25-35) having a first input (input 401/501 in Figs. 4-5, col. 3 lines 25-35), a first output (tap junction/output from divider in Figs. 4-5, col. 3 lines 25-35), a first resistor (R405 in Figs. 4-5, col. 3 lines 25-35) coupled between the first input and the first output (coupled as divider in Figs. 4-5, col. 3 lines 25-35), and a second resistor (R417 in Figs. 4-5, col. 3 lines 25-35) coupled between the first output and a reference node (to ground/reference node in Figs. 4-5, col. 3 lines 25-35);
a second circuit (buffer amplifiers in Figs. 11-14, col. 4 lines 10-20) having a second input (input to buffers U1105 and/or U1113 in Figs. 11-14, col. 3 lines 40-50), a second output (output from buffers in Figs. 11-14, col. 3 lines 40-50), and a first amplifier circuit (U1105, U1113 as first amplifier circuit in Figs. 11-14, col. 4 lines 10-20), the second input coupled to the first output (tap to buffer input in Figs. 4-5, col. 3 lines 40-50), and the first amplifier circuit coupled between the second input and the second output (coupled as buffer in Figs. 11-14, col. 4 lines 10-20); and
a third circuit (gain control with selectable amps in Figs. 11-14, 22-25, col. 5 lines 50-60) having a third input (input from second output in Figs. 11-14, col. 4 lines 10-20), a third output (final output in Figs. 11-14, col. 4 lines 10-20), a second amplifier circuit (U1307, U1311 in Fig. 13, col. 4 lines 30-40), and a gain control circuit (switches and sliding window logic in Figs. 22-25, col. 5 lines 50-60), the third input coupled to the second output (coupled via switches in Figs. 11-14, col. 4 lines 10-20), the second amplifier circuit coupled between the third input and the third output (coupled as followers in Fig. 13, col. 4 lines 30-40), and the gain control circuit configured to adjust a gain of the second amplifier circuit (adjusts via selection in Figs. 22-25, col. 6 lines 1-10).
As to claim 2, Behzad discloses the attenuator circuit of claim 1, wherein an input impedance of the second circuit is greater than a sum of resistances of the first and second resistors (buffer amps high impedance >> resistor sums in col. 3 lines 40-50).
As to claim 6, Behzad discloses the attenuator circuit of claim 5, wherein the gain control circuit is digitally programmable to adjust the gain of the second amplifier circuit (digital logic gates for control in col. 5 lines 50-60: "A daisy-chained OR and XOR gate logic controls the sliding window").
As to claim 7, Behzad discloses the attenuator circuit of claim 1, wherein the gain control circuit is digitally programmable to adjust the gain of the second amplifier circuit (digital logic gates for control in col. 5 lines 50-60: "A daisy-chained OR and XOR gate logic controls the sliding window").
Claims 18-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ricca et al. (US 2004/0177293 A1 hereinafter Ricca).
As to claim 18, Ricca discloses in ¶0032, ¶0037-0038, ¶0048, ¶0056-0057, ¶0069, a method of fabricating an electronic device, the method comprising:
installing first and second electronic devices into respective first and second sockets of a handler interface board (HIB) (DUTs via pogo pins/sockets; ¶0037-0038: "selectively couples... to an array of pogo pin outputs 130");
adjusting a channel attenuator gain of respective first and second attenuator circuits of the HIB (programmable attenuators/gains; ¶0048, ¶0056-0057); and
testing an electrical parameter of the first and second electronic devices using first and second time stampers that are connected to the respective first and second attenuator circuits of the HIB (timing tests via TMU; ¶0040, ¶0068-0069).
As to claim 19, Ricca discloses in ¶0057, the method of claim 18, further comprising:
again adjusting the channel attenuator gain of the respective first and second attenuator circuits of the HIB; and
testing a second electrical parameter of the first and second electronic devices using the first and second time stampers (multiple tests with adjustment; ¶0032: programmable for different tests).
As to claim 20, Ricca discloses in ¶0069, the method of claim 18, further comprising:
installing third and fourth electronic devices into the respective first and second sockets of the HIB;
adjusting the channel attenuator gain of the respective first and second attenuator circuits of the HIB; and
testing an electrical parameter of the third and fourth electronic devices using the first and second time stampers (parallel/multiple DUTs; ¶0069: "four single-ended signals may be sourced in parallel").
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3-5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Behzad (US 6,696,892 B1 hereinafter Behzad) in view of Mullen et al. (US 7,626,474 B2 hereinafter Mullen).
As to claim 3, Behzad discloses in col. 1 lines 10-20, the attenuator circuit of claim 1, except for wherein the attenuator circuit has a current consumption of 0.5 mA or less (low power design implied).
Behzad does not explicitly specify, but Mullen discloses in col. 3 lines 20-60, wherein the attenuator circuit has a current consumption of 0.5 mA or less (passive elements, low current).
Therefore, It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains, to modify the circuit of Behzad and provide low current as taught by Mullen for power-efficient test instrumentation.
As to claim 4, Behzad discloses in col. 6 lines 1-10, the attenuator circuit of claim 1, except for wherein the attenuator circuit has a time constant of 3 ns or less (fast switching for high freq implied).
Behzad does not explicitly specify, but Mullen discloses in col. 3 lines 35-45, wherein the attenuator circuit has a time constant of 3 ns or less (high freq compensation implying fast RC times).
Therefore, It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains, to modify the circuit of Behzad and provide fast time constant as taught by Mullen for high-speed signals.
As to claim 5, Behzad discloses in Fig. 31, the attenuator circuit of claim 1, except for wherein the attenuator circuit has an adjustable signal gain of 0.03 or more and 0.20 or less (fine steps 0.2 dB ~0.023 gain steps, covering range).
Behzad does not explicitly match the range, but Mullen discloses in col. 3 lines 35-45, wherein the attenuator circuit has an adjustable signal gain of 0.03 or more and 0.20 or less (10:1 ~0.1 gain, adjustable).
Therefore, It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains, to modify the circuit of Behzad and provide the gain range as taught by Mullen for typical test attenuation.
Allowable Subject Matter
Claims 11-17 allowed.
Claims 8-10 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
As to claims 8-10, the prior art does disclose wherein: the first amplifier circuit includes a third resistor, a fourth resistor, and a first op-amp, the first op-amp having first and second inputs and an output, the third resistor coupled between the first input of the first op-amp and the first output, the fourth resistor coupled between the first input of the first op-amp and the output of the first op-amp, the second input of the first op-amp coupled to the reference node, and the output of the first op-amp coupled to the third input; and the second amplifier circuit includes a fifth resistor, a sixth resistor, and a second op-amp, the second op-amp having first and second inputs and an output, the fifth resistor coupled between the output of the first op-amp and the first input of the second op-amp, the sixth resistor coupled between the first input of the second op-amp and the output of the second op-amp, the output of the second op-amp coupled to the third output, and the gain control circuit configured to adjust a resistance of the sixth resistor, as recited in claims 8-9; and a second instance of the third circuit connected to the second TS of the test system and having a third input, a third output, a second amplifier circuit, and a gain control circuit, the third input coupled to the second output, the second amplifier circuit coupled between the third input and the third output, and the gain control circuit configured to adjust a gain of the second amplifier circuit, as recited in claim 10; a handler interface board (HIB), having first and second sockets, and first and second attenuator circuits, and a first time stamper (TS) connected to the first socket; and a second TS connected to the second socket; as recited in claims 1-17
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TUNG X NGUYEN whose telephone number is (571)272-1967. The examiner can normally be reached 10:30am-6:30pm M-F.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Judy Nguyen can be reached at 571-272-2258. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/TUNG X NGUYEN/ Primary Examiner, Art Unit 2858 12/13/2025