Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 1/13/2026 has been entered.
Response to Arguments
Applicant’s arguments, see pgs. 7-12, filed 1/13/2026, with respect to the rejection(s) of claim(s) 1-16 and 18-21 under 102/103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Trock (US Patent No. 10955472).
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 13-16, 18, and 20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 13, lines 5-6 state: “supply power from a first power domain to functional logic and from a second power domain to self-testing logic and to second self-testing logic.” Lines 10-11 state: “perform a functional operation using the functional logic and the second self-testing logic.” There is no indication in the written disclosure that a functional operation can be performed jointly with functional logic within a primary (or always-on, or functional) power domain and with any kind of self-testing logic that receives power from a different secondary (or lesser-on or self-testing) power domain. Instead throughout the specification a functional operation is only disclosed as being performed solely by functional logic or by functional logic, conjointly with other elements within the primary (or always-on or functional) power domain (for example, para. 132).
Claim 20 recites similar new matter. Claims 14-16 and 18 are rejected at least by their dependency on claim 13.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 6, 8, 10, 12, and 21-23 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Trock (US Patent No. 10955472).
Regarding claim 1, Trock teaches:
A system-on-a-chip (SoC), comprising:
functional logic configured to perform one or more functions; (see fig. 3A, isolation gates 333.)
self-testing logic configured to perform a self-testing operation on the functional logic; (see fig. 3A and col. 9, lines 48-53: In core 300, scan testing can be performed with the first power domain 310 and the second power domain 320 together. For example, in an internal test mode test, the full circuitry in core 300, in both the first power domain 310 and the second power domain 320 is powered on. In the internal test mode, the isolation gates and logic are testable by ATPG [using scan chain 314].)
a plurality of power domains, including a functional power domain coupled to the functional logic and configured to provide power to the functional logic and a self-testing power domain coupled to the self-testing logic and configured to provide power to the self-testing logic; (see fig. 3A, AON Domain 320 is considered to be the functional power domain, coupled to functional logic (isolation gates) 333; PD Domain 310 is considered to be the self-testing power domain, coupled to self-test logic (scan chain) 314.)
second self-testing logic coupled to the self-testing logic and configured to perform the self-testing operation on the functional logic with the self-testing logic, wherein the functional power domain is further coupled to the second self-testing logic and configured to provide power to the second self-testing logic: (see fig. 3A, dedicated wrapper cells in scan chain 324 (considered to be second-self test logic) within AON Domain 320 receive output from isolation gate 333 (functional logic), used to test the functional logic.)
and power control logic configured to control power delivery from the plurality of power domains to the functional logic, self-testing logic and the second self-testing logic and configured to power collapse the self-testing logic. (see fig. 3A, Power Control 330 controls power delivery, which allows it to power collapse self-testing logic (scan chain 314) by powering off power switchable domain 310.)
Regarding claim 2, Trock teaches the system-on-a-chip of claim 1. Trock further teaches:
wherein the plurality of power domains includes a second self-testing power domain, and wherein the self-testing power domain and the second self-testing power domain are included on a same tile of the SoC. (see col. 6, lines 58-61: It is understood that each core can have more than two power domains, and each core can have an additional power-switchable portion in an additional power domain. And see col. 7, lines 4-7: During a test, the always-on domain may contain circuits needed to perform the test, and the power-switchable domains can be powered off depending on the test conditions.)
Regarding claim 3, Trock teaches the system-on-a-chip of claim 1. Trock further teaches:
wherein the functional power domain is an always-on power domain, and wherein the self-testing power domain is a lesser-on power domain. (see fig. 3A, AON Domain 320 is always on, PD Domain is power-switchable, meaning it is lesser-on.)
Regarding claim 6, Trock teaches the system-on-a-chip of claim 1. Trock further teaches:
wherein the functional logic, the self- testing logic, and the second self-testing logic are included on a same tile of the SoC. (see fig. 3A, the functional logic, self-testing logic, and second-self testing logic are all included within core 300.) It is well known in the art that cores do not span over multiple tiles.
Regarding claim 8, Trock teaches the system-on-a-chip of claim 1. Trock further teaches:
The SoC of claim 1, wherein the power control logic configured to power collapse the self-testing logic includes to:
power collapse first self-testing logic of a split design wrapper cell;
power collapse third self-testing logic of a chip clock controller circuit;
power collapse fourth self-testing logic of an always-on wrapper cell;
power collapse fifth self-testing logic of a memory circuit; (see fig. 3A, PD scan compression 312 is considered to be fifth self-testing logic, and is power collapsed by power control 330. Core 300 is considered to be a memory circuit as described in col. 5, lines 1-5: The scan test circuitry is coupled to internal core circuitry for scan testing the internal core circuitry (e.g., … memory).)
or any combination thereof.
Regarding claim 10, Trock teaches the system-on-a-chip of claim 1. Trock further teaches:
chip clock controller circuitry including the functional logic and the self-testing logic, (see fig. 3A, core 300 is considered to be chip clock controller circuitry as described in col. 5, lines 56-60: a core… can include clock tree synthesis.)
wherein the chip clock controller circuitry includes:
power collapsible self-testing logic coupled to the self-testing power domain; (see fig. 3A, core 300 contains power collapsible scan chain 314)
and non-power collapsible logic coupled to the functional power domain, wherein the non-power collapsible logic includes a clamp circuity, a mixer, and a multiplexer. (see fig. 3A, core 300 contains non-power collapsible logic within the functional power domain including clamp circuitry 333.)
Regarding claim 12, Trock teaches the system-on-a-chip of claim 1. Trock further teaches:
a memory circuit including the functional logic and the self-testing logic, (see fig. 3A, Core 300 is considered to be a memory circuit as described in col. 5, lines 1-5: The scan test circuitry is coupled to internal core circuitry for scan testing the internal core circuitry (e.g., … memory).)
wherein the memory circuit includes:
power collapsible self-testing logic coupled to the self-testing power domain; (see fig. 3A, Core 300 contains power collapsible self-testing logic 314 within the self-testing power domain).
and memory logic and multiplexers coupled to the functional power domain. (see fig. 3A, Core 300 contains wrapper cells 324, considered to be memory logic because they are part of a memory circuit. And see col. 9, lines 21-25: test wrapper cells 324 may include… selection circuits… the selection circuits can be multiplexers.)
Regarding claim 21, Trock teaches the system-on-a-chip of claim 1. Trock further teaches:
wherein the functional power domain is separate from the self-testing power domain, and wherein the power control logic is configured to power collapse the self-testing logic while providing power to the functional power domain and to non-power collapsible self-testing logic including the second self-testing logic. (see fig. 3A, PD-domain 310 and AON Domain 320 are separate, and PD domain can be powered off by power control 330, power collapsing self-testing logic (scan chain 314), while providing power to the functional power domain (it is always on) and to second self-testing logic (scan chain 324), which is non-power collapsible as it is in an always-on power domain.)
Regarding claim 22, Trock teaches the system-on-a-chip of claim 1. Trock further teaches:
wherein the second self-testing logic corresponds to a portion of circuity of a wrapper cell and comprises one or more of clamp circuity, a mixer, a multiplexer, or inverter circuity. (see fig. 3A, second self testing logic corresponds to wrapper cell 324, and includes a multiplexer as described in col. 9, lines 21-25: test wrapper cells 324 may include… selection circuits… the selection circuits can be multiplexers.)
Regarding claim 23, Trock teaches the system-on-a-chip of claim 1. Trock further teaches:
wherein the second self-testing logic is not power collapsed with the self-testing logic. (PD domain can be powered off by power control 330, power collapsing self-testing logic (scan chain 314), while providing power to the functional power domain (it is always on) and to second self-testing logic (scan chain 324), therefore it is not power-collapsed with the self-testing logic.)
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Trock in view of Acharya (US Publication No. 20220043653).
Regarding claim 4, Trock teaches the system-on-a-chip of claim 1. Trock further teaches:
wherein the functional power domain is a … power domain, and wherein the self-testing power domain is a collapsible design-for- testing (DFT) power domain. (fig. 3A, core 300 includes functional power domain 320 and collapsible self-test power domain 310. The self-test power domain is considered to be a DFT power domain because the core operates based on DFT principles as disclosed in col. 6, lines 4-5: Each such core can be equipped with DFT (design for testability) logic and components.)
However, Trock does not explicitly disclose that the functional power domain is collapsible. In the analogous art of power domains, Acharya teaches:
[Functional logic other than memory are placed in individual] … collapsible power domains. (see fig. 12 various processing blocks such as A 212a and para 27: other components with power collapsible domains (e.g., blocks 212).
It would have been obvious to one of ordinary skill in the art, having the teachings of Trock and Acharya before them, before the effective filing date of the instant application, to incorporate placing individual processing blocks in their own power collapsible domains (Acharya) into the testing system taught by Trock, to allow for benefits such as: increased power efficiency (Acharya, para. 8).
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Trock in view of Pugliesi-Conti (US Publication No. 2010/0011264).
Regarding claim 2, Trock teaches the system-on-a-chip of claim 1. Trock further teaches:
wherein the plurality of power domains includes no more than one self-testing power domain for the… [core]. (see fig. 3A, core 300 contains only one self-testing power domain 310.)
However, Trock does not explicitly disclose that there is only one core in the system-on-a-chip. In the analogous art of computer operations, Pugliesi-Conti teaches:
[the system-on-a-chip contains just one core] (see para. 21: the multi-clock system-on-chip D comprises only one core.)
It would have been obvious to one of ordinary skill in the art, having the teachings of Trock and Pugliesi-Conti before them, before the effective filing date of the instant application, to incorporate just having a singular core into the testing system taught by Trock, to allow for benefits such as: simplification (Pugliesi-Conti, para. 21).
Allowable Subject Matter
Claims 7, 9, and 11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JACK K BARNETT whose telephone number is (571)270-0431. The examiner can normally be reached M-Th 8-5, F 8-4 EST.
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/JACK KENSINGTON BARNETT/Examiner, Art Unit 2111
/MARK D FEATHERSTONE/Supervisory Patent Examiner, Art Unit 2111