Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement filed 3/13/14 fails to comply with 37 CFR 1.98(a)(2), which requires a legible copy of each cited foreign patent document; each non-patent literature publication or that portion which caused it to be listed; and all other information or that portion which caused it to be listed. It has been placed in the application file, but the information referred to therein has not been considered as indicated by the strikethrough.
Election/Restrictions
Applicant’s election without traverse of invention I in the reply filed on 2/23/26 is acknowledged.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2, 6, 7, 13, and 17 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 2 and 13 describe the neural network processing circuit as both “local to” and “on chip” with the graphics processor. Applicant’s disclosure appears to equate the terms, rather than describe their distinct requirements, e.g. paragraph 67. While the claim recites these as separate requirements, any neural network processing circuit meeting the requirement of being “on chip”, would appear to inherently be “local to” the graphics processor, whereas the reverse is not necessarily true depending on the scope of “local to”, leaving the separate requirement of being “local to” in addition to “on chip” indefinite.
For purposes of applying prior art, the claim will be interpreted as though both requirements are met by being on chip as in paragraph 67, i.e. “wherein the neural network processing circuit is
Claims 6, 7, and 17 use the term “other, non-texture related neural network processing” which is ambiguous to the point of being indefinite. That is, a first, narrower, interpretation is that the term refers to neural network processing that is not texture related, and a second, broader, interpretation, is that the term refers to any processing which is not texture related neural network processing, leaving the scope indefinite, e.g. a first person of ordinary skill in the art using the first interpretation would reasonably find that performing, for example, conventional texture decompression does not meet the requirement to perform neural network processing that is not texture related, while a second person of ordinary skill in the art would reasonably find that said conventional texture decompression does meet the requirement to perform processing that is not texture related neural network processing.
For purposes of applying prior art, the broader interpretation will be used. Applicant is advised that the first interpretation would be clearly stated as “other neural network processing that is not texture related” and the second interpretation would be clearly stated as “other non-texture related processing”.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6, 12-16, are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication 2019/0096027 A1 (hereinafter Fielding) in view of U.S. Patent Application Publication 2019/0304140 A1 (hereinafter Fuller).
Regarding claim 1, the limitations “A method of operating a graphics processing system, wherein the graphics processing system comprises: a graphics processor comprising a programmable execution unit operable to execute graphics processing programs, wherein the graphics processor, when executing a graphics processing program that includes one or more graphics texturing operations, is operable to issue requests for graphics texture data that is required for the one or more graphics texturing operations to a memory system in which the graphics texture data is stored to cause the required graphics texture data to be fetched into the graphics processor for use by the graphics processing program … the method comprising: when graphics texture data is fetched into the graphics processor, which graphics texture data is fetched into the graphics processor in a first, compressed format … process at least some of the graphics texture data from the first, compressed format in which it is fetched into the graphics processor into a second, uncompressed format for use by the graphics processor” are taught by Fielding (Fielding, e.g. abstract, paragraphs 24-352, describes a computing system including a graphics processing unit (GPU) performing texturing using a texture cache system which decompresses texture data retrieved from system memory in a compressed format. More specifically, Fielding teaches that the GPU includes a shader core performing fragment shading as part of a graphics pipeline, e.g. paragraphs 227-245, where the shader core executes graphics texturing operations, in part, by requesting to sample texture data using the texture mapper, e.g. paragraphs 229, 230, 236, 242, 243, 245, wherein the texture mapper accesses the texels for sampling using the texture cache system, e.g. paragraphs 236, 245, 248, 249. Further, Fielding teaches that the texture cache system fetches compressed texture data into the first texture cache, e.g. paragraphs 44-47, 251, 284-287, allowing the data processing unit to perform decompression and/or format conversion on the fetched compressed texture data to generate and store the texture data in a decompressed format in the second texture cache, e.g. paragraphs 119, 120, 282-288, which is provided to the texture mapper/shader core for completing the graphics texturing operation, e.g. paragraphs 242, 249, 301-312. That is, as claimed, Fielding's graphics processor comprises a programmable execution unit to execute graphics processing programs, i.e. the shader core of the GPU executing shaders, which issues requests for required graphics texture data to a memory system in which the data is stored, causing it to be fetched in a compressed format, and decompressed into a second uncompressed format for use by the graphics processor.)
The limitations “a neural network processing circuit that is operable and configured to execute one or more neural networks to perform neural network processing for the graphics processor, the method comprising: when graphics texture data is fetched into the graphics processor, which graphics texture data is fetched into the graphics processor in a first, compressed format, wherein the first compressed format is a format in which neural network based texture decompression should be performed to decompress the graphics texture data: the neural network processing circuit performing neural network processing to process at least some of the graphics texture data from the first, compressed format in which it is fetched into the graphics processor into a second, uncompressed format for use by the graphics processor” are not explicitly taught by Fielding (As discussed above, Fielding teaches that the texture cache system fetches compressed texture data into the first texture cache, allowing the data processing unit to perform decompression and/or format conversion on the fetched compressed texture data to generate and store the texture data in a decompressed format in the second texture cache. That is, while Fielding’s GPU includes a second processing circuit for processing the texture data from the first compressed format to the second uncompressed format, Fielding does not disclose performing decompression (or format conversion) using a neural network, per se, i.e. Fielding only discusses specific uncompressed texture formats, and does not discuss details of decompression algorithms or compressed texture formats.) However, this limitation is taught by Fuller (Fuller, e.g. abstract, paragraphs 20-77, describes a system for storing and decompressing textures using machine learning models for performing the decompression as an alternative to conventional compression formats. Fuller, e.g. paragraphs 26-28, 44-52, describes a computing system analogous to Fielding, i.e. performing graphics rendering for an application by a GPU accessing textures stored in a compressed format in system main memory, wherein the decompression may be performed at runtime, e.g. paragraphs 25, 33, 47, 49. Further, Fuller teaches that any type of processor can execute the machine learning model to decompress the texture data, e.g. paragraphs 45, 51, and the machine learning models comprise neural networks, e.g. paragraphs 22, 24, 35, 39-43. Finally, Fuller, e.g. paragraphs 21, 34, describes the advantages of using machine learning models for texture compression/decompression, including higher compression ratios relative to conventional compression formats and the capability to recreate upscaled MIP image data in order to reduce the number of MIP chain images that are transmitted.)
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Fielding’s graphics processing system to support Fuller’s machine learning model texture compression format because Fuller teaches that the machine learning model texture compression format has a higher compression ratio and reduces data requirements for MIP textures. In Fielding’s modified system, the data processor 24 in the texture cache system would execute the machine learning model(s) for requested texture(s) compressed using machine learning model(s) analogous to the conventional decompression algorithms for requested texture(s) in Fielding’s unmodified system, thereby corresponding to the claimed neural network processing circuit configured to perform neural network processing to process at least some of the graphics texture from the first, compressed format in which it fetched into the second, uncompressed format for use by the graphics processor, where the first, compressed format should be decompressed using neural network based decompression.
Regarding claim 2, the limitation “wherein the neural network processing circuit is
Regarding claim 3, the limitation “wherein the graphics processor includes a texture mapping system that is operable to manage requests for graphics texture data, and wherein an interface is provided between the texture mapping system and the neural network processing circuit such that the texture mapping system is operable to exchange messages with the neural network processing circuit, the method comprising: the texture mapping system exchanging messages with the neural network processing circuit to control the processing of graphics texture data from the first, compressed format in which it is stored in the memory system into a second, uncompressed format for use by the graphics processor” is taught by Fielding in view of Fuller(Fielding, e.g. paragraphs 236, 248, 303, 305-310, 314-321, 339-341, teaches that the texture mapper 14 includes a texture cache lookup unit which exchanges requests/messages with the texture cache system comprising/controlling the data processor 24, corresponding to the neural network processing circuit in Fielding’s system as modified in view of Fuller as discussed in the claim 1 rejection above. That is, the texture mapper in Fielding’s modified system corresponds to the claimed texture mapper, which has an interface to exchange requests/messages with the neural network processing circuit/data processor 24, which performs the neural network texture decompression as discussed in the claim 1 rejection.)
Regarding claim 4, the limitation “wherein the neural network processing circuit passes the graphics texture data in the second, uncompressed format to the texture mapping system, the texture mapping system then providing the required graphics texture data to the execution unit” is taught by Fielding (Fielding, e.g. paragraphs 248, 287, 305, 310, 314, 341, teaches that the data processor 24, i.e. the claimed neural network processing circuit as discussed above, writes the uncompressed texture data to the second texture cache from which the texture mapper reads the uncompressed texture data for sampling/providing texture data to the share core/execution unit.)
Regarding claim 5, the limitations are similar to those treated in the above rejection(s) and are met by the references as discussed in claims 1, 3, and 4 above, i.e. as discussed in the claim 1 rejection, textures are requested in response to performing texture operations using texture data, which may be texture data stored in the compressed format for which neural network processing should be performed as in Fielding's modified system, and as discussed in the claims 3 and 4 rejections above, the texture mapper receives texture mapping requests/messages from the shader core/execution unit, which cause the texture cache system to fetch and decompress the texture data stored in the compressed format from the system memory and store the uncompressed texture data in the second texel cache for access by the texture mapper to perform the texture sampling operations, corresponding to the claim 5 requirements that the programming execution unit messages the neural network processing circuit to request the required graphics texture, i.e. the request/message is transmitted via the texture mapping unit, causing the neural network processing circuit to decompress the fetched texture data and store the uncompressed data in the second texture cache for access by the texture mapping unit, which further processes and/or otherwise provides the uncompressed data to the shader core for further processing the fragment being shaded.
Regarding claim 6, the limitation “wherein the neural network processing circuit is also operable to perform other, non-texture related neural network processing for the graphics processor” is taught by Fielding (As discussed in the claim 1 rejection above, Fielding’s data processing unit 24, which performs Fuller’s machine learning model texture decompression for textures compressed using machine learning models, also performs conventional decompression and format conversion operations for textures compressed using conventional compression formats and/or stored in a different format than requested by the texture mapping system.)
Regarding claim 12, the limitations are similar to those treated in the above rejection(s) and are met by the references as discussed in claim 1 above.
Regarding claim 13, the limitations are similar to those treated in the above rejection(s) and are met by the references as discussed in claim 2 above.
Regarding claim 14, the limitations are similar to those treated in the above rejection(s) and are met by the references as discussed in claim 3 above.
Regarding claim 15, the limitations are similar to those treated in the above rejection(s) and are met by the references as discussed in claim 4 above.
Regarding claim 16, the limitations are similar to those treated in the above rejection(s) and are met by the references as discussed in claim 5 above.
Claims 7 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication 2019/0096027 A1 (hereinafter Fielding) in view of U.S. Patent Application Publication 2019/0304140 A1 (hereinafter Fuller) as applied to claims 6 and 12 above, and further in view of U.S. Patent Application Publication 2018/0165786 (hereinafter Bourd)
Regarding claim 7, the limitation “wherein the graphics processor is operable to block other, non-texture related neural network processing being performed by the neural network processing circuit, when required, to allow the neural network processing circuit to perform texture related neural network processing, the method comprising controlling scheduling of texture related neural network processing tasks and other non-texture related neural network processing tasks” is not taught by Fielding or Fuller (As discussed in the claims 1 and 6 rejections above, Fielding’s data processing unit 24, which performs Fuller’s machine learning model texture decompression for textures compressed using machine learning models, also performs conventional decompression and format conversion operations for textures compressed using conventional compression formats and/or stored in a different format than requested by the texture mapping system. Neither Fielding or Fuller address scheduling or blocking of other processing, per se, with respect to the data processor 24/neural network processor.) However, this limitation is taught by Bourd (Bourd, e.g. abstract, paragraphs 14-98, describes a GPU including one or more shader cores executing shaders, wherein different shaders have different priorities, and a shader core executing a low priority “host” shader may be preempted to execute a high priority “guest” shader, e.g. paragraphs 16, 17, 20-28. Further, Bourd, e.g. paragraphs 27, 31, 54, 82, teaches that the guest shader can borrow or steal resources of the host shader, where the resources include textures, texture samplers, memory, buffers, etc., i.e. a guest shader preempting a host shader blocks the host shader from continuing to use said resources until the guest shader has completed execution and returns execution to the host shader. If Bourd’s shader prioritization and resource sharing technique was combined with Fielding’s modified system, an exemplary low priority host shader could perform a first texture operation/request causing the data processor 24/neural network processor to perform other processing that is not texture related neural network processing, e.g. conventional texture decompression/format conversion, and an exemplary high priority guest shader could preempt the low priority shader and perform second texture operation(s)/request(s) causing the data processor 24/neural network processor to perform the neural network texture decompression as discussed in the above rejections, which corresponds to the claim 7 requirement of scheduling the two types of processing and blocking non texture related neural network processing in favor of the texture related neural network processing when required.)
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Fielding’s graphics processing system, supporting Fuller’s machine learning model texture compression format, to use Bourd’s shader prioritization and resource sharing technique in order to gain the advantages of asynchronous parallel processing as taught by Bourd, e.g. paragraphs 17-20. As discussed above, in the modified system, an exemplary low priority host shader could perform a first texture operation/request causing the data processor 24/neural network processor to perform other processing that is not texture related neural network processing, e.g. conventional texture decompression/format conversion, and an exemplary high priority guest shader could preempt the low priority shader and perform second texture operation(s)/request(s) causing the data processor 24/neural network processor to perform the neural network texture decompression as discussed in the above rejections, which corresponds to the claim 7 requirement.
Regarding claim 17, the limitations are similar to those treated in the above rejection(s) and are met by the references as discussed in claim 7 above.
Claims 8 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication 2019/0096027 A1 (hereinafter Fielding) in view of U.S. Patent Application Publication 2019/0304140 A1 (hereinafter Fuller) as applied to claims 1 and 12 above, and further in view of U.S. Patent Application Publication 2024/0338555 A1 (hereinafter Kamenetskaya) in view of U.S. Patent Application Publication 2018/0165786 (hereinafter Bourd).
Regarding claim 8, the limitation “wherein the graphics processor is arranged as plural shader cores, and wherein when the programmable execution unit of a particular shader core requires texture related neural network processing to be performed in respect of a graphics texture data that has been fetched into the graphics processor, when there is no respective neural network processing circuit associated with that programmable execution unit available to perform the required texture related neural network processing, the graphics processor attempts to perform the texture related neural network processing using the neural network processing circuit of another shader core" is not taught by Fielding in view of Fuller (Fielding does not address using plural shader cores. Further, while Fuller teaches any processor can execute the machine learning model(s), Fuller does not address one processor accessing another processor or another processor’s resources to execute the model(s).) However, this limitation is taught by Kamenetskaya in view of Bourd (Kamenetskaya, e.g. abstract, paragraphs 26-88, describes a computing system including a GPU comprising a plurality of shader cores executing neural network(s) partitioned into work tasks, wherein the GPU shader cores are able to offload neural network work tasks to another processor in order to improve parallelism and performance. Kamenetskaya, e.g. paragraphs 29-69, describes operation of the system, where the GPU service routine module facilitates data and control exchange between the GPU and NPU processors, allowing work tasks to be selected for offload onto the NPU, which results in performance improvement as shown in figure 7, e.g. paragraphs 31, 79, due to processing tasks in parallel rather than processing all of the tasks sequentially. Further, Kamenetskaya, e.g. paragraph 72, indicates that the GPU may comprise a plurality of shader processors operating in parallel. Bourd, e.g. abstract, paragraphs 14-98, describes a GPU including one or more shader cores executing shaders, wherein different shaders have different priorities, and a shader core executing a low priority “host” shader may be preempted to execute a high priority “guest” shader, e.g. paragraphs 16, 17, 20-28. Further, Bourd, e.g. paragraphs 27, 31, 54, 82, teaches that the guest shader can borrow or steal resources of the host shader, where the resources include textures, texture samplers, memory, buffers, etc., i.e. Fielding’s texture cache system comprising the data processor 24/neural network processor corresponds to one of Bourd’s borrowable resources. Finally, Bourd, e.g. paragraphs 19, 20, 23, 28, teaches that the system uses priority queues and evaluates the host shader’s resources being used in a given shader core when determining which shader core/host shader to preempt with the guest shader, i.e. the scheduler assigns guest shaders to shader cores based in part on whether the shader core has the necessary resources available that the guest shader requires, as in paragraph 28. In combination, Kamenetskaya teaches that a GPU having plural shader cores can offload neural network work tasks to another available neural processor unit to improve performance through parallelism, and Bourd teaches that a GPU scheduling execution of plural shaders executed using plural shader cores in parallel can select a shader core executing a low priority shader for preemption by a higher priority shader requiring use of the shader core’s resources, such that if Fielding’s modified system were combined with Kamenetskaya’s neural network work task offloading and Bourd’s shader prioritization and resource sharing technique, the resulting combined system would teach the claim 8 limitation, i.e. a high priority shader executing on a first shader core could offload texture decompression neural network processing work task(s) as taught by Kamenetskaya, where the offloaded texture decompression neural network processing work task(s) could be assigned to a second shader core executing a lower priority shader, allowing the offloaded texture decompression neural network processing work task(s) to be executed using the second shader core’s resources, as taught by Bourd, wherein said resources include Fielding’s modified texture cache system as in the claim 1 modification above.)
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Fielding’s graphics processing system, supporting Fuller’s machine learning model texture compression format, to use Kamenetskaya’s neural network work task offloading and Bourd’s shader prioritization and resource sharing technique, in order to gain the advantages of asynchronous parallel processing as taught by Kamenetskaya, e.g. paragraphs 31, 79 and Bourd, e.g. paragraphs 17-20. As discussed above, in Fielding’s modified system using Kamenetskaya’s neural network work task offloading and Bourd’s shader prioritization and resource sharing technique, the resulting modified system would include a GPU comprising plural shader cores, and scheduling/preempting shader execution in a manner reading on the claim 8 limitation, i.e. a high priority shader executing on a first shader core could offload texture decompression neural network processing work task(s) as taught by Kamenetskaya, where the offloaded texture decompression neural network processing work task(s) could be assigned to a second shader core executing a lower priority shader, allowing the offloaded texture decompression neural network processing work task(s) to be executed using the second shader core’s resources, as taught by Bourd, wherein said resources include Fielding’s modified texture cache system as in the claim 1 modification above. It is noted that this meets the claim 8 requirement in comparison to the operation of Fielding’s modified system as in the claim 1 rejection, i.e. a given work task in Fielding’s modified system in the claim 1 rejection is potentially required to wait until the data processor 24/neural network processor is available, corresponding to the condition of “no respective neural network processing circuit [being] available”, whereas, in comparison, in the modified system in view of Kamenetskaya and Bourd, said given work task could instead be offloaded, avoiding the requirement to wait until the data processor 24/neural network processor is available.
Regarding claim 18, the limitations are similar to those treated in the above rejection(s) and are met by the references as discussed in claim 8 above.
Claims 9, 10, 19 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication 2019/0096027 A1 (hereinafter Fielding) in view of U.S. Patent Application Publication 2019/0304140 A1 (hereinafter Fuller) as applied to claims 1 and 12 above, and further in view of U.S. Patent Application Publication 2020/0082274 A1 (hereinafter Rossi)
Regarding claim 9, the limitations “wherein the neural network processing circuit is associated with a neural network buffer for storing data for one or more neural networks for execution to perform texture related neural network processing, the method comprising: when a texturing request causes graphics texture data to be fetched into the graphics processor, which graphics texture is fetched into the graphics processor in a first, compressed format, wherein the first, compressed format is a format in which neural network based texture decompression should be used to decompress the graphics texture data such that the neural network processing circuit should perform texture related neural network processing to process the graphics texture data from the first, compressed format in which it is fetched into the graphics processor into a second, uncompressed format for use by the graphics processor: determining whether the neural network or networks required for processing the fetched graphics texture data are already present in the neural network buffer; and when it is determined that the required neural network or networks are not already present in the neural network buffer, causing data for the required neural networks to be loaded into the neural network buffer” are implicitly taught by Fielding in view of Fuller (As discussed in the claim 1 rejection above, in Fielding’s modified system the texel cache system data processor 24 corresponds to the neural network processing circuit performing neural network processing to decompress texture(s) compressed using machine learning model(s). Further, Fuller, e.g. paragraphs 47-51 figure 1, teaches that the trained machine learning model is part of the application data stored in memory, i.e. the machine learning model comprises model data and executable instructions which are stored in the memory prior to execution. One of ordinary skill in the art would understand that Fuller’s exemplary processors executing the machine learning model(s), e.g. paragraphs 45, 49-51, would require that the machine learning model(s) are loaded into memory accessible by the exemplary processor during execution, i.e. the machine learning model(s)/neural network(s) stored with the application in the system hard drive would have to be loaded into CPU memory or GPU memory for execution by the CPU or GPU, which implicitly, if not inherently, requires the additional elements of claim 9, i.e. the machine learning model(s)/neural network(s) to be executed by the texel cache system data processor 24 in Fielding’s modified system for decompressing a compressed texture requiring neural network based decompression would have to be loaded into a memory accessible to the data processor 24/neural network processing circuit prior to execution, corresponding to the claimed neural network buffer. Further, the implicit, if not inherent, requirement that the machine learning model(s)/neural network(s) are loaded into said accessible memory/neural network buffer prior to their execution by the data processor 24, also implicitly, if not inherently, requires checking/determining whether the machine learning model(s)/neural network(s) are loaded into said accessible memory/neural network buffer prior to their execution by the data processor 24, i.e. an attempt to execute a program which is not accessible cannot succeed. While Fuller does not address loading and/or checking whether machine learning model(s) needed for performing machine learning model based decompression for a given texture are stored in the accessible memory/neural network buffer, it is noted that Fielding’s texture cache system already operates under the same principle for processing texture requests with respect to loading and checking whether the texture data, per se, is available for processing in the first or second texture cache, e.g. paragraphs 314-321, 349-352, wherein the texturing operations/threads are “parked” in a parking buffer until the necessary data has been fetched, i.e. in addition to the above noted implicit, if not inherent, requirement for the machine learning model(s)/neural network(s) to be loaded and checked for being loaded within the accessible memory/neural network buffer prior to their execution, analogous to the texture data, per se, Fielding’s parking buffer system already supports loading, checking, and delaying execution of texturing operations/threads until necessary data is loaded/accessible, such that one of ordinary skill in the art would have found it implicit, if not inherent, that in Fielding’s modified system using Fuller’s machine learning model based texture decompression, the machine learning model(s)/neural network(s) used for performing texture decompression could be fetched and/or processed and/or evicted from the cache using Fielding’s parking buffer system to ensure the machine learning model(s)/neural networks are accessible to the data processor 24, which a prerequisite for the data processor 24 performing the machine learning based decompression. In the interest of compact prosecution, Rossi is cited for describing a system performing operations using plural neural network models, including details of storing/loading the neural networks using a memory, i.e. buffer, prior to execution of the neural networks, i.e. the above noted implicit elements of machine learning model execution that Fuller does not explicitly discuss.) However, this limitation is taught by Rossi (Rossi, e.g. abstract, paragraphs 16-76, describes a system for performing machine learning/neural network processing in a computing system including multiple processors, i.e. a CPU, a GPU, and/or a neural processors. Rossi, e.g. paragraphs 56-60, figure 6, teaches that an application using previously compiled neural network model(s) communicates with the neural processor daemon to load said previously compiled neural network model(s) from the storage cache to the memory accessible to the application, and after the neural network model(s) are loaded into the memory, the application is able to invoke commands using the loaded neural network(s), i.e. cause the processor to execute the loaded neural network model(s). That is, as noted above, Rossi teaches the details of machine learning/neural network model execution which are implicitly required by Fuller’s system, in particular that the neural network model must be loaded into a memory accessible by the application/processor executing the neural network model prior to execution thereof.)
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Fielding’s graphics processing system, supporting Fuller’s machine learning model texture compression format, to extend Fielding’s parking buffer system to ensure the machine learning model(s)/neural network(s) are accessible to the data processor 24 prior to their execution because one of ordinary skill in the art would have understood, as explicitly taught by Rossi, that the machine learning model(s)/neural network(s) would have to be in a memory accessible to the data processor as a prerequisite for execution. As discussed above, one of ordinary skill in the art would have recognized that that in order for the data processor 24 to execute the machine learning model(s)/neural network(s) to decompress the texture(s) it is implicitly, if not inherently, required to load and check that the machine learning model(s)/neural network(s) are loaded in the memory accessible to the data processor prior to execution, as well as that Fielding’s parking buffer system already operates under the same principle with respect to the compressed texture data, per se, such that one of ordinary skill in the art would have found it obvious to extend Fielding’s parking buffer system to additionally load and check for the machine learning model(s)/neural networks in the same manner the compressed texture data is handled. Alternately stated, in the modified system, the “texture data” handled by the parking buffer system is expanded to include both the compressed texture data as in the unmodified system, and the machine learning model(s)/neural network(s) required for decompression, such that threads would be “parked” in the parking buffer until both their respective compressed texture data and machine learning model(s)/neural network model(s) have been loaded.
Regarding claim 10, the limitation “wherein when it is determined that the required neural network or networks are not already present in the neural network buffer, the method comprises: prior to loading the data for the required neural networks into the neural network buffer, parking the current texturing request and attempting to process a subsequent texturing request” is taught by Fielding in view of Rossi (As discussed in the claim 9 rejection above, in the modified system, the “texture data” handled by the parking buffer system is expanded to include both the compressed texture data as in the unmodified system, and the machine learning model(s)/neural network(s) required for decompression, such that threads would be “parked” in the parking buffer until both their respective compressed texture data and machine learning model(s)/neural network model(s) have been loaded. That is, as claimed, threads/texturing requests would be parked until all of their texture data, including both the compressed texture data and the neural network(s) are loaded into the memory accessible to the data processor.)
Regarding claims 19 and 20, the limitations are similar to those treated in the above rejection(s) and are met by the references as discussed in claims 9 and 10 above. It is noted that claim 19 is not as narrow as claim 9, which requires determining whether the neural network(s) are loaded and loading the neural network(s) into the neural network buffer which are determined not to be loaded, such that claim 19 may be read on by the combination of Fielding and Fuller alone, but in the interest of compact prosecution it is addressed using the mapping of claim 9 which actually discusses the claimed neural network buffer.
Conclusion
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/ROBERT BADER/Primary Examiner, Art Unit 2611
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