DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on July 13th, 2026, has been entered.
Response to Amendment
Applicant’s Remarks/Arguments filed on July 13th, 2026, have been carefully considered.
Claims 1, 8, 10-12 and 21 have been amended.
Claim 9 has been canceled.
Claims 23-27 have been added as new.
Claims 1-8, 10-14 and 21-27 are currently pending in the instant application.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-14 and 20-21 are rejected under 35 U.S.C. 103 as being unpatentable over Haribhatt et al. [US2023/0359740] in view of Bennett et al. [US2019/0138453] further in view of Cromer et al. [US7,702,789]. Haribhatt teaches code patching for system on a chip. Bennett teaches computer memory content movement. Cromer teaches apparatus system, and method for reassigning a client.
Regarding claim 1, Haribhatt teaches a method comprising:
Booting a system-on-chip (SOC) [Haribhatt paragraph 0028, first lines “…when the SOC 102 is powered up…”];
copying a set of data from a first memory to a second memory during the booting [Haribhatt paragraph 0035, last lines “…the processor 112 may utilize the data directly from the non-volatile memory 108 or may load some or all the patch data to a RAM such as the RAM 110 and or the IRAM 116…”],
wherein the set of data comprises instructions and wherein the instructions are associated with booting [Haribhatt paragraph 0028, middle lines “…may load the firmware code…” and paragraph 0010, most lines “…the firmware code causes the processor to initialize various components at the SOC to prepare the SOC for operation. For example, firmware code may include instructions for initializing various hardware components on the SOC such as various memory devices, various clocks, various processors, various I/O interfaces, and/or the like. The firmware code may also include instructions for performing other initializations, such as for example, launching an operating system (OS) that may handle operation of the SOC after the firmware code is executed…”];
Haribhatt fails to explicitly teach monitoring a progress of the copying of the set of data; receiving a transaction from a processing unit during the copying of the set of data; determining, based on the monitoring, whether to perform the transaction using the set of data as stored in the first memory or the set of data as stored in the second memory; and performing the transaction;
However, Bennett does teach monitoring a progress of the copying of the set of data [Bennett paragraph 0017, last lines ”…depending upon how the progress of the move defines a current state of the move…”];
receiving a transaction from a processing unit during the copying of the set of data [Bennett paragraph 0025, all lines “…A request analysis module 112 may determine whether the request 104 is directed to the content 106 that is to be moved from a source 114 of the computer memory 108 to a destination 116 of the computer memory 108…” and paragraph 0018, all lines “…may provide for continuous operation of a hypervisor (or another device) so that is no pause in the hypervisor functionality during a move, including no interruptions or failure of direct memory access activity…”]; and
determining, based on the monitoring, whether to perform the transaction using the set of data as stored in the first memory or the set of data as stored in the second memory [Bennett paragraph 0026, all lines “…the request analysis module 112 may determine, based on an analysis of a map page table 118, whether the request 104 is directed to the content 106 that is to be moved from the source 114 to the destination 116. The map page table 118 may include an indication of whether the content 106 is located at the source 114, at the destination 116, or is to be moved from the source 114 to the destination 116. In this regard, the request analysis module 112 may determine, by using the page table 118, that a memory region requested by a guest is located successively at the physical source 114, at the address of a reflective copy module 120, and finally at the physical destination 116, and this determination may guide memory requests on behalf of the guest to be performed originally by the source memory, then by the reflective copy module 120 for the duration of the move, and then by the destination memory after the move is complete…”]; and
performing the transaction [Bennett figure 8, feature 816 and 818].
Haribhatt and Bennett are analogous arts in that they both deal with improving memory performance.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to the teachings of Haribhatt’s system-on-chip booting process with Bennett’s teachings of managing the copying process for the benefit of optimizing the computer system performance by moving data to the appropriate tier for best performance while not delaying the use of the memory [Bennett paragraph 0004, first lines “…optimize the computer system performance, content in the computer memory may need to be moved, for example, for re-allocation of the computer memory. For example, content in the computer memory may need to be placed in an appropriate tier of the computer memory. In this regard, there may be situations where the content is to be moved from one physical location to another, without stopping or otherwise delaying the possible users of the computer memory…”].
Haribhatt and Bennett fail to explicitly teach executing the instructions, based on the set of data, before the copying is complete.
However, Cromer does teach executing the instructions, based on the set of data, before the copying is complete [Cromer column 3, lines 45-48 “…The process copy module copies the software process image from the first storage system to a second storage system concurrent with the resumption of execution of the software process…”(The examiner has determined that the concurrent execution of the software would read on the beginning the executing of the software function before the copying is complete since the actions are concurrent neither action has completed.)].
Haribhatt, Bennett, and Cromer are analogous arts in that they both deal with improving the performance of data movement in a memory system.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Haribhatt and Bennett with Cromer’s teachings of the memory being a set of software functions of a software application by being a software process image that would contain both of those items for the benefit of reducing latency by seamlessly performing the copying and execution of the application. [Cromer column 3, lines 2-6 “…the second computation module may begin executing the software process where the first computation module left off, seamlessly moving the execution of the software process from the first computation module to the second computation module…’].
Regarding claim 2, as per claim 1, Bennett teaches the transaction comprises a read request identifying an address and a size of a subset of the set of data [Bennett paragraph [Bennett paragraph 0019, middle lines “…The reflective copy module may advertise an address range of a same size as a page that includes the content, where the page may be moved from the source to the destination…”].
Regarding claim 3, as per claim 1, Bennett teaches the address comprises an address within the second memory [Bennett paragraph 0047, last lines “…In this regard, the page table 118 entry for that logical address is changed to point to the physical destination…”].
Regarding claim 4, as per claim 1, Bennett teaches determining that a subset of the set of data is not available in the second memory [Bennett paragraph 0061, middle lines “…Based on the determination that the content 106 is at the source 114, the processor 602 may fetch, decode, and execute the instructions to perform, based on mapping of the ascertained logical address to a source physical address (e.g., a physical address assigned to the source 114) assigned to the content 106, the request 104 associated with the content 106 using the source 114…” and paragraph 0059, last lines “…based on a determination that the content 106 is not included in the portion of the memory address range 124, the processor 602 may fetch, decode, and execute the instructions to perform the request 104 associated with the content 106 using the source 114…”(Where range reads on a subset.)];
translating an address received from the processing unit to an address corresponding to a location in the first memory [Bennett paragraph 0061, middle lines “…based on mapping of the ascertained logical address to a source physical address (e.g., a physical address assigned to the source 114) assigned to the content 106, the request 104 associated with the content 106 using the source 114…”]; and
accessing the subset of the set of data from the first memory according to the address corresponding to a location in the first memory [Bennett paragraph 0061, middle lines “…Based on the determination that the content 106 is at the source 114, the processor 602 may fetch, decode, and execute the instructions to perform…the request 104 associated with the content 106 using the source 114…”].
Regarding claim 5, as per claim 1, Bennett teaches determining that a subset of the set of data is available in the second memory [Bennett paragraph 0061, last lines “…Based on the determination that the content 106 has been moved from the source 114 to the destination 116, the processor 602 may fetch, decode, and execute the instructions to perform, based on mapping of the ascertained logical address to a destination physical address (e.g., a physical address assigned to the destination 116) assigned to the content 106, the request 104 associated with the content 106 using the destination 116…”]; and
accessing the subset of the set of data from the second memory according to an address received from the processing unit [Bennett paragraph 0059, last lines “…Based on a determination that the content 106 is included in the portion of the memory address range 124, the processor 602 may fetch, decode, and execute the instructions to perform the request 104 associated with the content 106 using the destination 116....”(Where range reads on subset.)]
Regarding claim 6, as per claim 1, Bennett teaches the first memory comprises external memory [Bennett paragraph 0034, middle lines “…The bulk memory may be described as high-capacity memory used in connection with the computer system 110 for bulk storage of large quantities of data, e.g., flash disk…”] and wherein the second memory comprises on-chip random access memory (RAM) [Bennett paragraph 0036, first lines “…such pages may be moved by the reflective copy module 120 into the DRAM…”].
Regarding claim 7, as per claim 1, Bennett teaches sequentially reading contents from a first plurality of addresses of the first memory; and writing the contents to a second plurality of addresses of the second memory in a same order in which the contents were read from the first plurality of addresses [Bennett paragraph 0039, first lines “…The fold may move sequentially through the page 122, copying by reading an item (e.g., a cache line size) of the content 106 from the source 114 and writing it to the destination 116…”].
Regarding claim 8, as per claim 1, Haribhatt teaches the transaction is associated with execution of the instructions, wherein the instructions are associated with a software application [Haribhatt paragraph 0010, last lines “…The firmware code may also include instructions for performing other initializations, such as for example, launching an operating system (OS) that may handle operation of the SOC after the firmware code is executed…”(Where the OS reads on software application.)], and
Bennett teaches wherein the first plurality of addresses correspond to an order in which the set of data is accessed during execution of the software application [Bennett paragraph 0018, most lines “…the apparatuses, methods, and non-transitory computer readable media disclosed herein may provide an operating system (OS), a hypervisor, or another such device, to be able to move content from one physical device to another while the content remains in active use by both code and devices, where the use of the content may migrate from a previous physical location (e.g., a source) to a new physical location (e.g., a destination)…”(Where the OS implies the use of applications and a hypervisor and code when given their BRI reads on applications)].
Regarding claim 10, Haribhatt teaches a system on-chip (SoC) [Haribhatt paragraph 0028, first lines “…when the SOC 102 is powered up…”] comprising:
a central processing unit (CPU) [Haribhatt paragraph 0055, first lines “…he example architecture 600 includes a processor unit 602 comprising at least one processor (e.g., a central processing unit (CPU),..”];
wherein the CPU is configured to initiate a boot of the SOC [Haribhatt paragraph 0028, first lines “…When the SOC 102 is powered-up, the processor 112 may access the firmware code 124 from the boot ROM 106 and begin to execute it…”]
first memory [Haribhatt paragraph 0024, first lines “…The SOC 102 also includes various memories including a boot ROM 106, a non-volatile memory 108, and a RAM 110…”]; and
Haribhatt fails to explicitly teach hardware logic disposed within a communication path between the CPU and the first memory wherein the hardware logic is configured to: perform a mirroring operation on data from a second memory to the first memory.
However, Bennett does teach hardware logic disposed within a communication path between the CPU and the first memory [Bennett paragraph 0038, first lines “…The fold operation may be implemented in FPGA, in an application-specific integrated circuit (ASIC), in the CPU, or in another suitable component of the computer system 110…”], wherein the hardware logic is configured to:
perform a mirroring operation on data from a second memory to the first memory [Bennett paragraph 0017, middle lines “…The movement of the content may be for the purpose of copying the content from the source to the destination…”(Where copying reads on the BRI of mirroring.)];
Haribhatt and Bennett are analogous arts in that they both deal with improving memory performance.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to the teachings of Haribhatt’s system-on-chip booting process with Bennett’s teachings of managing the copying process for the benefit of optimizing the computer system performance by moving data to the appropriate tier for best performance while not delaying the use of the memory [Bennett paragraph 0004, first lines “…optimize the computer system performance, content in the computer memory may need to be moved, for example, for re-allocation of the computer memory. For example, content in the computer memory may need to be placed in an appropriate tier of the computer memory. In this regard, there may be situations where the content is to be moved from one physical location to another, without stopping or otherwise delaying the possible users of the computer memory…”].
wherein the data corresponds to a software function of a software application [Haribhatt paragraph 0010, last lines “…The firmware code may also include instructions for performing other initializations, such as for example, launching an operating system (OS) that may handle operation of the SOC after the firmware code is executed…”(Where the OS reads on software application.)].
receive a request from the CPU, wherein the request references an address in the first memory [Bennett paragraph 0061, most lines “…the processor 602 may fetch, decode, and execute the instructions to ascertain, from the request 104, the logical address. The processor 602 may fetch, decode, and execute the instructions to determine, based on the ascertained logical address, whether the request 104 is directed to the content 106 that is to be moved from the source 114 of the computer memory 108 to the destination 116 of the computer memory 108. Based on the determination that the content 106 is at the source 114, the processor 602 may fetch, decode, and execute the instructions to perform, based on mapping of the ascertained logical address to a source physical address (e.g., a physical address assigned to the source 114) assigned to the content 106…”];
determine whether to respond to the request using the data as stored in the first memory or the data as stored in the second memory based on whether the address referenced by the request has been written by the mirroring operation [Bennett paragraph 0026, all lines “…the request analysis module 112 may determine, based on an analysis of a map page table 118, whether the request 104 is directed to the content 106 that is to be moved from the source 114 to the destination 116. The map page table 118 may include an indication of whether the content 106 is located at the source 114, at the destination 116, or is to be moved from the source 114 to the destination 116. In this regard, the request analysis module 112 may determine, by using the page table 118, that a memory region requested by a guest is located successively at the physical source 114, at the address of a reflective copy module 120, and finally at the physical destination 116, and this determination may guide memory requests on behalf of the guest to be performed originally by the source memory, then by the reflective copy module 120 for the duration of the move, and then by the destination memory after the move is complete…”]; and
respond to the request [Bennett figure 8, feature 816 and 818].
Haribhatt and Bennett fail to explicitly teach wherein the CPU is configured to, executing the instructions based on the data, before the mirroring operation is complete.
However, Cromer does teach wherein the CPU is configured to, execute the instructions based on the data, before the mirroring operation is complete [Cromer column 3, lines 45-48 “…The process copy module copies the software process image from the first storage system to a second storage system concurrent with the resumption of execution of the software process…”(The examiner has determined that the concurrent execution of the software would read on the beginning the executing of the software function before the copying is complete since the actions are concurrent neither action has completed.)].
Haribhatt, Bennett, and Cromer are analogous arts in that they both deal with improving the performance of data movement in a memory system.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Haribhatt and Bennett with Cromer’s teachings of the memory being a set of software functions of a software application by being a software process image that would contain both of those items for the benefit of reducing latency by seamlessly performing the copying and execution of the application. [Cromer column 3, lines 2-6 “…the second computation module may begin executing the software process where the first computation module left off, seamlessly moving the execution of the software process from the first computation module to the second computation module…’].
Regarding claim 11, as per claim 10, Bennett teaches translate the address in the first memory to an address in the second memory [Bennett paragraph 0040, last lines “…The move may be transparent to any CPU operation or device input/output which uses guest address spaces, which may be managed by the hypervisor and translated to physical addresses by the page table 118 entries…”] in response to a determination of responding to the request using the data as stored in the second memory [Haribhatt paragraph 0016, first lines “…The SOC may also include a non-volatile memory. When it is desirable to patch the firmware code, a patch table data structure may be stored at the non-volatile memory. The patch table data structure, in some examples, includes a record for each functional block of the firmware code…” and paragraph 0035, last lines “…the processor 112 may utilize the data directly from the non-volatile memory 108 or may load some or all the patch data to a RAM such as the RAM 110 and or the IRAM 116…”].
Regarding claim 12, as per claim 10, Cromer teaches wherein the data is associated with a software function of a software application [Cromer column 5, lines 54-57 “…a module of executable code may be a single instruction, or many instructions, and may even be distributed over several different code segments, among different programs, and across several memory devices…”].
Regarding claim 13, as per claim 10, Bennett teaches the hardware logic comprises direct memory access (DMA) logic configured to perform the mirroring operation, further wherein the first memory comprises on-chip random access memory (RAM) and the second memory comprises external memory [Bennett paragraph 0004, last lines “…usage of the specified portion of the computer memory may include direct memory access from peripheral devices such as a network or a solid-state drive (SSD), and a hypervisor may not be aware of how or when the direct memory access may be scheduled. In this regard, it is technically challenging to move memory blocks in such a way that the memory block user perceives no interruption or error…” and paragraph 0034, last lines “…for pages in the DRAM that are no longer the most highly used, the reflective copy module 120 may move such pages to the memory accessible via DDR4 or DDR5 interface standards, or to the bulk memory. The bulk memory may be described as high-capacity memory used in connection with the computer system 110 for bulk storage of large quantities of data, e.g., flash disk, RAM, etc…”].
Regarding claim 14, as per claim 10, Bennett teaches the hardware logic is configured to, as part of the mirroring operation: sequentially read the data from a first plurality of addresses of the second memory; and write the data to a second plurality of addresses of the first memory in a same order in which the data was read from the first plurality of addresses [Bennett paragraph 0039, first lines “…The fold may move sequentially through the page 122, copying by reading an item (e.g., a cache line size) of the content 106 from the source 114 and writing it to the destination 116…”].
Regarding claim 21, Haribhatt teaches a device ) [Haribhatt paragraph 0028, first lines “…when the SOC 102 is powered up…”] comprising:
processor circuitry configured to initiate a boot of the device [Haribhatt paragraph 0028, first lines “…When the SOC 102 is powered-up, the processor 112 may access the firmware code 124 from the boot ROM 106 and begin to execute it…”];
a first set of memory control circuitry coupled to the processor circuitry [Haribhatt figure 1, feature 120 “Singal processing circuitry”];
a first memory coupled to the first set of memory control circuitry [Haribhatt figure 1, feature 110 “RAM”]; and
a second set of memory control circuitry coupled to the first set of memory control circuitry and configured to couple to a second memory [Haribhatt paragraph 0018, last lines “…The communication bus 122 may be arranged according to any suitable hardware and/or software protocol or protocols, such as, for example, the Inter-Integrated Circuit (I2C) protocol…” and figure 1, feature 108 “NVM”], wherein:
Haribhatt fails to explicitly teach the first set of memory control circuitry includes a set of direct memory access (DMA) circuitry capable of performing a DMA transfer of a set of data between the second memory and the first memory using the second set of memory control circuitry; and the first set of memory control circuitry is capable of, during the DMA transfer: receiving, from the processor circuitry, a read request directed to a subset of the set of data.
However, Bennett does teach the first set of memory control circuitry includes a set of direct memory access (DMA) circuitry capable of performing a DMA transfer of a set of data between the second memory and the first memory using the second set of memory control circuitry [Bennett paragraph 0004, last lines “…usage of the specified portion of the computer memory may include direct memory access from peripheral devices such as a network or a solid-state drive (SSD), and a hypervisor may not be aware of how or when the direct memory access may be scheduled. In this regard, it is technically challenging to move memory blocks in such a way that the memory block user perceives no interruption or error…” ]; and
the first set of memory control circuitry is capable of, during the DMA transfer:
receiving, from the processor circuitry, a read request directed to a subset
of the set of data [Bennett paragraph 0025, all lines “…A request analysis module 112 may determine whether the request 104 is directed to the content 106 that is to be moved from a source 114 of the computer memory 108 to a destination 116 of the computer memory 108…” and paragraph 0018, all lines “…may provide for continuous operation of a hypervisor (or another device) so that is no pause in the hypervisor functionality during a move, including no interruptions or failure of direct memory access activity…” and paragraph 0059, last lines “…based on a determination that the content 106 is not included in the portion of the memory address range 124, the processor 602 may fetch, decode, and execute the instructions to perform the request 104 associated with the content 106 using the source 114…”(Where range reads on a subset.)].
Haribhatt and Bennett are analogous arts in that they both deal with improving memory performance.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to the teachings of Haribhatt’s system-on-chip booting process with Bennett’s teachings of managing the copying process for the benefit of optimizing the computer system performance by moving data to the appropriate tier for best performance while not delaying the use of the memory [Bennett paragraph 0004, first lines “…optimize the computer system performance, content in the computer memory may need to be moved, for example, for re-allocation of the computer memory. For example, content in the computer memory may need to be placed in an appropriate tier of the computer memory. In this regard, there may be situations where the content is to be moved from one physical location to another, without stopping or otherwise delaying the possible users of the computer memory…”].
Haribhatt teaches wherein the subset of the set of data is associated with the boot [Haribhatt paragraph 0016, first lines “…The SOC may also include a non-volatile memory. When it is desirable to patch the firmware code, a patch table data structure may be stored at the non-volatile memory. The patch table data structure, in some examples, includes a record for each functional block of the firmware code…” and paragraph 0035, last lines “…the processor 112 may utilize the data directly from the non-volatile memory 108 or may load some or all the patch data to a RAM such as the RAM 110 and or the IRAM 116…”].
Bennett teaches determining whether to provide the subset of the set of data using the first memory or the second memory [Bennett paragraph 0026, all lines “…the request analysis module 112 may determine, based on an analysis of a map page table 118, whether the request 104 is directed to the content 106 that is to be moved from the source 114 to the destination 116. The map page table 118 may include an indication of whether the content 106 is located at the source 114, at the destination 116, or is to be moved from the source 114 to the destination 116. In this regard, the request analysis module 112 may determine, by using the page table 118, that a memory region requested by a guest is located successively at the physical source 114, at the address of a reflective copy module 120, and finally at the physical destination 116, and this determination may guide memory requests on behalf of the guest to be performed originally by the source memory, then by the reflective copy module 120 for the duration of the move, and then by the destination memory after the move is complete…”]; and
Haribhatt and Bennett fail to explicitly teach causing the subset of the first set of data to be provided to the processor circuitry before the DMA transfer is complete.
However, Cromer does teach causing the subset of the first set of data to be provided to the processor circuitry before the DMA transfer is complete [Cromer column 3, lines 45-48 “…The process copy module copies the software process image from the first storage system to a second storage system concurrent with the resumption of execution of the software process…”(The examiner has determined that the concurrent execution of the software would read on the beginning the executing of the software function before the copying is complete since the actions are concurrent neither action has completed.)].
Haribhatt, Bennett, and Cromer are analogous arts in that they both deal with improving the performance of data movement in a memory system.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Haribhatt and Bennett with Cromer’s teachings of the memory being a set of software functions of a software application by being a software process image that would contain both of those items for the benefit of reducing latency by seamlessly performing the copying and execution of the application. [Cromer column 3, lines 2-6 “…the second computation module may begin executing the software process where the first computation module left off, seamlessly moving the execution of the software process from the first computation module to the second computation module…’].
Regarding claim 22, as per claim 21, Bennett teaches the first memory is random-access
memory (RAM) and the second memory is Flash memory [Bennett paragraph 0034, last lines “…for pages in the DRAM that are no longer the most highly used, the reflective copy module 120 may move such pages to the memory accessible via DDR4 or DDR5 interface standards, or to the bulk memory. The bulk memory may be described as high-capacity memory used in connection with the computer system 110 for bulk storage of large quantities of data, e.g., flash disk, RAM, etc…”].
Regarding claim 24, as per claim 1, Haribhatt teaches the SoC comprises a central processing unit (CPU), and the method further comprising determining whether the set of data is accessible by the CPU before copying the set of data from the first memory to the second memory, wherein copying the set of data from the first memory to the second memory is performed in response to that the set of data is accessible by the CPU [ paragraph 0029, most lines “…When executing the firmware code 124, the processor 112 may determine whether firmware patching is active for the SOC 102. This may be performed in various different ways. In some examples, firmware patching may be activated by providing an appropriate signal at the bootstrap pin BS. For example, if it becomes desirable to patch the firmware code 124, the SOC 102 may be configured in a circuit that provides a signal at the bootstrap pin BS. In another example, the processor 112 may determine whether firmware patching is active for the SOC 102 by referring to a location at the non-volatile memory 108…”(The examiner has determined if the patch is active then the data is accessible to the CPU via the non-volatile memory.)].
Claim 23 is rejected under 35 U.S.C. 103 as being unpatentable over Haribhatt et al. [US2023/0359740] in view of Bennett et al. [US2019/0138453] in view of Cromer et al. [US7,702,789] further in view of Aberl et al [US2018/0293129]. Haribhatt teaches code patching for system on a chip. Bennett teaches computer memory content movement. Cromer teaches apparatus system, and method for reassigning a client. Aberl teaches safe execution in place (XIP) from flash memory.
Regarding claim 23, as per claim 1, Haribhatt, Bennett, and Cromer fail to explicitly teach accessing the subset of the set of data from the first memory comprises performing an execute-in-place (XIP) operation.
However, Aberl does teach accessing the subset of the set of data from the first memory comprises performing an execute-in-place (XIP) operation [Aberl paragraph 0013, middle lines “…he ECC protection is implemented on the SoC between any processors coupled to access the flash memory and a flash interface controller on the SoC, which provides protection from both soft errors in accessed flash memory locations and errors that may introduced due to failures in the circuitry coupling the flash memory to the SoC or failures in the flash interface controller…” and paragraph 0026, first lines “…One application of the safe XIP is booting a processor on the SOC 100 where at least some of the boot instructions and data are stored in an ECC region of the flash memory 126…”].
Haribhatt, Bennett, Cromer and Aberl are analogous arts in that they all deal with improving memory performance.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Haribhatt, Bennett, and Cromer with the teachings of Aberl’s use of XIP for the benefit of protecting from soft errors in accessed flash memory by avoiding radiation flip bits which improves reliability [Aberl paragraph 0013, middle lines “…which provides protection from both soft errors in accessed flash memory locations and errors that may introduced due to failures in the circuitry coupling the flash memory to the SoC or failures in the flash interface controller…”].
Allowable Subject Matter
Claims 25-27 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant’s arguments with respect to claims 1, 10, and 21 have been considered but are moot in view of new grounds of rejection.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC CARDWELL whose telephone number is (571)270-1379. The examiner can normally be reached on Monday - Friday 10-6pm EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Reginald Bragdon can be reached on (571) 272-4204. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ERIC CARDWELL/Primary Examiner, Art Unit 2139
Prosecution Insights