DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicant’s Remarks/Arguments filed on January 12th, 2026, have been carefully considered.
Claims 1, 8-10, 12 and 21 have been amended.
No claims have been added or canceled.
Claims 1-14 and 21-22 are currently pending in the instant application.
Claim Objections
Claim 10 is objected to because of the following informalities:
Regarding claim 10, the second to last line, includes the word CUP, the examiner believes the word is intended to be CPU.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-14 and 20-21 are rejected under 35 U.S.C. 103 as being unpatentable over Bennett et al. [US2019/0138453] in view of Cromer et al. [US7,702,789]. Bennett teaches computer memory content movement. Cromer teaches apparatus system, and method for reassigning a client.
Regarding claim 1, Bennett teaches a method comprising:
copying a set of data from a first memory to a second memory [Bennett paragraph 0017, middle lines “…The movement of the content may be for the purpose of copying the content from the source to the destination…”];
Bennett fails to explicitly teach wherein the set of data corresponds to a software function of a software application.
However, Cromer does teach wherein the set of data corresponds to a software function of a software application [Cromer column 2, lines 36-38 “…copying the memory map of the software process image from the first computation module to the second computation module…”].
Bennett and Cromer are analogous arts in that they both deal with improving the performance of data movement in a memory system.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Bennett’s data copying process with Cromer’s teachings of the memory being a set of software functions of a software application by being a software process image that would contain both of those items for the benefit of reducing latency by seamlessly performing the copying and execution of the application. [Cromer column 3, lines 2-6 “…the second computation module may begin executing the software process where the first computation module left off, seamlessly moving the execution of the software process from the first computation module to the second computation module…’].
monitoring a progress of the copying of the set of data [Bennett paragraph 0017, last lines ”…depending upon how the progress of the move defines a current state of the move…”];
receiving a transaction from a processing unit during the copying of the set of data [Bennett paragraph 0025, all lines “…A request analysis module 112 may determine whether the request 104 is directed to the content 106 that is to be moved from a source 114 of the computer memory 108 to a destination 116 of the computer memory 108…” and paragraph 0018, all lines “…may provide for continuous operation of a hypervisor (or another device) so that is no pause in the hypervisor functionality during a move, including no interruptions or failure of direct memory access activity…”]; and
determining, based on the monitoring, whether to perform the transaction using the set of data as stored in the first memory or the set of data as stored in the second memory [Bennett paragraph 0026, all lines “…the request analysis module 112 may determine, based on an analysis of a map page table 118, whether the request 104 is directed to the content 106 that is to be moved from the source 114 to the destination 116. The map page table 118 may include an indication of whether the content 106 is located at the source 114, at the destination 116, or is to be moved from the source 114 to the destination 116. In this regard, the request analysis module 112 may determine, by using the page table 118, that a memory region requested by a guest is located successively at the physical source 114, at the address of a reflective copy module 120, and finally at the physical destination 116, and this determination may guide memory requests on behalf of the guest to be performed originally by the source memory, then by the reflective copy module 120 for the duration of the move, and then by the destination memory after the move is complete…”]; and
performing the transaction [Bennett figure 8, feature 816 and 818].
Cromer teaches beginning executing the software function, based on the set of data, before the copying is complete [Cromer column 3, lines 45-48 “…The process copy module copies the software process image from the first storage system to a second storage system concurrent with the resumption of execution of the software process…”(The examiner has determined that the concurrent execution of the software would read on the beginning the executing of the software function before the copying is complete since the actions are concurrent neither action has completed.)].
Regarding claim 2, as per claim 1, Bennett teaches the transaction comprises a read request identifying an address and a size of a subset of the set of data [Bennett paragraph [Bennett paragraph 0019, middle lines “…The reflective copy module may advertise an address range of a same size as a page that includes the content, where the page may be moved from the source to the destination…”].
Regarding claim 3, as per claim 1, Bennett teaches the address comprises an address within the second memory [Bennett paragraph 0047, last lines “…In this regard, the page table 118 entry for that logical address is changed to point to the physical destination…”].
Regarding claim 4, as per claim 1, Bennett teaches determining that a subset of the set of data is not available in the second memory [Bennett paragraph 0061, middle lines “…Based on the determination that the content 106 is at the source 114, the processor 602 may fetch, decode, and execute the instructions to perform, based on mapping of the ascertained logical address to a source physical address (e.g., a physical address assigned to the source 114) assigned to the content 106, the request 104 associated with the content 106 using the source 114…” and paragraph 0059, last lines “…based on a determination that the content 106 is not included in the portion of the memory address range 124, the processor 602 may fetch, decode, and execute the instructions to perform the request 104 associated with the content 106 using the source 114…”(Where range reads on a subset.)];
translating an address received from the processing unit to an address corresponding to a location in the first memory [Bennett paragraph 0061, middle lines “…based on mapping of the ascertained logical address to a source physical address (e.g., a physical address assigned to the source 114) assigned to the content 106, the request 104 associated with the content 106 using the source 114…”]; and
accessing the subset of the set of data from the first memory according to the address corresponding to a location in the first memory [Bennett paragraph 0061, middle lines “…Based on the determination that the content 106 is at the source 114, the processor 602 may fetch, decode, and execute the instructions to perform…the request 104 associated with the content 106 using the source 114…”].
Regarding claim 5, as per claim 1, Bennett teaches determining that a subset of the set of data is available in the second memory [Bennett paragraph 0061, last lines “…Based on the determination that the content 106 has been moved from the source 114 to the destination 116, the processor 602 may fetch, decode, and execute the instructions to perform, based on mapping of the ascertained logical address to a destination physical address (e.g., a physical address assigned to the destination 116) assigned to the content 106, the request 104 associated with the content 106 using the destination 116…”]; and
accessing the subset of the set of data from the second memory according to an address received from the processing unit [Bennett paragraph 0059, last lines “…Based on a determination that the content 106 is included in the portion of the memory address range 124, the processor 602 may fetch, decode, and execute the instructions to perform the request 104 associated with the content 106 using the destination 116....”(Where range reads on subset.)]
Regarding claim 6, as per claim 1, Bennett teaches the first memory comprises external memory [Bennett paragraph 0034, middle lines “…The bulk memory may be described as high-capacity memory used in connection with the computer system 110 for bulk storage of large quantities of data, e.g., flash disk…”] and wherein the second memory comprises on-chip random access memory (RAM) [Bennett paragraph 0036, first lines “…such pages may be moved by the reflective copy module 120 into the DRAM…”].
Regarding claim 7, as per claim 1, Bennett teaches sequentially reading contents from a first plurality of addresses of the first memory; and writing the contents to a second plurality of addresses of the second memory in a same order in which the contents were read from the first plurality of addresses [Bennett paragraph 0039, first lines “…The fold may move sequentially through the page 122, copying by reading an item (e.g., a cache line size) of the content 106 from the source 114 and writing it to the destination 116…”].
Regarding claim 8, as per claim 1, Bennett teaches the transaction is associated with execution of the software application, further wherein the set of data is associated with the software application, and wherein the first plurality of addresses correspond to an order in which the set of data is accessed during execution of the software application [Bennett paragraph 0018, most lines “…the apparatuses, methods, and non-transitory computer readable media disclosed herein may provide an operating system (OS), a hypervisor, or another such device, to be able to move content from one physical device to another while the content remains in active use by both code and devices, where the use of the content may migrate from a previous physical location (e.g., a source) to a new physical location (e.g., a destination)…”(Where the OS implies the use of applications and a hypervisor and code when given their BRI reads on applications)].
Regarding claim 9, as per claim 1, Cromer teaches the transaction is associated with execution of the software application, and further wherein the set of data is associated with the software application and includes machine code instructions and data values [Cromer column 5, lines 54-57 “…a module of executable code may be a single instruction, or many instructions, and may even be distributed over several different code segments, among different programs, and across several memory devices…”], the method further comprising: at the processing unit [Cromer column 5, lines 44-45 “…Modules may also be implemented in software for execution by various types of processors…”], beginning executing the software application before the set of data has been written to the second memory in its entirety [Cromer column 3, lines 45-48 “…The process copy module copies the software process image from the first storage system to a second storage system concurrent with the resumption of execution of the software process…”(The examiner has determined that the concurrent execution of the software would read on the beginning the executing of the software function before the copying is complete since the actions are concurrent neither action has completed.)].
Regarding claim 10, Bennett teaches a system on-chip (SoC) [Bennett paragraph 0038, first lines “…The fold operation may be implemented in FPGA, in an application-specific integrated circuit (ASIC), in the CPU, or in another suitable component of the computer system 110…”] comprising:
a central processing unit (CPU) [Bennett paragraph 0050, middle lines “…The hardware may include a processor 602…”];
first memory [Bennett paragraph 0050, middle lines “…and a memory 604 storing machine readable instructions that when executed by the processor…”]; and
hardware logic disposed within a communication path between the CPU and the first memory [Bennett paragraph 0038, first lines “…The fold operation may be implemented in FPGA, in an application-specific integrated circuit (ASIC), in the CPU, or in another suitable component of the computer system 110…”], wherein the hardware logic is configured to:
perform a mirroring operation on data from a second memory to the first memory [Bennett paragraph 0017, middle lines “…The movement of the content may be for the purpose of copying the content from the source to the destination…”(Where copying reads on the BRI of mirroring.)];
Bennett fails to explicitly teach wherein the data corresponds to a software function of a software application.
However, Cromer does teach wherein the data corresponds to a software function of a software application [Cromer column 2, lines 36-38 “…copying the memory map of the software process image from the first computation module to the second computation module…”].
Bennett and Cromer are analogous arts in that they both deal with improving the performance of data movement in a memory system.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Bennett’s data copying process with Cromer’s teachings of the memory being a set of software functions of a software application by being a software process image that would contain both of those items for the benefit of reducing latency by seamlessly performing the copying and execution of the application. [Cromer column 3, lines 2-6 “…the second computation module may begin executing the software process where the first computation module left off, seamlessly moving the execution of the software process from the first computation module to the second computation module…’].
receive a request from the CPU, wherein the request references an address in the first memory [Bennett paragraph 0061, most lines “…the processor 602 may fetch, decode, and execute the instructions to ascertain, from the request 104, the logical address. The processor 602 may fetch, decode, and execute the instructions to determine, based on the ascertained logical address, whether the request 104 is directed to the content 106 that is to be moved from the source 114 of the computer memory 108 to the destination 116 of the computer memory 108. Based on the determination that the content 106 is at the source 114, the processor 602 may fetch, decode, and execute the instructions to perform, based on mapping of the ascertained logical address to a source physical address (e.g., a physical address assigned to the source 114) assigned to the content 106…”];
determine whether to respond to the request using the data as stored in the first memory or the data as stored in the second memory based on whether the address referenced by the request has been written by the mirroring operation [Bennett paragraph 0026, all lines “…the request analysis module 112 may determine, based on an analysis of a map page table 118, whether the request 104 is directed to the content 106 that is to be moved from the source 114 to the destination 116. The map page table 118 may include an indication of whether the content 106 is located at the source 114, at the destination 116, or is to be moved from the source 114 to the destination 116. In this regard, the request analysis module 112 may determine, by using the page table 118, that a memory region requested by a guest is located successively at the physical source 114, at the address of a reflective copy module 120, and finally at the physical destination 116, and this determination may guide memory requests on behalf of the guest to be performed originally by the source memory, then by the reflective copy module 120 for the duration of the move, and then by the destination memory after the move is complete…”]; and
respond to the request [Bennett figure 8, feature 816 and 818].
wherein the CPU is configured to begin executing the software function, based on the data, before the mirroring operation is complete [Cromer column 3, lines 45-48 “…The process copy module copies the software process image from the first storage system to a second storage system concurrent with the resumption of execution of the software process…”(The examiner has determined that the concurrent execution of the software would read on the beginning the executing of the software function before the copying is complete since the actions are concurrent neither action has completed.)].
Regarding claim 11, as per claim 10, Bennett teaches translate the address in the first memory to an address in the second memory [Bennett paragraph 0040, last lines “…The move may be transparent to any CPU operation or device input/output which uses guest address spaces, which may be managed by the hypervisor and translated to physical addresses by the page table 118 entries…”].
Regarding claim 12, as per claim 10, Cromer teaches wherein the data includes machine code instructions [Cromer column 5, lines 54-57 “…a module of executable code may be a single instruction, or many instructions, and may even be distributed over several different code segments, among different programs, and across several memory devices…”].
Regarding claim 13, as per claim 10, Bennett teaches the hardware logic comprises direct memory access (DMA) logic configured to perform the mirroring operation, further wherein the first memory comprises on-chip random access memory (RAM) and the second memory comprises external memory [Bennett paragraph 0004, last lines “…usage of the specified portion of the computer memory may include direct memory access from peripheral devices such as a network or a solid-state drive (SSD), and a hypervisor may not be aware of how or when the direct memory access may be scheduled. In this regard, it is technically challenging to move memory blocks in such a way that the memory block user perceives no interruption or error…” and paragraph 0034, last lines “…for pages in the DRAM that are no longer the most highly used, the reflective copy module 120 may move such pages to the memory accessible via DDR4 or DDR5 interface standards, or to the bulk memory. The bulk memory may be described as high-capacity memory used in connection with the computer system 110 for bulk storage of large quantities of data, e.g., flash disk, RAM, etc…”].
Regarding claim 14, as per claim 10, Bennett teaches the hardware logic is configured to, as part of the mirroring operation: sequentially read the data from a first plurality of addresses of the second memory; and write the data to a second plurality of addresses of the first memory in a same order in which the data was read from the first plurality of addresses [Bennett paragraph 0039, first lines “…The fold may move sequentially through the page 122, copying by reading an item (e.g., a cache line size) of the content 106 from the source 114 and writing it to the destination 116…”].
Regarding claim 21, Bennett teaches a device comprising:
processor circuitry [Bennett paragraph 0050, middle lines “…The hardware may include a processor 602…”];
a first set of memory control circuitry coupled to the processor circuitry [Bennett paragraph 0050, middle lines “…and a memory 604 storing machine readable instructions that when executed by the processor…”];
a first memory coupled to the first set of memory control circuitry [Bennett paragraph 0032, first lines “…the computer memory 108 may include a page 122 that includes the content 106. In this regard, the page may be moved from the source 114 to the destination 116…”]; and
a second set of memory control circuitry coupled to the first set of memory control circuitry and configured to couple to a second memory [Bennett paragraph 0034, last lines “…for pages in the DRAM that are no longer the most highly used, the reflective copy module 120 may move such pages to the memory accessible via DDR4 or DDR5 interface standards, or to the bulk memory. The bulk memory may be described as high-capacity memory used in connection with the computer system 110 for bulk storage of large quantities of data, e.g., flash disk, RAM, etc…”], wherein:
the first set of memory control circuitry includes a set of direct memory access (DMA) circuitry capable of performing a DMA transfer of a set of data between the second memory and the first memory using the second set of memory control circuitry [Bennett paragraph 0004, last lines “…usage of the specified portion of the computer memory may include direct memory access from peripheral devices such as a network or a solid-state drive (SSD), and a hypervisor may not be aware of how or when the direct memory access may be scheduled. In this regard, it is technically challenging to move memory blocks in such a way that the memory block user perceives no interruption or error…” ]; and
the first set of memory control circuitry is capable of, during the DMA transfer:
receiving, from the processor circuitry, a read request directed to a subset
of the set of data [Bennett paragraph 0025, all lines “…A request analysis module 112 may determine whether the request 104 is directed to the content 106 that is to be moved from a source 114 of the computer memory 108 to a destination 116 of the computer memory 108…” and paragraph 0018, all lines “…may provide for continuous operation of a hypervisor (or another device) so that is no pause in the hypervisor functionality during a move, including no interruptions or failure of direct memory access activity…” and paragraph 0059, last lines “…based on a determination that the content 106 is not included in the portion of the memory address range 124, the processor 602 may fetch, decode, and execute the instructions to perform the request 104 associated with the content 106 using the source 114…”(Where range reads on a subset.)]; and
Bennett fails to explicitly teach wherein the subset of the set of data corresponds to a software function of a software application.
However, Cromer does teach wherein the subset of the set of data corresponds to a software function of a software application [Cromer column 2, lines 36-38 “…copying the memory map of the software process image from the first computation module to the second computation module…”].
Bennett and Cromer are analogous arts in that they both deal with improving the performance of data movement in a memory system.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Bennett’s data copying process with Cromer’s teachings of the memory being a set of software functions of a software application by being a software process image that would contain both of those items for the benefit of reducing latency by seamlessly performing the copying and execution of the application. [Cromer column 3, lines 2-6 “…the second computation module may begin executing the software process where the first computation module left off, seamlessly moving the execution of the software process from the first computation module to the second computation module…’].
determining whether to provide the subset of the set of data using the first memory or the second memory [Bennett paragraph 0026, all lines “…the request analysis module 112 may determine, based on an analysis of a map page table 118, whether the request 104 is directed to the content 106 that is to be moved from the source 114 to the destination 116. The map page table 118 may include an indication of whether the content 106 is located at the source 114, at the destination 116, or is to be moved from the source 114 to the destination 116. In this regard, the request analysis module 112 may determine, by using the page table 118, that a memory region requested by a guest is located successively at the physical source 114, at the address of a reflective copy module 120, and finally at the physical destination 116, and this determination may guide memory requests on behalf of the guest to be performed originally by the source memory, then by the reflective copy module 120 for the duration of the move, and then by the destination memory after the move is complete…”]; and
causing the subset of the first set of data to be provided to the processor circuitry [Bennett figure 8, feature 816 and 818].
wherein the processor circuitry is configured to: begin executing the software function, based on the subset of the set of data, before the DMA transfer is complete [Cromer column 3, lines 45-48 “…The process copy module copies the software process image from the first storage system to a second storage system concurrent with the resumption of execution of the software process…”(The examiner has determined that the concurrent execution of the software would read on the beginning the executing of the software function before the copying is complete since the actions are concurrent neither action has completed. Also, it is obvious that a DMA transfer is a type of copy and the BRI of copy reads on a DMA transfer.)].
Regarding claim 22, as per claim 21, Bennett teaches the first memory is random-access
memory (RAM) and the second memory is Flash memory [Bennett paragraph 0034, last lines “…for pages in the DRAM that are no longer the most highly used, the reflective copy module 120 may move such pages to the memory accessible via DDR4 or DDR5 interface standards, or to the bulk memory. The bulk memory may be described as high-capacity memory used in connection with the computer system 110 for bulk storage of large quantities of data, e.g., flash disk, RAM, etc…”].
Response to Arguments
Applicant’s arguments with respect to claims 1, 10, and 21 have been considered but are moot in view of new grounds of rejection.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Osaki et al. [US2025/0103443] Osaki teaches continuing execution during a copy operation.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC CARDWELL whose telephone number is (571)270-1379. The examiner can normally be reached on Monday - Friday 10-6pm EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Reginald Bragdon can be reached on (571) 272-4204. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ERIC CARDWELL/Primary Examiner, Art Unit 2139
Prosecution Insights