Prosecution Insights
Last updated: August 17, 2026
Application No. 18/592,222

LOOP OPTIMIZATION-BASED APPROACH FOR TASK SCHEDULING IN GRAPH MACHINE LEARNING MODELS

Non-Final OA §101§112
Filed
Feb 29, 2024
Examiner
ANDREI, RADU
Art Unit
Tech Center
Assignee
Qualcomm Incorporated
OA Round
1 (Non-Final)
37%
Grant Probability
At Risk
1-2
OA Rounds
11m
Est. Remaining
57%
With Interview

Examiner Intelligence

Grants only 37% of cases
37%
Career Allowance Rate
214 granted / 582 resolved
-23.2% vs TC avg
Strong +20% interview lift
Without
With
+20.3%
Interview Lift
resolved cases with interview
Typical timeline
3y 4m
Avg Prosecution
52 currently pending
Career history
641
Total Applications
across all art units

Statute-Specific Performance

§101
43.5%
+3.5% vs TC avg
§103
37.1%
-2.9% vs TC avg
§102
1.9%
-38.1% vs TC avg
§112
15.2%
-24.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 582 resolved cases

Office Action

§101 §112
DETAILED ACTION The present application, filed on 2/29/2024 is being examined under the AIA first inventor to file provisions. The following is a non-final First Office Action on the Merits. Claims 1-20 are pending and have been considered below. Information Disclosure Statement (IDS) The information disclosure statement (IDS) submitted on 7/28/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, such IDS is being considered by Examiner. Claim Rejections - 35 USC § 101 35 USC 101 reads as follows: Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title. Claims 1-20 are rejected under 35 USC 101 because the claimed invention is not directed to patent eligible subject matter. The claimed matter is directed to a judicial exception, i.e. an abstract idea, not integrated into a practical application, and without significantly more. Per Step 1 of the multi-step eligibility analysis, claims 1-7 are directed to a system, claims 8-14 are directed to a computer implemented method, and claims 15-20 are directed to a system. Thus, on its face, each independent claim and the associated dependent claims are directed to a statutory category of invention. [INDEPENDENT CLAIMS] Per Step 2A.1. Independent claim 1, (which is representative of independent claims 8, 15) is rejected under 35 USC 101 because the independent claim is directed to an abstract idea, a judicial exception, without reciting additional elements that integrate the judicial exception into a practical application. The limitations of the independent claim 1 (which is representative of independent claims 8, 15) recite an abstract idea, shown in bold below: [A] An apparatus comprising: [B] at least one memory, and at least one processor coupled to the at least one memory [C] receive a machine learning (ML) model, the ML model being represented as a graph having multiple nodes coupled by edges; [D] assign a value number to each node in the graph based on a similarity in characteristics of the multiple nodes; [E] reconstruct a loop for computations in the graph based on the value number to generate a reconstructed loop; and [F] determine loop bounds of the reconstructed loop using an affine scalar evolution analysis technique. Independent claim 1 (which is representative of independent claims 8, 15) recites: assigning a value to each node in a graph ([D]); reconstructing a loop for computation in the graph ([E]); and determine loop bounds ([F]), which, based on the claim language and in view of the application disclosure, represents a process aimed at: task scheduling based on loop optimization. This is a combination that, under its broadest reasonable interpretation, covers performance of limitations expressing mathematical concepts like mathematical calculations, mathematical operations. These fall under the Mathematical Concepts. i.e., mathematical relationships, mathematical formulas or equations, or mathematical calculations grouping of abstract ideas (see MPEP 2106.04(a)(2) I). Accordingly, it is concluded that independent claim 1 (which is representative of independent claims 8, 15) recites an abstract idea that corresponds to a judicial exception. [INDEPENDENT CLAIMS – Additional Elements] Per Step 2A.2. The identified abstract idea is not integrated into a practical application because the additional elements in the independent claims only amount to instructions to apply the judicial exception to a computer, or are a general link to a technological environment (see MPEP 2106.05(f); MPEP 2106.05(h)). For example, the added elements “processor,” and “memory” recite computing elements at a high level of generality, generally linking the use of a judicial exception to a particular technological environment (see MPEP 2106.05(h)), or merely using a computer as a tool to perform an abstract idea (MPEP 2106.05(f)). These additional elements of the independent claims do not preclude from carrying out the identified abstract idea task scheduling based on loop optimization, and do not serve to integrate the identified abstract idea into a practical application. The additional elements in the independent claims, shown not bolded above, recite: receive a machine learning (ML) model ([C]). When considered individually, they amount to nothing more than receiving data, processing data, storing results or transmitting data that serves merely to implement the abstract idea using computing components for performing computer functions (corresponding to the words “apply it” or an equivalent), or merely uses a computer as a tool to perform the identified abstract idea. Thus, it is concluded that these claim elements do not integrate the identified abstract idea (task scheduling based on loop optimization) into a practical application (see MPEP 2106.05(f)(2)). Therefore, the additional claim elements of independent claim 1, (which is representative of independent claims 8, 15), evaluated individually, as well as a whole, as an ordered combination, do not integrate the identified abstract idea into a practical application and the claims are directed to the recited judicial exception. Per Step 2B. Independent claim 1 (which is representative of claims independent 8, 15) does not include additional elements that are sufficient to amount to significantly more than the judicial exception because, when the independent claim is reevaluated as a whole, as an ordered combination under the considerations of Step 2B, the outcome is the same like under Step 2A.2. Overall, it is concluded that independent claims 1, 8, 15 are deemed ineligible. [DEPENDENT CLAIMS] Dependent claim 2, which is representative of dependent claims 9, 16, recites: grouping the multiple nodes into a group by applying a hashing function based on a node type. The elements in these dependent claims are comparable to receiving/transmitting data, processing data, storing results or transmitting data that serves merely to implement the abstract idea using computing components for performing computer functions (corresponding to the words “apply it” or an equivalent), or merely uses a computer as a tool to perform the identified abstract idea. Thus, it is concluded that these claim elements do not integrate the identified abstract idea (task scheduling based on loop optimization) into a practical application (see MPEP 2106.05(f)(2)). When considered individually, these added claim elements further elaborate on the abstract idea identified in the independent claims, because the dependent claims continue to recite the identified abstract idea. The dependent claims elements have the same relationship to the underlying abstract idea as outlined in the independent claims analysis above. It is readily clear that the dependent claim elements are not directed to any specific improvements of the independent claims and do not practically or significantly alter how the identified abstract idea would be performed. When considered as a whole, as an ordered combination, the dependent claims further elaborate on the previously identified abstract idea (task scheduling based on loop optimization). Therefore, dependent claim 2 (which is representative of dependent claims 9, 16) is deemed ineligible. As a result, it is concluded that the dependent claim elements do not integrate the identified abstract idea into a practical application (see MPEP 2106.05(f)(2)). Dependent claim 6, which is representative of dependent claims 13, 19, recites: determining a stride of the reconstructed loop based on a difference between neighboring split history offsets. The elements in these dependent claims are comparable to receiving/transmitting data, processing data, storing results or transmitting data that serves merely to implement the abstract idea using computing components for performing computer functions (corresponding to the words “apply it” or an equivalent), or merely uses a computer as a tool to perform the identified abstract idea. Thus, it is concluded that these claim elements do not integrate the identified abstract idea (task scheduling based on loop optimization) into a practical application (see MPEP 2106.05(f)(2)). When considered individually, these added claim elements further elaborate on the abstract idea identified in the independent claims, because the dependent claims continue to recite the identified abstract idea. The dependent claims elements have the same relationship to the underlying abstract idea as outlined in the independent claims analysis above. It is readily clear that the dependent claim elements are not directed to any specific improvements of the independent claims and do not practically or significantly alter how the identified abstract idea would be performed. When considered as a whole, as an ordered combination, the dependent claims further elaborate on the previously identified abstract idea (task scheduling based on loop optimization). Therefore, dependent claim 6 (which is representative of dependent claims 13, 19) is deemed ineligible. As a result, it is concluded that the dependent claim elements do not integrate the identified abstract idea into a practical application (see MPEP 2106.05(f)(2)). Dependent claim 7, which is representative of dependent claims 14, 20, recites: determining a schedule for performing operations in the ML model using one or more loop optimization techniques on the reconstructed loop. The elements in these dependent claims are comparable to receiving/transmitting data, processing data, storing results or transmitting data that serves merely to implement the abstract idea using computing components for performing computer functions (corresponding to the words “apply it” or an equivalent), or merely uses a computer as a tool to perform the identified abstract idea. Thus, it is concluded that these claim elements do not integrate the identified abstract idea (task scheduling based on loop optimization) into a practical application (see MPEP 2106.05(f)(2)). When considered individually, these added claim elements further elaborate on the abstract idea identified in the independent claims, because the dependent claims continue to recite the identified abstract idea. The dependent claims elements have the same relationship to the underlying abstract idea as outlined in the independent claims analysis above. It is readily clear that the dependent claim elements are not directed to any specific improvements of the independent claims and do not practically or significantly alter how the identified abstract idea would be performed. When considered as a whole, as an ordered combination, the dependent claims further elaborate on the previously identified abstract idea (task scheduling based on loop optimization). Therefore, dependent claim 7 (which is representative of dependent claims 14, 20) is deemed ineligible. As a result, it is concluded that the dependent claim elements do not integrate the identified abstract idea into a practical application (see MPEP 2106.05(f)(2)). Dependent claims 3-5, which are representative of dependent claims 10-12, 17-18, respectively, recite: in which the group represents identical computation expressions. in which the identical computation expressions correspond to iterations of an unrolled loop. in which the loop bounds are determined based on a split history offset of each operation in the graph. These further elements in the dependent claims do not perform any claimed method steps. They describe the nature, structure and/or content of other claim elements (in this instance – the group, the identical computation expressions, the loop bounds) and as such, cannot change the nature of the identified abstract idea (see MPEP 2106.07). The nature, form or structure of the other claim elements themselves do not practically or significantly alter how the identified abstract idea would be performed and do not provide more than a general link to a technological environment. Therefore, dependent claims 3-5, which are representative of dependent claims 10-12, 17-18, respectively, are deemed ineligible. When the dependent claims are considered as a whole, as an ordered combination, the claim elements noted above appear to merely apply the abstract concept to a technical environment in a very general sense. The most significant elements, which form the abstract concept, are set forth in the independent claims. The fact that the computing devices and the dependent claims are facilitating the abstract concept is not enough to confer statutory subject matter eligibility, since their individual and combined significance do not transform the identified abstract concept at the core of the claimed invention into eligible subject matter. Therefore, it is concluded that the dependent claims of the instant application, considered individually, or as a as a whole, as an ordered combination, do not amount to significantly more (see MPEP 2106.07(a)II). In sum, claims 1-20 are rejected under 35 USC 101 as being directed to non-statutory subject matter. Claim Interpretation The following is a quotation of 35 U.S.C. 112(f): (f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof. The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112 (f). is invoked. As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f): (A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function; (B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and (C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function. Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112 (f). The presumption that the claim limitation is interpreted under 35 U.S.C. 112 (f), is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function. Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112 (f). The presumption that the claim limitation is not interpreted under 35 U.S.C. 112 (f). is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function. Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112 (f). except as otherwise indicated in an Office Action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112 (f), except as otherwise indicated in the Office Action. This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112 (f). because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: “means for receiving a machine learning (ML) model …” in claim15; “means for assigning a value number to each node in the graph …” in claim 15; “means for reconstructing a loop for computations in the graph …” claim 15; “means for determining loop bounds of the reconstructed loop …” in claim 15. Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112 (f), it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof. If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112 (f). applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112 (f). Claim Rejections - 35 USC § 112(a) The following is a quotation of 35 U.S.C. 112(a): The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same and shall set forth the best mode contemplated by the inventor of carrying out his invention. Claims 15-20 are rejected under 35 U.S.C. 112(a) as failing to comply with the written description requirement. The claims contain subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for pre-AIA the inventor(s), at the time the application was filed, had possession of the claimed invention. Claim 15 is rejected for reciting the elements: “means for receiving a machine learning (ML) model …” in claim15; “means for assigning a value number to each node in the graph …” in claim 15; “means for reconstructing a loop for computations in the graph …” claim 15; “means for determining loop bounds of the reconstructed loop …” in claim 15. For these elements, there are no sufficient algorithms in the specification or drawings. The remainder of the claims are rejected by virtue of dependency. The reference is provided for compact prosecution purpose. Claim Rejections - 35 USC § 112(b) The following is a quotation of 35 U.S.C. 112(b): The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 15-20 are rejected under 35 U.S.C. 112(b), as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or the applicant regards as the invention. Such a claim is not sufficiently precise to provide competitors with an accurate determination of the 'metes and bounds' of the protection involved (IPXL Holdings LLC v. Amazon.com Inc., 77 USPQ2d 1140 (CA FCs 2005); Ex parte Lyell, 17 USPQ2d 1548). Claim 15 is rejected under 35 U.S.C. 112(b), as being indefinite for failing to particularly point out and distinctly claim the subject matter which applicant regards as the invention. The claim limitations “means for receiving a machine learning (ML) model …” in claim15; “means for assigning a value number to each node in the graph …” in claim 15; “means for reconstructing a loop for computations in the graph …” claim 15; “means for determining loop bounds of the reconstructed loop …” in claim 15 invoke 35 U.S.C. 112 (f). However, the written description fails to disclose the corresponding structure, material, or acts for performing the entire claimed function and to clearly link the structure, material, or acts to the function. [explanation] Therefore, the claim is indefinite and is rejected under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph. Applicant may: (a) Amend the claim so that the claim limitation will no longer be interpreted as a limitation under 35 U.S.C. 112(f); (b) Amend the written description of the specification such that it expressly recites what structure, material, or acts perform the entire claimed function, without introducing any new matter (35 U.S.C. 132(a)); or (c) Amend the written description of the specification such that it clearly links the structure, material, or acts disclosed therein to the function recited in the claim, without introducing any new matter (35 U.S.C. 132(a)). If applicant is of the opinion that the written description of the specification already implicitly or inherently discloses the corresponding structure, material, or acts and clearly links them to the function so that one of ordinary skill in the art would recognize what structure, material, or acts perform the claimed function, applicant should clarify the record by either: (a) Amending the written description of the specification such that it expressly recites the corresponding structure, material, or acts for performing the claimed function and clearly links or associates the structure, material, or acts to the claimed function, without introducing any new matter (35 U.S.C. 132(a)); or (b) Stating on the record what the corresponding structure, material, or acts, which are implicitly or inherently set forth in the written description of the specification, perform the claimed function. For more information, see 37 CFR 1.75(d) and MPEP §§ 608.01(o) and 2181. The remainder of the claims are rejected by virtue of dependency. The reference is provided for compact prosecution purpose. Examiner Remarks No art rejection has been applied to the instant set of claims. The identified prior art does not disclose at least following claim limitations: reconstructing a loop for computations in the graph based on the value number to generate a reconstructed loop; and determining loop bounds of the reconstructed loop using an affine scalar evolution analysis technique. The prior art made of record and not relied upon which, however, is considered pertinent to applicant's disclosure: US 20220147675 A1 SIRACUSA; Marco et al. METHOD OF REALIZING A HARDWARE DEVICE FOR EXECUTING OPERATIONS DEFINED BY A HIGH-LEVEL SOFTWARE CODE This disclosure provides a method to realize a hardware device, in particular a hardware device configured on a FPGA or manufactured as an ASIC, configured to meet maximum performances achievable by a certain algorithm defined by a high-level software code. The method is based on the steps of translating of the high-level software code into a corresponding low-level software code defining low-level operation, for executing the same operations defined by the high-level software code; then on estimating of certain parameters to calculate a peak performance value P and memory transfer performance Pm of the hardware device; finally, on realizing the hardware device with hardware resources having performance within the peak performance value P and memory transfer performance Pm. US 20240411967 A1 Yu; Lin-Ya et al. HIGH-LEVEL SYNTHESIS OF DESIGNS USING LOOP-AWARE EXECUTION INFORMATION High-level synthesis of designs using loop-aware execution information includes generating, using computer hardware, an intermediate representation (IR) of a design specified in a high-level programming language. The design is for an integrated circuit. Execution information analysis is performed on the IR of the design generating analysis results for functions of the design. The analysis results of the design are transformed by embedding the analysis results in a plurality of regions of the IR of the design. Selected regions of the plurality of regions are merged based on the analysis results, as embedded, for the selected regions. The IR of the design is scheduled using the analysis results subsequent to the merging. US 20220400272 A1 LIN; Sheng et al. CONTENT-ADAPTIVE ONLINE TRAINING FOR DNN-BASED CROSS COMPONENT PREDICTION WITH SCALING FACTORS A method and apparatus for neural network based cross component prediction with scaling factors during encoding or decoding of an image frame or a video sequence, which may include training a deep neural network (DNN) cross component prediction (CCP) model with at least one or more scaling factors, wherein the at least one or more scaling factors are learned by optimizing a rate-distortion loss based on an input video sequence comprising a luma component, and reconstructing a chroma component based on the luma component using the trained DNN CCP model with the at least one or more scaling factors for chroma prediction. The trained DNN CCP may be updated for chroma prediction of the input video sequence using the one or more scaling factors, and performing chroma prediction of the input video sequence using the updated DNN CCP model with the one or more scaling factors. US 20240248716 A1 Cui; Shimin et al. Predictive Dead Store Elimination Predictive dead store elimination is provided. The method comprises identifying, in a program, a first store operation and a second store operation in a program loop that comprise a store pair with a same loop-invariant base address and determining whether the store pair is a predictive dead store elimination candidate. Responsive to a determination that the store pair is a predictive dead store elimination candidate, the method eliminates the first store operation in each iteration of the program loop, except the last DSRC (dead store recurrence constant) iterations and sinks the first store operation in the last DSRC iterations to after the program loop. US 20180314506 A1 Shahid; Md Asghar Ahmad et al. METHOD AND APPARATUS FOR COMPILING COMPUTER-READABLE COMPUTER PROGRAMS USING EXTENDED ISOMORPHISM A method and apparatus provides for compiling a computer-readable computer program having a plurality of computer-readable statements into a plurality of computer-executable instructions. In one example, the method and apparatus determines when at least one pair of the computer-readable statements is partial-isomorphic having an equivalent operation and same order of operation but causing non-consecutive memory accesses, and generates the computer-executable instructions causing the at least one pair of the partial-isomorphic statements to perform sequential physical memory accesses. US 20220174281 A1 JIANG; Wei et al. END-TO-END DEPENDENT QUANTIZATION WITH DEEP REINFORCEMENT LEARNING There is included a method and apparatus comprising computer code configured to cause a processor or processors to perform obtaining an input stream of video data, computing a key based on a floating number in the input stream, predicting a current dependent quantization (DQ) state based on a state predictor and a number of previous keys and a number of previous DQ states, reconstructing the floating number based on the key and the current DQ state, and coding the video based on the reconstructed floating number. US 20240329957 A1 LIU; Bangtian et al. CONTROL FLOW AUTO-VECTORIZATION USING RUN-TIME CHECKS AND COMPILE-TIME ANALYSIS Vectorization of program code by way of a method that includes obtaining program code to be compiled. The program code has a loop that includes a control-flow having divergent branch conditions. The method includes compiling the program code to produce compiled code. The compiling includes performing compile-time analysis of the loop based on an assumption of dynamic uniformity, and determining from the analysis a vectorizable access pattern of the loop. The compiling also includes vectorizing the loop as part of the compiling the program code, including compiling the loop. The vectorizing includes providing run-time checks in the compiled code. The run-time checks are configured for checking for dynamically uniform conditions for vector processing at run-time to control program execution flow based on a result of the checking. The method also includes outputting the compiled code for execution. US 20220400273 A1 LIN; Sheng et al. CONTENT-ADAPTIVE ONLINE TRAINING FOR DNN-BASED CROSS COMPONENT PREDICTION WITH LOW-BIT PRECISION A method and apparatus for neural network based cross component prediction with low-bit precision during encoding or decoding of an image frame or a video sequence, which may include reconstructing a chroma component based on a received luma component using a pre-trained deep neural network (DNN) cross component prediction (CCP) model for chroma prediction, and updating a set of parameters of the pre-trained DNN CCP model with low-bit precision. The method may also include generating an updated DNN CCP model for chroma prediction with low-bit precision based on at least one video sequence, and using the updated DNN CCP model for cross component prediction of the at least one video sequence at reduced processing time. US 20240241704 A1 Chen; Zheng et al. REDUCING REGISTER PRESSURE A computer-implemented method, system and computer program product for reducing register pressure. Loops of a computer program with a number of live variables that exceeds a threshold number, such as the number of available registers with capacity to store data, are identified. Such identified loops may be the to be subject to high register pressure. Upon identifying such loops in the computer program, chains within each identified loop are identified, where each chain includes load and store instructions from the same induction address and where the variable offsets of the load and store instructions are loop invariants. The address expressions for the load and store instructions in the identified chains may then be modified or changed to reuse common variable offsets using an analysis and transformation process. By reusing common variable offsets, there are less variable offsets that need to be stored in the registers thereby mitigating register pressure. Inquiries Any inquiry concerning this communication or earlier communications from the examiner should be directed to Radu Andrei whose telephone number is 313.446.4948. The examiner can normally be reached on Monday – Friday 8:30am – 5pm EST. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, John Hayes can be reached at 571.272.6708. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http:/www.uspto.gov/interviewpractice. As disclosed in MPEP 502.03, communications via Internet e-mail are at the discretion of the applicant. Without a written authorization by applicant in place, the USPTO will not respond via Internet e-mail to any Internet correspondence which contains information subject to the confidentiality requirement as set forth in 35 U.S.C. 122. A paper copy of such correspondence will be placed in the appropriate patent application. The following is a sample authorization form which may be used by applicant: “Recognizing that Internet communications are not secure, I hereby authorize the USPTO to communicate with me concerning any subject matter of this application by electronic mail. I understand that a copy of these communications will be made of record in the application file.” Information regarding the status of published or unpublished applications may be obtained from Patent Center. Status information for published applications may be obtained from Patent Center information webpage. Status information for unpublished applications is available to registered users through Patent Center information webpage only. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (in USA or CANADA) or 571-272-1000. Any response to this action should be mailed to: Commissioner of Patents and Trademarks P.O. Box 1450 Alexandria, VA 22313-1450 or faxed to 571-273-8300 /Radu Andrei/ Primary Examiner, AU 3697
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Prosecution Timeline

Feb 29, 2024
Application Filed
Aug 05, 2026
Non-Final Rejection mailed — §101, §112 (current)

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Prosecution Projections

1-2
Expected OA Rounds
37%
Grant Probability
57%
With Interview (+20.3%)
3y 4m (~11m remaining)
Median Time to Grant
Low
PTA Risk
Based on 582 resolved cases by this examiner. Grant probability derived from career allowance rate.

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